"!TARGET_5200"
"or%.b %1,%0")
+;; On all 68k models, this makes faster code in a special case.
+;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
+
+(define_insn "iorsi_zexthi_ashl16"
+ [(set (match_operand:SI 0 "general_operand" "=d,d")
+ (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dmn,dmn"))
+ (ashift:SI (match_operand:SI 2 "general_operand" "o,0")
+ (const_int 16))))]
+ ""
+ "*
+{
+ CC_STATUS_INIT;
+ if (GET_CODE (operands[2]) != REG)
+ {
+ operands[2] = adj_offsettable_operand (operands[2], 2);
+ output_asm_insn (\"move%.w %2,%0\", operands);
+ }
+ return \"swap %0\;mov%.w %1,%0\";
+}")
+
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=o,d")
(ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
;; On all 68k models, this makes faster code in a special case.
-(define_insn ""
+(define_insn "ashrsi_16"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
(const_int 16)))]