X86: Implement SHLD.

diff --git a/src/arch/x86/isa/decoder/two_byte_opcodes.isa b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
index 401e029652d3484f35c0644f8204fde54eed4bab..c47fb5184fb89e38adb191d49b6918ec40969e53 100644 (file)
--- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa
+++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa
@@ -820,8 +820,8 @@
                     Rdx = result.rdx;
                     }});
                 0x3: Inst::BT(Ev,Gv);
-                0x4: shld_Ev_Gv_Ib();
-                0x5: shld_Ev_Gv_rCl();
+                0x4: Inst::SHLD(Ev,Gv,Ib);
+                0x5: Inst::SHLD(Ev,Gv);
                 0x6: xbts_and_cmpxchg();
                 0x7: ibts_and_cmpxchg();
             }

diff --git a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
index caaeca974f10da740d88c3957bf5e6865bd8c1ce..d2a579ecb3270d65bdd04794916b78e2edb59644 100644 (file)
--- a/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
+++ b/src/arch/x86/isa/insts/general_purpose/rotate_and_shift/shift.py
@@ -114,6 +114,52 @@ def macroop SAL_P_R
     st t1, seg, riprel, disp
 };
 
+def macroop SHLD_R_R
+{
+    mdbi regm, 0
+    sld reg, reg, rcx, flags=(CF,OF,SF,ZF,PF)
+};
+
+def macroop SHLD_M_R
+{
+    ldst t1, seg, sib, disp
+    mdbi reg, 0
+    sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
+    st t1, seg, sib, disp
+};
+
+def macroop SHLD_P_R
+{
+    rdip t7
+    ldst t1, seg, riprel, disp
+    mdbi reg, 0
+    sld t1, t1, rcx, flags=(CF,OF,SF,ZF,PF)
+    st t1, seg, riprel, disp
+};
+
+def macroop SHLD_R_R_I
+{
+    mdbi regm, 0
+    sldi reg, reg, imm, flags=(CF,OF,SF,ZF,PF)
+};
+
+def macroop SHLD_M_R_I
+{
+    ldst t1, seg, sib, disp
+    mdbi reg, 0
+    sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
+    st t1, seg, sib, disp
+};
+
+def macroop SHLD_P_R_I
+{
+    rdip t7
+    ldst t1, seg, riprel, disp
+    mdbi reg, 0
+    sldi t1, t1, imm, flags=(CF,OF,SF,ZF,PF)
+    st t1, seg, riprel, disp
+};
+
 def macroop SHR_R_I
 {
     srli reg, reg, imm, flags=(CF,OF,SF,ZF,PF)