if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
return;
- radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
- radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
+ radeon_set_context_reg_seq(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, 1);
radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
- radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
-
radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
/* GFX9: Flush DFSM when the AA mode changes. */
radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
+ radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
+ radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
/* The exclusion bits can be set to improve rasterization efficiency
* if no sample lies on the pixel boundary (-8 sample offset). It's