radv: move emission of two PA_SC_* registers to the pipeline CS
authorSamuel Pitoiset <samuel.pitoiset@gmail.com>
Fri, 6 Dec 2019 11:12:38 +0000 (12:12 +0100)
committerSamuel Pitoiset <samuel.pitoiset@gmail.com>
Tue, 10 Dec 2019 10:04:40 +0000 (11:04 +0100)
They don't have to be updated dynamically.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
src/amd/vulkan/radv_cmd_buffer.c
src/amd/vulkan/radv_pipeline.c

index d655f6e2313a0812feab7e83b6d46f0159f09c18..5850172d127509a960be79a542e82a38b91b4113 100644 (file)
@@ -874,12 +874,9 @@ radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer,
        if (old_pipeline && num_samples == old_pipeline->graphics.ms.num_samples)
                return;
 
-       radeon_set_context_reg_seq(cmd_buffer->cs, R_028BDC_PA_SC_LINE_CNTL, 2);
-       radeon_emit(cmd_buffer->cs, ms->pa_sc_line_cntl);
+       radeon_set_context_reg_seq(cmd_buffer->cs, R_028BE0_PA_SC_AA_CONFIG, 1);
        radeon_emit(cmd_buffer->cs, ms->pa_sc_aa_config);
 
-       radeon_set_context_reg(cmd_buffer->cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
-
        radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);
 
        /* GFX9: Flush DFSM when the AA mode changes. */
index 95b1684fdf827da35a185464718299471592db05..aa97137c7fd696d7941ea6d6074af048b92a67da 100644 (file)
@@ -3648,7 +3648,9 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
        radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
 
        radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
+       radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
        radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
+       radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
 
        /* The exclusion bits can be set to improve rasterization efficiency
         * if no sample lies on the pixel boundary (-8 sample offset). It's