dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
}
break;
+ case nir_intrinsic_load_local_group_size:
+ for (int i = 0; i < intr->num_components; i++) {
+ dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
+ }
+ break;
case nir_intrinsic_discard_if:
case nir_intrinsic_discard: {
struct ir3_instruction *cond, *kill;
[IR3_DP_NUM_WORK_GROUPS_X] = info->grid[0],
[IR3_DP_NUM_WORK_GROUPS_Y] = info->grid[1],
[IR3_DP_NUM_WORK_GROUPS_Z] = info->grid[2],
- /* do we need work-group-size? */
+ [IR3_DP_LOCAL_GROUP_SIZE_X] = info->block[0],
+ [IR3_DP_LOCAL_GROUP_SIZE_Y] = info->block[1],
+ [IR3_DP_LOCAL_GROUP_SIZE_Z] = info->block[2],
};
ctx->emit_const(ring, SHADER_COMPUTE, offset * 4, 0,
IR3_DP_NUM_WORK_GROUPS_X = 0,
IR3_DP_NUM_WORK_GROUPS_Y = 1,
IR3_DP_NUM_WORK_GROUPS_Z = 2,
+ IR3_DP_LOCAL_GROUP_SIZE_X = 4,
+ IR3_DP_LOCAL_GROUP_SIZE_Y = 5,
+ IR3_DP_LOCAL_GROUP_SIZE_Z = 6,
/* NOTE: gl_NumWorkGroups should be vec4 aligned because
* glDispatchComputeIndirect() needs to load these from
* the info->indirect buffer. Keep that in mind when/if
* adding any addition CS driver params.
*/
- IR3_DP_CS_COUNT = 4, /* must be aligned to vec4 */
+ IR3_DP_CS_COUNT = 8, /* must be aligned to vec4 */
/* vertex shader driver params: */
IR3_DP_VTXID_BASE = 0,