brw_gs_state.c \
brw_misc_state.c \
brw_pipe_blend.c \
- brw_pipe_debug.c \
brw_pipe_depth.c \
brw_pipe_fb.c \
brw_pipe_flush.c \
brw_wm_surface_state.c \
brw_bo.c \
intel_batchbuffer.c \
- intel_tex_format.c \
intel_tex_layout.c
include ../../Makefile.template
#include "brw_types.h"
#include "brw_winsys.h"
#include "brw_reg.h"
+#include "util/u_debug.h"
#define BATCH_SZ 16384
#define BATCH_RESERVED 16
static INLINE boolean
brw_batchbuffer_require_space(struct brw_batchbuffer *batch,
- GLuint sz,
- enum cliprect_mode cliprect_mode)
+ GLuint sz)
{
assert(sz < batch->size - 8);
if (brw_batchbuffer_space(batch) < sz) {
assert(0);
return FALSE;
}
-
- /* All commands should be executed once regardless of cliprect
- * mode.
- */
- (void)cliprect_mode;
+#ifdef DEBUG
+ batch->emit.end_ptr = batch->ptr + sz;
+#endif
+ return TRUE;
}
/* Here are the crusty old macros, to be removed:
*/
-#define BATCH_LOCALS
-
#define BEGIN_BATCH(n, cliprect_mode) do { \
- brw_batchbuffer_require_space(intel->batch, (n)*4, cliprect_mode); \
- assert(intel->batch->emit.start_ptr == NULL); \
- intel->batch->emit.total = (n) * 4; \
- intel->batch->emit.start_ptr = intel->batch->ptr; \
+ brw_batchbuffer_require_space(brw->batch, (n)*4); \
} while (0)
-#define OUT_BATCH(d) brw_batchbuffer_emit_dword(intel->batch, d)
+#define OUT_BATCH(d) brw_batchbuffer_emit_dword(brw->batch, d)
#define OUT_RELOC(buf, read_domains, write_domain, delta) do { \
assert((unsigned) (delta) < buf->size); \
- brw_batchbuffer_emit_reloc(intel->batch, buf, \
+ brw_batchbuffer_emit_reloc(brw->batch, buf, \
read_domains, write_domain, delta); \
} while (0)
+#ifdef DEBUG
#define ADVANCE_BATCH() do { \
- unsigned int _n = intel->batch->ptr - intel->batch->emit.start_ptr; \
- assert(intel->batch->emit.start_ptr != NULL); \
- if (_n != intel->batch->emit.total) { \
- fprintf(stderr, "ADVANCE_BATCH: %d of %d dwords emitted\n", \
- _n, intel->batch->emit.total); \
+ unsigned int _n = brw->batch->ptr - brw->batch->emit.end_ptr; \
+ if (_n != 0) { \
+ debug_printf("%s: %d too many bytes emitted to batch\n", __FUNCTION__, _n); \
abort(); \
} \
- intel->batch->emit.start_ptr = NULL; \
+ brw->batch->emit.end_ptr = NULL; \
} while(0)
-
+#else
+#define ADVANCE_BATCH()
+#endif
static INLINE void
brw_batchbuffer_emit_mi_flush(struct brw_batchbuffer *batch)
{
- brw_batchbuffer_require_space(batch, 4, IGNORE_CLIPRECTS);
+ brw_batchbuffer_require_space(batch, 4);
brw_batchbuffer_emit_dword(batch, MI_FLUSH);
}
cc_unit_populate_key(const struct brw_context *brw,
struct brw_cc_unit_key *key)
{
- key->cc0 = brw->curr.dsa->cc0;
- key->cc1 = brw->curr.dsa->cc1;
- key->cc2 = brw->curr.dsa->cc2;
- key->cc3 = combine_cc3( brw->curr.dsa->cc3, brw->curr.blend->cc3 );
+ key->cc0 = brw->curr.zstencil->cc0;
+ key->cc1 = brw->curr.zstencil->cc1;
+ key->cc2 = brw->curr.zstencil->cc2;
+ key->cc3 = combine_cc3( brw->curr.zstencil->cc3, brw->curr.blend->cc3 );
key->cc5 = brw->curr.blend->cc5;
key->cc6 = brw->curr.blend->cc6;
key->cc7 = brw->curr.blend->cc7;
c.func.single_program_flow = 1;
+ c.chipset = brw->chipset;
c.key = *key;
- c.need_ff_sync = BRW_IS_IGDNG(brw);
+ c.need_ff_sync = c.chipset.is_igdng;
/* Need to locate the two positions present in vertex + header.
* These are currently hardcoded:
*/
c.header_position_offset = ATTR_SIZE;
- if (BRW_IS_IGDNG(brw))
+ if (c.chipset.is_igdng)
delta = 3 * REG_SIZE;
else
delta = REG_SIZE;
key.primitive = brw->reduced_primitive;
/* PIPE_NEW_VS */
- key.nr_attrs = brw->curr.vs->info.file_max[TGSI_FILE_OUTPUT] + 1;
+ key.nr_attrs = brw->curr.vertex_shader->info.file_max[TGSI_FILE_OUTPUT] + 1;
/* PIPE_NEW_CLIP */
key.nr_userclip = brw->curr.ucp.nr;
#ifndef BRW_CLIP_H
#define BRW_CLIP_H
-
-#include "brw_context.h"
+#include "pipe/p_state.h"
+#include "brw_reg.h"
#include "brw_eu.h"
#define MAX_VERTS (3+6+6)
GLfloat offset_units;
};
+struct brw_clip_prog_data {
+ GLuint curb_read_length; /* user planes? */
+ GLuint clip_mode;
+ GLuint urb_read_length;
+ GLuint total_grf;
+};
#define CLIP_LINE 0
#define CLIP_POINT 1
GLuint last_tmp;
GLboolean need_direction;
+ struct brw_chipset chipset;
GLuint last_mrf;
GLuint header_position_offset;
GLuint offset[PIPE_MAX_SHADER_OUTPUTS];
GLboolean need_ff_sync;
+
+ GLuint nr_color_attrs;
+ GLuint offset_color0;
+ GLuint offset_color1;
+ GLuint offset_bfc0;
+ GLuint offset_bfc1;
+
+ GLuint offset_edge;
};
#define ATTR_SIZE (4*4)
* Keith Whitwell <keith@tungstengraphics.com>
*/
+#include "util/u_debug.h"
+
#include "brw_defines.h"
-#include "brw_context.h"
#include "brw_eu.h"
#include "brw_util.h"
#include "brw_clip.h"
+
static void brw_clip_line_alloc_regs( struct brw_clip_compile *c )
{
GLuint i = 0,j;
struct brw_instruction *is_neg2 = NULL;
struct brw_instruction *not_culled;
struct brw_reg v1_null_ud = retype(vec1(brw_null_reg()), BRW_REGISTER_TYPE_UD);
+ const int hpos = 0; /* XXX: position not always first element */
brw_MOV(p, get_addr_reg(vtx0), brw_address(c->reg.vertex[0]));
brw_MOV(p, get_addr_reg(vtx1), brw_address(c->reg.vertex[1]));
brw_clip_init_clipmask(c);
/* -ve rhw workaround */
- if (BRW_IS_965(p->brw)) {
+ if (c->chipset.is_965) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
/* dp = DP4(vtx->position, plane)
*/
- brw_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, c->offset[VERT_RESULT_HPOS]), c->reg.plane_equation);
+ brw_DP4(p, vec4(c->reg.dp0), deref_4f(vtx0, c->offset[hpos]), c->reg.plane_equation);
/* if (IS_NEGATIVE(dp1))
*/
brw_set_conditionalmod(p, BRW_CONDITIONAL_L);
- brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, c->offset[VERT_RESULT_HPOS]), c->reg.plane_equation);
+ brw_DP4(p, vec4(c->reg.dp1), deref_4f(vtx1, c->offset[hpos]), c->reg.plane_equation);
is_negative = brw_IF(p, BRW_EXECUTE_1);
{
/*
* Both can be negative on GM965/G965 due to RHW workaround
* if so, this object should be rejected.
*/
- if (BRW_IS_965(p->brw)) {
+ if (c->chipset.is_965) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_LE, c->reg.dp0, brw_imm_f(0.0));
is_neg2 = brw_IF(p, BRW_EXECUTE_1);
{
/* If both are positive, do nothing */
/* Only on GM965/G965 */
- if (BRW_IS_965(p->brw)) {
+ if (c->chipset.is_965) {
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.dp0, brw_imm_f(0.0));
is_neg2 = brw_IF(p, BRW_EXECUTE_1);
}
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
- if (BRW_IS_965(p->brw)) {
+ if (c->chipset.is_965) {
brw_ENDIF(p, is_neg2);
}
}
brw_CMP(p, vec1(brw_null_reg()), BRW_CONDITIONAL_L, c->reg.t, brw_imm_f(1.0));
not_culled = brw_IF(p, BRW_EXECUTE_1);
{
- brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, GL_FALSE);
- brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, GL_FALSE);
+ brw_clip_interp_vertex(c, newvtx0, vtx0, vtx1, c->reg.t0, FALSE);
+ brw_clip_interp_vertex(c, newvtx1, vtx1, vtx0, c->reg.t1, FALSE);
brw_clip_emit_vue(c, newvtx0, 1, 0, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_START);
brw_clip_emit_vue(c, newvtx1, 0, 1, (_3DPRIM_LINESTRIP << 2) | R02_PRIM_END);
*/
#include "brw_defines.h"
-#include "brw_context.h"
#include "brw_eu.h"
#include "brw_util.h"
#include "brw_clip.h"
* Keith Whitwell <keith@tungstengraphics.com>
*/
+#include "util/u_math.h"
+
#include "brw_context.h"
+#include "brw_clip.h"
#include "brw_state.h"
#include "brw_defines.h"
+#include "brw_debug.h"
struct brw_clip_unit_key {
unsigned int total_grf;
memset(&clip, 0, sizeof(clip));
- clip.thread0.grf_reg_count = ALIGN(key->total_grf, 16) / 16 - 1;
+ clip.thread0.grf_reg_count = align(key->total_grf, 16) / 16 - 1;
/* reloc */
clip.thread0.kernel_start_pointer = brw->clip.prog_bo->offset >> 6;
clip.thread4.max_threads = 1 - 1;
}
- if (INTEL_DEBUG & DEBUG_SINGLE_THREAD)
+ if (BRW_DEBUG & DEBUG_SINGLE_THREAD)
clip.thread4.max_threads = 0;
- if (INTEL_DEBUG & DEBUG_STATS)
+ if (BRW_DEBUG & DEBUG_STATS)
clip.thread4.stats_enable = 1;
clip.clip5.userclip_enable_flags = 0x7f;
/* Emit clip program relocation */
assert(brw->clip.prog_bo);
- dri_bo_emit_reloc(bo,
- I915_GEM_DOMAIN_INSTRUCTION,
- 0,
- clip.thread0.grf_reg_count << 1,
- offsetof(struct brw_clip_unit_state, thread0),
- brw->clip.prog_bo);
+ brw->sws->bo_emit_reloc(bo,
+ I915_GEM_DOMAIN_INSTRUCTION,
+ 0,
+ clip.thread0.grf_reg_count << 1,
+ offsetof(struct brw_clip_unit_state, thread0),
+ brw->clip.prog_bo);
return bo;
}
*/
#include "brw_defines.h"
-#include "brw_context.h"
#include "brw_eu.h"
#include "brw_util.h"
#include "brw_clip.h"
for (j = 0; j < 3; j++) {
GLuint delta = c->nr_attrs*16 + 32;
- if (BRW_IS_IGDNG(c->func.brw))
+ if (c->chipset.is_igdng)
delta = c->nr_attrs * 16 + 32 * 3;
brw_MOV(&c->func, byte_offset(c->reg.vertex[j], delta), brw_imm_f(0));
/* if -ve rhw workaround bit is set,
do cliptest */
- if (BRW_IS_965(p->brw)) {
+ if (c->chipset.is_965) {
brw_set_conditionalmod(p, BRW_CONDITIONAL_NZ);
brw_AND(p, brw_null_reg(), get_element_ud(c->reg.R0, 2),
brw_imm_ud(1<<20));
* Keith Whitwell <keith@tungstengraphics.com>
*/
-#include "brw_batchbuffer.h"
-
#include "brw_defines.h"
-#include "brw_context.h"
#include "brw_eu.h"
#include "brw_util.h"
#include "brw_clip.h"
/* Do we have any colors to copy?
*/
- if (!(c->offset[VERT_RESULT_COL0] && c->offset[VERT_RESULT_BFC0]) &&
- !(c->offset[VERT_RESULT_COL1] && c->offset[VERT_RESULT_BFC1]))
+ if (c->nr_color_attrs == 0)
return;
/* In some wierd degnerate cases we can end up testing the
GLuint i;
for (i = 0; i < 3; i++) {
- if (c->offset[VERT_RESULT_COL0] && c->offset[VERT_RESULT_BFC0])
+ if (c->offset_color0 && c->offset_bfc0)
brw_MOV(p,
- byte_offset(c->reg.vertex[i], c->offset[VERT_RESULT_COL0]),
- byte_offset(c->reg.vertex[i], c->offset[VERT_RESULT_BFC0]));
+ byte_offset(c->reg.vertex[i], c->offset_color0),
+ byte_offset(c->reg.vertex[i], c->offset_bfc0));
- if (c->offset[VERT_RESULT_COL1] && c->offset[VERT_RESULT_BFC1])
+ if (c->offset_color1 && c->offset_bfc1)
brw_MOV(p,
- byte_offset(c->reg.vertex[i], c->offset[VERT_RESULT_COL1]),
- byte_offset(c->reg.vertex[i], c->offset[VERT_RESULT_BFC1]));
+ byte_offset(c->reg.vertex[i], c->offset_color0),
+ byte_offset(c->reg.vertex[i], c->offset_bfc0));
}
}
brw_ENDIF(p, ccw);
{
brw_set_conditionalmod(p, BRW_CONDITIONAL_EQ);
brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<8));
- brw_MOV(p, byte_offset(c->reg.vertex[0], c->offset[VERT_RESULT_EDGE]), brw_imm_f(0));
+ brw_MOV(p, byte_offset(c->reg.vertex[0], c->offset_edge), brw_imm_f(0));
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
brw_set_conditionalmod(p, BRW_CONDITIONAL_EQ);
brw_AND(p, vec1(brw_null_reg()), get_element_ud(c->reg.R0, 2), brw_imm_ud(1<<9));
- brw_MOV(p, byte_offset(c->reg.vertex[2], c->offset[VERT_RESULT_EDGE]), brw_imm_f(0));
+ brw_MOV(p, byte_offset(c->reg.vertex[2], c->offset_edge), brw_imm_f(0));
brw_set_predicate_control(p, BRW_PREDICATE_NONE);
}
brw_ENDIF(p, is_poly);
/* draw edge if edgeflag != 0 */
brw_CMP(p,
vec1(brw_null_reg()), BRW_CONDITIONAL_NZ,
- deref_1f(v0, c->offset[VERT_RESULT_EDGE]),
+ deref_1f(v0, c->offset_edge),
brw_imm_f(0));
draw_edge = brw_IF(p, BRW_EXECUTE_1);
{
*/
brw_CMP(p,
vec1(brw_null_reg()), BRW_CONDITIONAL_NZ,
- deref_1f(v0, c->offset[VERT_RESULT_EDGE]),
+ deref_1f(v0, c->offset_edge),
brw_imm_f(0));
draw_point = brw_IF(p, BRW_EXECUTE_1);
{
brw_clip_tri_init_vertices(c);
brw_clip_init_ff_sync(c);
- assert(c->offset[VERT_RESULT_EDGE]);
+ assert(c->offset_edge);
if (c->key.fill_ccw == CLIP_CULL &&
c->key.fill_cw == CLIP_CULL) {
#include "brw_defines.h"
-#include "brw_context.h"
#include "brw_eu.h"
#include "brw_util.h"
#include "brw_clip.h"
for (i = 0; i < c->nr_attrs; i++) {
GLuint delta = i*16 + 32;
- if (BRW_IS_IGDNG(p->brw))
+ if (c->chipset.is_igdng)
delta = i * 16 + 32 * 3;
- if (delta == c->offset[VERT_RESULT_EDGE]) {
+ if (delta == c->offset_edge) {
if (force_edgeflag)
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(1));
else
if (i & 1) {
GLuint delta = i*16 + 32;
- if (BRW_IS_IGDNG(p->brw))
+ if (c->chipset.is_igdng)
delta = i * 16 + 32 * 3;
brw_MOV(p, deref_4f(dest_ptr, delta), brw_imm_f(0));
{
struct brw_compile *p = &c->func;
- if (c->offset[VERT_RESULT_COL0])
+ if (c->offset_color0)
brw_MOV(p,
- byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL0]),
- byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL0]));
+ byte_offset(c->reg.vertex[to], c->offset_color0),
+ byte_offset(c->reg.vertex[from], c->offset_color0));
- if (c->offset[VERT_RESULT_COL1])
+ if (c->offset_color1)
brw_MOV(p,
- byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_COL1]),
- byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_COL1]));
+ byte_offset(c->reg.vertex[to], c->offset_color1),
+ byte_offset(c->reg.vertex[from], c->offset_color1));
- if (c->offset[VERT_RESULT_BFC0])
+ if (c->offset_bfc0)
brw_MOV(p,
- byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC0]),
- byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC0]));
+ byte_offset(c->reg.vertex[to], c->offset_bfc0),
+ byte_offset(c->reg.vertex[from], c->offset_bfc0));
- if (c->offset[VERT_RESULT_BFC1])
+ if (c->offset_bfc1)
brw_MOV(p,
- byte_offset(c->reg.vertex[to], c->offset[VERT_RESULT_BFC1]),
- byte_offset(c->reg.vertex[from], c->offset[VERT_RESULT_BFC1]));
+ byte_offset(c->reg.vertex[to], c->offset_bfc1),
+ byte_offset(c->reg.vertex[from], c->offset_bfc1));
}
#include "pipe/p_context.h"
+#include "util/u_simple_list.h"
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_draw.h"
#include "brw_state.h"
-#include "brw_vs.h"
-#include "brw_screen_tex.h"
#include "brw_batchbuffer.h"
+#include "brw_winsys.h"
-
-
-struct pipe_context *brw_create_context( struct pipe_screen *screen,
- void *priv )
-{
- struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context);
-
- if (!brw) {
- debug_printf("%s: failed to alloc context\n", __FUNCTION__);
- return GL_FALSE;
- }
-
- /* We want the GLSL compiler to emit code that uses condition codes */
- ctx->Shader.EmitCondCodes = GL_TRUE;
- ctx->Shader.EmitNVTempInitialization = GL_TRUE;
-
-
- brw_init_query( brw );
- brw_init_state( brw );
- brw_draw_init( brw );
-
- brw->state.dirty.mesa = ~0;
- brw->state.dirty.brw = ~0;
-
- brw->emit_state_always = 0;
-
- make_empty_list(&brw->query.active_head);
-
-
- return GL_TRUE;
-}
-
-/**
- * called from intelDestroyContext()
- */
-static void brw_destroy_context( struct brw_context *brw )
+static void brw_destroy_context( struct pipe_context *pipe )
{
+ struct brw_context *brw = brw_context(pipe);
int i;
brw_destroy_state(brw);
- brw_draw_destroy( brw );
- _mesa_free(brw->wm.compile_data);
+ brw_draw_cleanup( brw );
+
+ FREE(brw->wm.compile_data);
- for (i = 0; i < brw->state.nr_color_regions; i++)
- intel_region_release(&brw->state.color_regions[i]);
- brw->state.nr_color_regions = 0;
- intel_region_release(&brw->state.depth_region);
+ for (i = 0; i < brw->curr.fb.nr_cbufs; i++)
+ pipe_surface_reference(&brw->curr.fb.cbufs[i], NULL);
+ brw->curr.fb.nr_cbufs = 0;
+ pipe_surface_reference(&brw->curr.fb.zsbuf, NULL);
brw->sws->bo_unreference(brw->curbe.curbe_bo);
brw->sws->bo_unreference(brw->vs.prog_bo);
brw->sws->bo_unreference(brw->cc.state_bo);
brw->sws->bo_unreference(brw->cc.vp_bo);
}
+
+
+struct pipe_context *brw_create_context(struct pipe_screen *screen)
+{
+ struct brw_context *brw = (struct brw_context *) CALLOC_STRUCT(brw_context);
+
+ if (!brw) {
+ debug_printf("%s: failed to alloc context\n", __FUNCTION__);
+ return GL_FALSE;
+ }
+
+ /* We want the GLSL compiler to emit code that uses condition codes */
+ //ctx->Shader.EmitCondCodes = GL_TRUE;
+ //ctx->Shader.EmitNVTempInitialization = GL_TRUE;
+
+ brw->base.destroy = brw_destroy_context;
+
+ brw_init_query( brw );
+ brw_init_state( brw );
+ brw_draw_init( brw );
+
+ brw->state.dirty.mesa = ~0;
+ brw->state.dirty.brw = ~0;
+
+ brw->emit_state_always = 0;
+
+ make_empty_list(&brw->query.active_head);
+
+
+ return &brw->base;
+}
+
#include "brw_structs.h"
#include "brw_winsys.h"
+#include "brw_reg.h"
#include "pipe/p_state.h"
#include "pipe/p_context.h"
#include "tgsi/tgsi_scan.h"
#define PIPE_NEW_VERTEX_ELEMENT 0x2
#define PIPE_NEW_FRAGMENT_SHADER 0x2
#define PIPE_NEW_VERTEX_SHADER 0x2
-#define PIPE_NEW_FRAGMENT_CONSTS 0x2
-#define PIPE_NEW_VERTEX_CONSTS 0x2
+#define PIPE_NEW_FRAGMENT_CONSTANTS 0x2
+#define PIPE_NEW_VERTEX_CONSTANTS 0x2
#define PIPE_NEW_CLIP 0x2
GLuint urb_entry_size;
};
-struct brw_clip_prog_data {
- GLuint curb_read_length; /* user planes? */
- GLuint clip_mode;
- GLuint urb_read_length;
- GLuint total_grf;
-};
+
+struct brw_clip_prog_data;
struct brw_gs_prog_data {
GLuint urb_read_length;
* This contains pointers to the drawing surfaces and current texture
* objects and shader constant buffers (+2).
*/
-#define BRW_WM_MAX_SURF (MAX_DRAW_BUFFERS + BRW_MAX_TEX_UNIT + 1)
+#define BRW_WM_MAX_SURF (PIPE_MAX_COLOR_BUFS + BRW_MAX_TEX_UNIT + 1)
/**
* Helpers to convert drawing buffers, textures and constant buffers
* to surface binding table indexes, for WM.
*/
#define SURF_INDEX_DRAW(d) (d)
-#define SURF_INDEX_FRAG_CONST_BUFFER (MAX_DRAW_BUFFERS)
-#define SURF_INDEX_TEXTURE(t) (MAX_DRAW_BUFFERS + 1 + (t))
+#define SURF_INDEX_FRAG_CONST_BUFFER (PIPE_MAX_COLOR_BUFS)
+#define SURF_INDEX_TEXTURE(t) (PIPE_MAX_COLOR_BUFS + 1 + (t))
/**
* Size of surface binding table for the VS.
*/
struct brw_context
{
- struct pipe_context pipe;
+ struct pipe_context base;
+ struct brw_chipset chipset;
struct brw_screen *brw_screen;
struct brw_winsys_screen *sws;
+ struct brw_batchbuffer *batch;
+
GLuint primitive;
GLuint reduced_primitive;
GLboolean emit_state_always;
- GLboolean no_batch_wrap;
/* Active vertex program:
*/
struct {
- const struct brw_vertex_shader *vs;
- const struct brw_fragment_shader *fs;
+ const struct brw_vertex_shader *vertex_shader;
+ const struct brw_fragment_shader *fragment_shader;
const struct brw_blend_state *blend;
const struct brw_rasterizer_state *rast;
- const struct brw_depth_stencil_alpha_state *dsa;
+ const struct brw_depth_stencil_alpha_state *zstencil;
struct pipe_framebuffer_state fb;
struct pipe_viewport_state vp;
struct pipe_clip_state ucp;
+ struct pipe_buffer *vertex_constants;
+ struct pipe_buffer *fragment_constants;
} curr;
struct {
};
-#define BRW_PACKCOLOR8888(r,g,b,a) ((r<<24) | (g<<16) | (b<<8) | a)
-
-
-
-/*======================================================================
- * brw_vtbl.c
- */
-void brwInitVtbl( struct brw_context *brw );
-
/*======================================================================
* brw_queryobj.c
}
+#define BRW_IS_965(brw) ((brw)->chipset.is_965)
+#define BRW_IS_IGDNG(brw) ((brw)->chipset.is_igdng)
+#define BRW_IS_G4X(brw) ((brw)->chipset.is_g4x)
-#define DO_SETUP_BITS ((1<<(FRAG_ATTRIB_MAX)) - 1)
-
#endif
* Keith Whitwell <keith@tungstengraphics.com>
*/
+#include "util/u_memory.h"
+#include "util/u_math.h"
#include "brw_batchbuffer.h"
-#include "intel_regions.h"
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_state.h"
#include "brw_util.h"
+#include "brw_debug.h"
+#include "brw_screen.h"
/**
/* PIPE_NEW_CLIP */
if (brw->curr.ucp.nr) {
- GLuint nr_planes = 6 + brw->nr_ucp;
+ GLuint nr_planes = 6 + brw->curr.ucp.nr;
nr_clip_regs = (nr_planes * 4 + 15) / 16;
}
*/
static void prepare_constant_buffer(struct brw_context *brw)
{
- const struct brw_vertex_program *vp =
- brw_vertex_program_const(brw->vertex_program);
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
const GLuint sz = brw->curbe.total_size;
const GLuint bufsz = sz * 16 * sizeof(GLfloat);
GLfloat *buf;
return;
}
- buf = (GLfloat *) _mesa_calloc(bufsz);
+ buf = (GLfloat *) CALLOC(bufsz, 1);
/* fragment shader constants */
if (brw->curbe.wm_size) {
/* Clip planes:
*/
- assert(brw->nr_ucp <= 6);
- for (j = 0; j < brw->nr_ucp; j++) {
- buf[offset + i * 4 + 0] = brw->ucp[j][0];
- buf[offset + i * 4 + 1] = brw->ucp[j][1];
- buf[offset + i * 4 + 2] = brw->ucp[j][2];
- buf[offset + i * 4 + 3] = brw->ucp[j][3];
+ assert(brw->curr.ucp.nr <= 6);
+ for (j = 0; j < brw->curr.ucp.nr; j++) {
+ buf[offset + i * 4 + 0] = brw->curr.ucp.ucp[j][0];
+ buf[offset + i * 4 + 1] = brw->curr.ucp.ucp[j][1];
+ buf[offset + i * 4 + 2] = brw->curr.ucp.ucp[j][2];
+ buf[offset + i * 4 + 3] = brw->curr.ucp.ucp[j][3];
i++;
}
}
/* vertex shader constants */
if (brw->curbe.vs_size) {
GLuint offset = brw->curbe.vs_start * 16;
- GLuint nr = brw->vs.prog_data->nr_params / 4;
+ GLuint nr = brw->curr.vertex_shader->info.file_max[TGSI_FILE_CONSTANT];
+ struct pipe_screen *screen = &brw->brw_screen->base;
- /* map vs constant buffer */
+ const GLfloat *value = screen->buffer_map( screen,
+ brw->curr.vertex_constants,
+ PIPE_BUFFER_USAGE_CPU_READ);
- /* XXX just use a memcpy here */
- for (i = 0; i < nr; i++) {
- const GLfloat *value = vp->program.Base.Parameters->ParameterValues[i];
- buf[offset + i * 4 + 0] = value[0];
- buf[offset + i * 4 + 1] = value[1];
- buf[offset + i * 4 + 2] = value[2];
- buf[offset + i * 4 + 3] = value[3];
- }
+ /* XXX: what if user's constant buffer is too small?
+ */
+ memcpy(&buf[offset], value, nr * 4 * sizeof(float));
- /* unmap vs constant buffer */
+ screen->buffer_unmap( screen, brw->curr.vertex_constants );
}
- if (0) {
+ if (BRW_DEBUG & DEBUG_CURBE) {
for (i = 0; i < sz*16; i+=4)
debug_printf("curbe %d.%d: %f %f %f %f\n", i/8, i&4,
buf[i+0], buf[i+1], buf[i+2], buf[i+3]);
/* Allocate a single page for CURBE entries for this batchbuffer.
* They're generally around 64b.
*/
- brw->curbe.curbe_bo = dri_bo_alloc(brw->intel.bufmgr, "CURBE",
- 4096, 1 << 6);
+ brw->curbe.curbe_bo = brw->sws->bo_alloc(brw->sws,
+ BRW_BUFFER_TYPE_CURBE,
+ 4096, 1 << 6);
brw->curbe.curbe_next_offset = 0;
}
brw->curbe.curbe_offset = brw->curbe.curbe_next_offset;
brw->curbe.curbe_next_offset += bufsz;
- brw->curbe.curbe_next_offset = ALIGN(brw->curbe.curbe_next_offset, 64);
+ brw->curbe.curbe_next_offset = align(brw->curbe.curbe_next_offset, 64);
/* Copy data to the buffer:
*/
- dri_bo_subdata(brw->curbe.curbe_bo, brw->curbe.curbe_offset, bufsz, buf);
+ brw->sws->bo_subdata(brw->curbe.curbe_bo,
+ brw->curbe.curbe_offset,
+ bufsz,
+ buf);
}
brw_add_validated_bo(brw, brw->curbe.curbe_bo);
const struct brw_tracked_state brw_constant_buffer = {
.dirty = {
- .mesa = (PIPE_NEW_FS_CONSTANTS |
- PIPE_NEW_VS_CONSTANTS |
+ .mesa = (PIPE_NEW_FRAGMENT_CONSTANTS |
+ PIPE_NEW_VERTEX_CONSTANTS |
PIPE_NEW_CLIP),
.brw = (BRW_NEW_FRAGMENT_PROGRAM |
BRW_NEW_VERTEX_PROGRAM |
--- /dev/null
+#ifndef BRW_DEBUG_H
+#define BRW_DEBUG_H
+
+/* ================================================================
+ * Debugging:
+ */
+
+#define DEBUG_TEXTURE 0x1
+#define DEBUG_STATE 0x2
+#define DEBUG_IOCTL 0x4
+#define DEBUG_BLIT 0x8
+#define DEBUG_CURBE 0x10
+#define DEBUG_FALLBACKS 0x20
+#define DEBUG_VERBOSE 0x40
+#define DEBUG_BATCH 0x80
+#define DEBUG_PIXEL 0x100
+#define DEBUG_BUFMGR 0x200
+#define DEBUG_unused1 0x400
+#define DEBUG_unused2 0x800
+#define DEBUG_unused3 0x1000
+#define DEBUG_SYNC 0x2000
+#define DEBUG_PRIMS 0x4000
+#define DEBUG_VERTS 0x8000
+#define DEBUG_unused4 0x10000
+#define DEBUG_DMA 0x20000
+#define DEBUG_SANITY 0x40000
+#define DEBUG_SLEEP 0x80000
+#define DEBUG_STATS 0x100000
+#define DEBUG_unused5 0x200000
+#define DEBUG_SINGLE_THREAD 0x400000
+#define DEBUG_WM 0x800000
+#define DEBUG_URB 0x1000000
+#define DEBUG_VS 0x2000000
+
+#ifdef DEBUG
+extern int BRW_DEBUG;
+#else
+#define BRW_DEBUG 0
+#endif
+
+
+#endif
#define R02_PRIM_END 0x1
#define R02_PRIM_START 0x2
-#include "intel_chipset.h"
-
-#define BRW_IS_G4X(brw) (IS_G4X((brw)->brw_screen->pci_id))
-#define BRW_IS_IGDNG(brw) (IS_IGDNG((brw)->brw_screen->pci_id))
-#define BRW_IS_965(brw) (!(BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)))
-#define CMD_PIPELINE_SELECT(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_PIPELINE_SELECT_GM45 : CMD_PIPELINE_SELECT_965)
-#define CMD_VF_STATISTICS(brw) ((BRW_IS_G4X(brw) || BRW_IS_IGDNG(brw)) ? CMD_VF_STATISTICS_GM45 : CMD_VF_STATISTICS_965)
#define URB_SIZES(brw) (BRW_IS_IGDNG(brw) ? 1024 : \
(BRW_IS_G4X(brw) ? 384 : 256)) /* 512 bit units */
#include "brw_defines.h"
#include "brw_context.h"
#include "brw_state.h"
+#include "brw_debug.h"
#include "brw_batchbuffer.h"
-#include "intel_buffer_objects.h"
#define FILE_DEBUG_FLAG DEBUG_BATCH
* programs be immune to the active primitive (ie. cope with all
* possibilities). That may not be realistic however.
*/
-static GLuint brw_set_prim(struct brw_context *brw, GLenum prim)
+static GLuint brw_set_prim(struct brw_context *brw, unsigned prim)
{
- if (INTEL_DEBUG & DEBUG_PRIMS)
- _mesa_printf("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim));
+ if (BRW_DEBUG & DEBUG_PRIMS)
+ debug_printf("PRIM: %s\n", u_prim_name(prim));
- /* Slight optimization to avoid the GS program when not needed:
- */
- if (prim == GL_QUAD_STRIP &&
- ctx->Light.ShadeModel != GL_FLAT &&
- ctx->Polygon.FrontMode == GL_FILL &&
- ctx->Polygon.BackMode == GL_FILL)
- prim = GL_TRIANGLE_STRIP;
-
if (prim != brw->primitive) {
brw->primitive = prim;
brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;
- if (reduced_prim[prim] != brw->intel.reduced_primitive) {
- brw->intel.reduced_primitive = reduced_prim[prim];
+ if (reduced_prim[prim] != brw->reduced_primitive) {
+ brw->reduced_primitive = reduced_prim[prim];
brw->state.dirty.brw |= BRW_NEW_REDUCED_PRIMITIVE;
}
}
}
-static GLuint trim(GLenum prim, GLuint length)
-{
- if (prim == GL_QUAD_STRIP)
- return length > 3 ? (length - length % 2) : 0;
- else if (prim == GL_QUADS)
- return length - length % 4;
- else
- return length;
-}
-
-static void brw_emit_prim(struct brw_context *brw,
- const struct _mesa_prim *prim,
- uint32_t hw_prim)
+static enum pipe_error brw_emit_prim(struct brw_context *brw,
+ unsigned prim,
+ unsigned start,
+ unsigned count,
+ boolean indexed,
+ uint32_t hw_prim)
{
struct brw_3d_primitive prim_packet;
if (INTEL_DEBUG & DEBUG_PRIMS)
- _mesa_printf("PRIM: %s %d %d\n", _mesa_lookup_enum_by_nr(prim->mode),
- prim->start, prim->count);
+ debug_printf("PRIM: %s %d %d\n", u_prim_name(prim), start, count);
prim_packet.header.opcode = CMD_3D_PRIM;
prim_packet.header.length = sizeof(prim_packet)/4 - 2;
prim_packet.header.pad = 0;
prim_packet.header.topology = hw_prim;
- prim_packet.header.indexed = prim->indexed;
+ prim_packet.header.indexed = indexed;
- prim_packet.verts_per_instance = trim(prim->mode, prim->count);
- prim_packet.start_vert_location = prim->start;
- if (prim->indexed)
+ prim_packet.verts_per_instance = count;
+ prim_packet.start_vert_location = start;
+ if (indexed)
prim_packet.start_vert_location += brw->ib.start_vertex_offset;
prim_packet.instance_count = 1;
prim_packet.start_instance_location = 0;
prim_packet.base_vert_location = prim->basevertex;
- /* Can't wrap here, since we rely on the validated state. */
- brw->no_batch_wrap = GL_TRUE;
/* If we're set to always flush, do it before and after the primitive emit.
* We want to catch both missed flushes that hurt instruction/state cache
* the besides the draw code.
*/
if (intel->always_flush_cache) {
- BEGIN_BATCH(1, IGNORE_CLIPRECTS);
+ BEGIN_BATCH(1, IGNORE_CLIPRECTS)
OUT_BATCH(intel->vtbl.flush_cmd());
ADVANCE_BATCH();
}
if (prim_packet.verts_per_instance) {
- brw_batchbuffer_data( brw->intel.batch, &prim_packet,
- sizeof(prim_packet), LOOP_CLIPRECTS);
+ ret = brw_batchbuffer_data( brw->intel.batch, &prim_packet,
+ sizeof(prim_packet), LOOP_CLIPRECTS);
+ if (ret)
+ return ret;
}
if (intel->always_flush_cache) {
BEGIN_BATCH(1, IGNORE_CLIPRECTS);
ADVANCE_BATCH();
}
- brw->no_batch_wrap = GL_FALSE;
+ return 0;
}
-static void brw_merge_inputs( struct brw_context *brw,
- const struct gl_client_array *arrays[])
-{
- struct brw_vertex_info old = brw->vb.info;
- GLuint i;
-
- for (i = 0; i < VERT_ATTRIB_MAX; i++)
- brw->sws->bo_unreference(brw->vb.inputs[i].bo);
-
- memset(&brw->vb.inputs, 0, sizeof(brw->vb.inputs));
- memset(&brw->vb.info, 0, sizeof(brw->vb.info));
-
- for (i = 0; i < VERT_ATTRIB_MAX; i++) {
- brw->vb.inputs[i].glarray = arrays[i];
- brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
-
- if (arrays[i]->StrideB != 0)
- brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
- ((i%16) * 2);
- }
-
- /* Raise statechanges if input sizes have changed. */
- if (memcmp(brw->vb.info.sizes, old.sizes, sizeof(old.sizes)) != 0)
- brw->state.dirty.brw |= BRW_NEW_INPUT_DIMENSIONS;
-}
/* May fail if out of video memory for texture or vbo upload, or on
* fallback conditions.
return 0;
}
-void brw_draw_prims( struct brw_context *brw,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prim,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index )
+
+static boolean
+brw_draw_range_elements(struct pipe_context *pipe,
+ struct pipe_buffer *index_buffer,
+ unsigned index_size,
+ unsigned min_index,
+ unsigned max_index,
+ unsigned mode, unsigned start, unsigned count)
{
enum pipe_error ret;
ret = brw_try_draw_prims(ctx, arrays, prim, nr_prims, ib, min_index, max_index);
assert(ret == 0);
}
+
+ return TRUE;
}
-void brw_draw_init( struct brw_context *brw )
+static boolean
+brw_draw_elements(struct pipe_context *pipe,
+ struct pipe_buffer *index_buffer,
+ unsigned index_size,
+ unsigned mode,
+ unsigned start, unsigned count)
{
- struct vbo_context *vbo = vbo_context(ctx);
+ return brw_draw_range_elements( pipe, index_buffer,
+ index_size,
+ 0, 0xffffffff,
+ mode,
+ start, count );
+}
+static boolean
+brw_draw_arrays(struct pipe_context *pipe, unsigned mode,
+ unsigned start, unsigned count)
+{
+ return brw_draw_elements(pipe, NULL, 0, mode, start, count);
+}
+
+
+
+void brw_draw_init( struct brw_context *brw )
+{
/* Register our drawing function:
*/
- vbo->draw_prims = brw_draw_prims;
+ brw->base.draw_arrays = brw_draw_arrays;
+ brw->base.draw_elements = brw_draw_elements;
+ brw->base.draw_range_elements = brw_draw_range_elements;
}
void brw_draw_destroy( struct brw_context *brw )
struct brw_context;
-void brw_draw_prims( struct brw_context *brw,
- const struct gl_client_array *arrays[],
- const struct _mesa_prim *prims,
- GLuint nr_prims,
- const struct _mesa_index_buffer *ib,
- GLboolean index_bounds_valid,
- GLuint min_index,
- GLuint max_index );
-
void brw_draw_init( struct brw_context *brw );
-void brw_draw_destroy( struct brw_context *brw );
+void brw_draw_cleanup( struct brw_context *brw );
-/* brw_draw_current.c
- */
-void brw_init_current_values(struct brw_context *brw,
- struct gl_client_array *arrays);
#endif
#include "brw_fallback.h"
#include "brw_batchbuffer.h"
-#include "intel_buffer_objects.h"
-#include "intel_tex.h"
#ifndef BRW_EU_H
#define BRW_EU_H
+#include "util/u_debug.h"
+
#include "brw_structs.h"
#include "brw_defines.h"
#include "brw_batchbuffer.h"
-#include "intel_regions.h"
-
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
+++ /dev/null
- if (INTEL_DEBUG & DEBUG_STATS)
- cc.cc5.statistics_enable = 1;
#include "brw_context.h"
#include "brw_state.h"
#include "brw_batchbuffer.h"
-#include "intel_reg.h"
+#include "brw_reg.h"
/** Waits on the query object's BO and totals the results for this query */
static void
brw->sws->bo_unreference(brw->query.bo);
brw->query.bo = NULL;
- brw->query.bo = dri_bo_alloc(brw->bufmgr, "query", 4096, 1);
+ brw->query.bo = brw->sws->bo_alloc(brw->sws, BRW_BUFFER_TYPE_QUERY, 4096, 1);
brw->query.index = 0;
}
--- /dev/null
+
+static void brw_merge_inputs( struct brw_context *brw,
+ const struct gl_client_array *arrays[])
+{
+ struct brw_vertex_info old = brw->vb.info;
+ GLuint i;
+
+ for (i = 0; i < VERT_ATTRIB_MAX; i++)
+ brw->sws->bo_unreference(brw->vb.inputs[i].bo);
+
+ memset(&brw->vb.inputs, 0, sizeof(brw->vb.inputs));
+ memset(&brw->vb.info, 0, sizeof(brw->vb.info));
+
+ for (i = 0; i < VERT_ATTRIB_MAX; i++) {
+ brw->vb.inputs[i].glarray = arrays[i];
+ brw->vb.inputs[i].attrib = (gl_vert_attrib) i;
+
+ if (arrays[i]->StrideB != 0)
+ brw->vb.info.sizes[i/16] |= (brw->vb.inputs[i].glarray->Size - 1) <<
+ ((i%16) * 2);
+ }
+
+ /* Raise statechanges if input sizes have changed. */
+ if (memcmp(brw->vb.info.sizes, old.sizes, sizeof(old.sizes)) != 0)
+ brw->state.dirty.brw |= BRW_NEW_INPUT_DIMENSIONS;
+}
#define FENCE_YMAJOR 2
+
+/* PCI IDs
+ */
+#define PCI_CHIP_I965_G 0x29A2
+#define PCI_CHIP_I965_Q 0x2992
+#define PCI_CHIP_I965_G_1 0x2982
+#define PCI_CHIP_I946_GZ 0x2972
+#define PCI_CHIP_I965_GM 0x2A02
+#define PCI_CHIP_I965_GME 0x2A12
+
+#define PCI_CHIP_GM45_GM 0x2A42
+
+#define PCI_CHIP_IGD_E_G 0x2E02
+#define PCI_CHIP_Q45_G 0x2E12
+#define PCI_CHIP_G45_G 0x2E22
+#define PCI_CHIP_G41_G 0x2E32
+#define PCI_CHIP_B43_G 0x2E42
+
+#define PCI_CHIP_ILD_G 0x0042
+#define PCI_CHIP_ILM_G 0x0046
+
+struct brw_chipset {
+ int pci_id:16;
+ int is_965:1;
+ int is_igdng:1;
+ int is_g4x:1;
+ int pad:13;
+};
+
+
+/* XXX: hacks
+ */
+#define VERT_RESULT_HPOS 0 /* not always true */
+#define VERT_RESULT_PSIZ 10000 /* disabled */
+
+
#endif
--- /dev/null
+/**************************************************************************
+ *
+ * Copyright 2008 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+
+#include "pipe/p_inlines.h"
+#include "util/u_memory.h"
+#include "util/u_string.h"
+
+#include "brw_reg.h"
+#include "brw_context.h"
+#include "brw_screen.h"
+#include "brw_buffer.h"
+#include "brw_texture.h"
+#include "brw_winsys.h"
+
+#ifdef DEBUG
+static const struct debug_named_value debug_names[] = {
+ { "tex", DEBUG_TEXTURE},
+ { "state", DEBUG_STATE},
+ { "ioctl", DEBUG_IOCTL},
+ { "blit", DEBUG_BLIT},
+ { "curbe", DEBUG_CURBE},
+ { "fall", DEBUG_FALLBACKS},
+ { "verb", DEBUG_VERBOSE},
+ { "bat", DEBUG_BATCH},
+ { "pix", DEBUG_PIXEL},
+ { "buf", DEBUG_BUFMGR},
+ { "reg", DEBUG_REGION},
+ { "fbo", DEBUG_FBO},
+ { "lock", DEBUG_LOCK},
+ { "sync", DEBUG_SYNC},
+ { "prim", DEBUG_PRIMS },
+ { "vert", DEBUG_VERTS },
+ { "dri", DEBUG_DRI },
+ { "dma", DEBUG_DMA },
+ { "san", DEBUG_SANITY },
+ { "sleep", DEBUG_SLEEP },
+ { "stats", DEBUG_STATS },
+ { "tile", DEBUG_TILE },
+ { "sing", DEBUG_SINGLE_THREAD },
+ { "thre", DEBUG_SINGLE_THREAD },
+ { "wm", DEBUG_WM },
+ { "urb", DEBUG_URB },
+ { "vs", DEBUG_VS },
+ { NULL, 0 }
+};
+
+int BRW_DEBUG = 0;
+#endif
+
+
+/*
+ * Probe functions
+ */
+
+
+static const char *
+brw_get_vendor(struct pipe_screen *screen)
+{
+ return "VMware, Inc.";
+}
+
+static const char *
+brw_get_name(struct pipe_screen *screen)
+{
+ static char buffer[128];
+ const char *chipset;
+
+ switch (brw_screen(screen)->pci_id) {
+ case PCI_CHIP_I965_G:
+ chipset = "I965_G";
+ break;
+ case PCI_CHIP_I965_Q:
+ chipset = "I965_Q";
+ break;
+ case PCI_CHIP_I965_G_1:
+ chipset = "I965_G_1";
+ break;
+ case PCI_CHIP_I946_GZ:
+ chipset = "I946_GZ";
+ break;
+ case PCI_CHIP_I965_GM:
+ chipset = "I965_GM";
+ break;
+ case PCI_CHIP_I965_GME:
+ chipset = "I965_GME";
+ break;
+ case PCI_CHIP_GM45_GM:
+ chipset = "GM45_GM";
+ break;
+ case PCI_CHIP_IGD_E_G:
+ chipset = "IGD_E_G";
+ break;
+ case PCI_CHIP_Q45_G:
+ chipset = "Q45_G";
+ break;
+ case PCI_CHIP_G45_G:
+ chipset = "G45_G";
+ break;
+ case PCI_CHIP_G41_G:
+ chipset = "G41_G";
+ break;
+ case PCI_CHIP_B43_G:
+ chipset = "B43_G";
+ break;
+ case PCI_CHIP_ILD_G:
+ chipset = "ILD_G";
+ break;
+ case PCI_CHIP_ILM_G:
+ chipset = "ILM_G";
+ break;
+ }
+
+ util_snprintf(buffer, sizeof(buffer), "i965 (chipset: %s)", chipset);
+ return buffer;
+}
+
+static int
+brw_get_param(struct pipe_screen *screen, int param)
+{
+ switch (param) {
+ case PIPE_CAP_MAX_TEXTURE_IMAGE_UNITS:
+ return 8;
+ case PIPE_CAP_NPOT_TEXTURES:
+ return 1;
+ case PIPE_CAP_TWO_SIDED_STENCIL:
+ return 1;
+ case PIPE_CAP_GLSL:
+ return 0;
+ case PIPE_CAP_ANISOTROPIC_FILTER:
+ return 0;
+ case PIPE_CAP_POINT_SPRITE:
+ return 0;
+ case PIPE_CAP_MAX_RENDER_TARGETS:
+ return 1;
+ case PIPE_CAP_OCCLUSION_QUERY:
+ return 0;
+ case PIPE_CAP_TEXTURE_SHADOW_MAP:
+ return 1;
+ case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
+ return 11; /* max 1024x1024 */
+ case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
+ return 8; /* max 128x128x128 */
+ case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
+ return 11; /* max 1024x1024 */
+ default:
+ return 0;
+ }
+}
+
+static float
+brw_get_paramf(struct pipe_screen *screen, int param)
+{
+ switch (param) {
+ case PIPE_CAP_MAX_LINE_WIDTH:
+ /* fall-through */
+ case PIPE_CAP_MAX_LINE_WIDTH_AA:
+ return 7.5;
+
+ case PIPE_CAP_MAX_POINT_WIDTH:
+ /* fall-through */
+ case PIPE_CAP_MAX_POINT_WIDTH_AA:
+ return 255.0;
+
+ case PIPE_CAP_MAX_TEXTURE_ANISOTROPY:
+ return 4.0;
+
+ case PIPE_CAP_MAX_TEXTURE_LOD_BIAS:
+ return 16.0;
+
+ default:
+ return 0;
+ }
+}
+
+static boolean
+brw_is_format_supported(struct pipe_screen *screen,
+ enum pipe_format format,
+ enum pipe_texture_target target,
+ unsigned tex_usage,
+ unsigned geom_flags)
+{
+ static const enum pipe_format tex_supported[] = {
+ PIPE_FORMAT_R8G8B8A8_UNORM,
+ PIPE_FORMAT_A8R8G8B8_UNORM,
+ PIPE_FORMAT_R5G6B5_UNORM,
+ PIPE_FORMAT_L8_UNORM,
+ PIPE_FORMAT_A8_UNORM,
+ PIPE_FORMAT_I8_UNORM,
+ PIPE_FORMAT_A8L8_UNORM,
+ PIPE_FORMAT_YCBCR,
+ PIPE_FORMAT_YCBCR_REV,
+ PIPE_FORMAT_S8Z24_UNORM,
+ PIPE_FORMAT_NONE /* list terminator */
+ };
+ static const enum pipe_format surface_supported[] = {
+ PIPE_FORMAT_A8R8G8B8_UNORM,
+ PIPE_FORMAT_R5G6B5_UNORM,
+ PIPE_FORMAT_S8Z24_UNORM,
+ PIPE_FORMAT_NONE /* list terminator */
+ };
+ const enum pipe_format *list;
+ uint i;
+
+ if(tex_usage & PIPE_TEXTURE_USAGE_RENDER_TARGET)
+ list = surface_supported;
+ else
+ list = tex_supported;
+
+ for (i = 0; list[i] != PIPE_FORMAT_NONE; i++) {
+ if (list[i] == format)
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+
+/*
+ * Fence functions
+ */
+
+
+static void
+brw_fence_reference(struct pipe_screen *screen,
+ struct pipe_fence_handle **ptr,
+ struct pipe_fence_handle *fence)
+{
+ struct brw_screen *is = brw_screen(screen);
+
+ is->iws->fence_reference(is->iws, ptr, fence);
+}
+
+static int
+brw_fence_signalled(struct pipe_screen *screen,
+ struct pipe_fence_handle *fence,
+ unsigned flags)
+{
+ struct brw_screen *is = brw_screen(screen);
+
+ return is->iws->fence_signalled(is->iws, fence);
+}
+
+static int
+brw_fence_finish(struct pipe_screen *screen,
+ struct pipe_fence_handle *fence,
+ unsigned flags)
+{
+ struct brw_screen *is = brw_screen(screen);
+
+ return is->iws->fence_finish(is->iws, fence);
+}
+
+
+/*
+ * Generic functions
+ */
+
+
+static void
+brw_destroy_screen(struct pipe_screen *screen)
+{
+ struct brw_screen *is = brw_screen(screen);
+
+ if (is->iws)
+ is->iws->destroy(is->iws);
+
+ FREE(is);
+}
+
+/**
+ * Create a new brw_screen object
+ */
+struct pipe_screen *
+brw_create_screen(struct intel_winsys *iws, uint pci_id)
+{
+ struct brw_screen *is;
+ struct brw_chipset chipset;
+
+#ifdef DEBUG
+ BRW_DEBUG = debug_get_flags_option("BRW_DEBUG", debug_names, 0);
+ BRW_DEBUG |= debug_get_flags_option("INTEL_DEBUG", debug_names, 0);
+#endif
+
+ memset(&chipset, 0, sizeof chipset);
+
+ chipset.pci_id = pci_id;
+
+ switch (pci_id) {
+ case PCI_CHIP_I965_G:
+ case PCI_CHIP_I965_Q:
+ case PCI_CHIP_I965_G_1:
+ case PCI_CHIP_I946_GZ:
+ case PCI_CHIP_I965_GM:
+ case PCI_CHIP_I965_GME:
+ chipset.is_965 = TRUE;
+ break;
+
+ case PCI_CHIP_GM45_GM:
+ case PCI_CHIP_IGD_E_G:
+ case PCI_CHIP_Q45_G:
+ case PCI_CHIP_G45_G:
+ case PCI_CHIP_G41_G:
+ case PCI_CHIP_B43_G:
+ chipset.is_g4x = TRUE;
+ break;
+
+ case PCI_CHIP_ILD_G:
+ case PCI_CHIP_ILM_G:
+ chipset.is_igdng = TRUE;
+ break;
+
+ default:
+ debug_printf("%s: unknown pci id 0x%x, cannot create screen\n",
+ __FUNCTION__, pci_id);
+ return NULL;
+ }
+
+
+ is = CALLOC_STRUCT(brw_screen);
+ if (!is)
+ return NULL;
+
+ is->chipset = chipset;
+ is->iws = iws;
+ is->base.winsys = NULL;
+ is->base.destroy = brw_destroy_screen;
+ is->base.get_name = brw_get_name;
+ is->base.get_vendor = brw_get_vendor;
+ is->base.get_param = brw_get_param;
+ is->base.get_paramf = brw_get_paramf;
+ is->base.is_format_supported = brw_is_format_supported;
+ is->base.fence_reference = brw_fence_reference;
+ is->base.fence_signalled = brw_fence_signalled;
+ is->base.fence_finish = brw_fence_finish;
+
+ brw_screen_init_texture_functions(is);
+ brw_screen_init_buffer_functions(is);
+
+ return &is->base;
+}
#include "pipe/p_state.h"
#include "pipe/p_screen.h"
+#include "brw_reg.h"
struct brw_winsys_screen;
struct brw_screen
{
struct pipe_screen base;
-
+ struct brw_chipset chipset;
struct brw_winsys_screen *sws;
-
- boolean is_i945;
- uint pci_id;
};
/**
c.key = *key;
c.nr_attrs = util_count_bits(c.key.attrs);
c.nr_attr_regs = (c.nr_attrs+1)/2;
- c.nr_setup_attrs = util_count_bits(c.key.attrs & DO_SETUP_BITS);
+ c.nr_setup_attrs = c.key.nr_attrs;
c.nr_setup_regs = (c.nr_setup_attrs+1)/2;
c.prog_data.urb_read_length = c.nr_attr_regs;
*/
/* The scissor only needs to handle the intersection of drawable and
- * scissor rect. Clipping to the boundaries of static shared buffers
- * for front/back/depth is covered by looping over cliprects in brw_draw.c.
+ * scissor rect.
*
* Note that the hardware's coordinates are inclusive, while Mesa's min is
* inclusive but max is exclusive.
int i;
/* Create the buffer object to contain the data */
- bo = dri_bo_alloc(cache->brw->intel.bufmgr,
- cache->name[cache_id], data_size, 1 << 6);
+ bo = brw->sws->bo_alloc(cache->sws,
+ cache->buffer_type[cache_id], data_size, 1 << 6);
/* Set up the memory containing the key, aux_data, and reloc_bufs */
--- /dev/null
+/*
+ Copyright (C) Intel Corp. 2006. All Rights Reserved.
+ Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ develop this 3D driver.
+
+ Permission is hereby granted, free of charge, to any person obtaining
+ a copy of this software and associated documentation files (the
+ "Software"), to deal in the Software without restriction, including
+ without limitation the rights to use, copy, modify, merge, publish,
+ distribute, sublicense, and/or sell copies of the Software, and to
+ permit persons to whom the Software is furnished to do so, subject to
+ the following conditions:
+
+ The above copyright notice and this permission notice (including the
+ next paragraph) shall be included in all copies or substantial
+ portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
+ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+ **********************************************************************/
+
+
+
+#include "brw_context.h"
+#include "brw_state.h"
+
+
+struct dirty_bit_map {
+ uint32_t bit;
+ char *name;
+ uint32_t count;
+};
+
+#define DEFINE_BIT(name) {name, #name, 0}
+
+static struct dirty_bit_map mesa_bits[] = {
+ DEFINE_BIT(_NEW_MODELVIEW),
+ DEFINE_BIT(_NEW_PROJECTION),
+ DEFINE_BIT(_NEW_TEXTURE_MATRIX),
+ DEFINE_BIT(_NEW_COLOR_MATRIX),
+ DEFINE_BIT(_NEW_ACCUM),
+ DEFINE_BIT(_NEW_COLOR),
+ DEFINE_BIT(_NEW_DEPTH),
+ DEFINE_BIT(_NEW_EVAL),
+ DEFINE_BIT(_NEW_FOG),
+ DEFINE_BIT(_NEW_HINT),
+ DEFINE_BIT(_NEW_LIGHT),
+ DEFINE_BIT(_NEW_LINE),
+ DEFINE_BIT(_NEW_PIXEL),
+ DEFINE_BIT(_NEW_POINT),
+ DEFINE_BIT(_NEW_POLYGON),
+ DEFINE_BIT(_NEW_POLYGONSTIPPLE),
+ DEFINE_BIT(_NEW_SCISSOR),
+ DEFINE_BIT(_NEW_STENCIL),
+ DEFINE_BIT(_NEW_TEXTURE),
+ DEFINE_BIT(_NEW_TRANSFORM),
+ DEFINE_BIT(_NEW_VIEWPORT),
+ DEFINE_BIT(_NEW_PACKUNPACK),
+ DEFINE_BIT(_NEW_ARRAY),
+ DEFINE_BIT(_NEW_RENDERMODE),
+ DEFINE_BIT(_NEW_BUFFERS),
+ DEFINE_BIT(_NEW_MULTISAMPLE),
+ DEFINE_BIT(_NEW_TRACK_MATRIX),
+ DEFINE_BIT(_NEW_PROGRAM),
+ DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
+ {0, 0, 0}
+};
+
+static struct dirty_bit_map brw_bits[] = {
+ DEFINE_BIT(BRW_NEW_URB_FENCE),
+ DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
+ DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
+ DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
+ DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
+ DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
+ DEFINE_BIT(BRW_NEW_PRIMITIVE),
+ DEFINE_BIT(BRW_NEW_CONTEXT),
+ DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
+ DEFINE_BIT(BRW_NEW_PSP),
+ DEFINE_BIT(BRW_NEW_FENCE),
+ DEFINE_BIT(BRW_NEW_INDICES),
+ DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
+ DEFINE_BIT(BRW_NEW_VERTICES),
+ DEFINE_BIT(BRW_NEW_BATCH),
+ DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
+ {0, 0, 0}
+};
+
+static struct dirty_bit_map cache_bits[] = {
+ DEFINE_BIT(CACHE_NEW_CC_VP),
+ DEFINE_BIT(CACHE_NEW_CC_UNIT),
+ DEFINE_BIT(CACHE_NEW_WM_PROG),
+ DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR),
+ DEFINE_BIT(CACHE_NEW_SAMPLER),
+ DEFINE_BIT(CACHE_NEW_WM_UNIT),
+ DEFINE_BIT(CACHE_NEW_SF_PROG),
+ DEFINE_BIT(CACHE_NEW_SF_VP),
+ DEFINE_BIT(CACHE_NEW_SF_UNIT),
+ DEFINE_BIT(CACHE_NEW_VS_UNIT),
+ DEFINE_BIT(CACHE_NEW_VS_PROG),
+ DEFINE_BIT(CACHE_NEW_GS_UNIT),
+ DEFINE_BIT(CACHE_NEW_GS_PROG),
+ DEFINE_BIT(CACHE_NEW_CLIP_VP),
+ DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
+ DEFINE_BIT(CACHE_NEW_CLIP_PROG),
+ DEFINE_BIT(CACHE_NEW_SURFACE),
+ DEFINE_BIT(CACHE_NEW_SURF_BIND),
+ {0, 0, 0}
+};
+
+
+static void
+brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ if (bit_map[i].bit == 0)
+ return;
+
+ if (bit_map[i].bit & bits)
+ bit_map[i].count++;
+ }
+}
+
+static void
+brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
+{
+ int i;
+
+ for (i = 0; i < 32; i++) {
+ if (bit_map[i].bit == 0)
+ return;
+
+ fprintf(stderr, "0x%08x: %12d (%s)\n",
+ bit_map[i].bit, bit_map[i].count, bit_map[i].name);
+ }
+}
+
{
&brw_check_fallback,
- &brw_wm_input_sizes,
+// &brw_wm_input_sizes,
&brw_vs_prog,
&brw_gs_prog,
&brw_clip_prog,
brw->state.validated_bo_count = 0;
}
-struct dirty_bit_map {
- uint32_t bit;
- char *name;
- uint32_t count;
-};
-
-#define DEFINE_BIT(name) {name, #name, 0}
-
-static struct dirty_bit_map mesa_bits[] = {
- DEFINE_BIT(_NEW_MODELVIEW),
- DEFINE_BIT(_NEW_PROJECTION),
- DEFINE_BIT(_NEW_TEXTURE_MATRIX),
- DEFINE_BIT(_NEW_COLOR_MATRIX),
- DEFINE_BIT(_NEW_ACCUM),
- DEFINE_BIT(_NEW_COLOR),
- DEFINE_BIT(_NEW_DEPTH),
- DEFINE_BIT(_NEW_EVAL),
- DEFINE_BIT(_NEW_FOG),
- DEFINE_BIT(_NEW_HINT),
- DEFINE_BIT(_NEW_LIGHT),
- DEFINE_BIT(_NEW_LINE),
- DEFINE_BIT(_NEW_PIXEL),
- DEFINE_BIT(_NEW_POINT),
- DEFINE_BIT(_NEW_POLYGON),
- DEFINE_BIT(_NEW_POLYGONSTIPPLE),
- DEFINE_BIT(_NEW_SCISSOR),
- DEFINE_BIT(_NEW_STENCIL),
- DEFINE_BIT(_NEW_TEXTURE),
- DEFINE_BIT(_NEW_TRANSFORM),
- DEFINE_BIT(_NEW_VIEWPORT),
- DEFINE_BIT(_NEW_PACKUNPACK),
- DEFINE_BIT(_NEW_ARRAY),
- DEFINE_BIT(_NEW_RENDERMODE),
- DEFINE_BIT(_NEW_BUFFERS),
- DEFINE_BIT(_NEW_MULTISAMPLE),
- DEFINE_BIT(_NEW_TRACK_MATRIX),
- DEFINE_BIT(_NEW_PROGRAM),
- DEFINE_BIT(_NEW_PROGRAM_CONSTANTS),
- {0, 0, 0}
-};
-
-static struct dirty_bit_map brw_bits[] = {
- DEFINE_BIT(BRW_NEW_URB_FENCE),
- DEFINE_BIT(BRW_NEW_FRAGMENT_PROGRAM),
- DEFINE_BIT(BRW_NEW_VERTEX_PROGRAM),
- DEFINE_BIT(BRW_NEW_INPUT_DIMENSIONS),
- DEFINE_BIT(BRW_NEW_CURBE_OFFSETS),
- DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
- DEFINE_BIT(BRW_NEW_PRIMITIVE),
- DEFINE_BIT(BRW_NEW_CONTEXT),
- DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
- DEFINE_BIT(BRW_NEW_PSP),
- DEFINE_BIT(BRW_NEW_FENCE),
- DEFINE_BIT(BRW_NEW_INDICES),
- DEFINE_BIT(BRW_NEW_INDEX_BUFFER),
- DEFINE_BIT(BRW_NEW_VERTICES),
- DEFINE_BIT(BRW_NEW_BATCH),
- DEFINE_BIT(BRW_NEW_DEPTH_BUFFER),
- {0, 0, 0}
-};
-
-static struct dirty_bit_map cache_bits[] = {
- DEFINE_BIT(CACHE_NEW_CC_VP),
- DEFINE_BIT(CACHE_NEW_CC_UNIT),
- DEFINE_BIT(CACHE_NEW_WM_PROG),
- DEFINE_BIT(CACHE_NEW_SAMPLER_DEFAULT_COLOR),
- DEFINE_BIT(CACHE_NEW_SAMPLER),
- DEFINE_BIT(CACHE_NEW_WM_UNIT),
- DEFINE_BIT(CACHE_NEW_SF_PROG),
- DEFINE_BIT(CACHE_NEW_SF_VP),
- DEFINE_BIT(CACHE_NEW_SF_UNIT),
- DEFINE_BIT(CACHE_NEW_VS_UNIT),
- DEFINE_BIT(CACHE_NEW_VS_PROG),
- DEFINE_BIT(CACHE_NEW_GS_UNIT),
- DEFINE_BIT(CACHE_NEW_GS_PROG),
- DEFINE_BIT(CACHE_NEW_CLIP_VP),
- DEFINE_BIT(CACHE_NEW_CLIP_UNIT),
- DEFINE_BIT(CACHE_NEW_CLIP_PROG),
- DEFINE_BIT(CACHE_NEW_SURFACE),
- DEFINE_BIT(CACHE_NEW_SURF_BIND),
- {0, 0, 0}
-};
-
-
-static void
-brw_update_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
-{
- int i;
-
- for (i = 0; i < 32; i++) {
- if (bit_map[i].bit == 0)
- return;
-
- if (bit_map[i].bit & bits)
- bit_map[i].count++;
- }
-}
-
-static void
-brw_print_dirty_count(struct dirty_bit_map *bit_map, int32_t bits)
-{
- int i;
-
- for (i = 0; i < 32; i++) {
- if (bit_map[i].bit == 0)
- return;
-
- fprintf(stderr, "0x%08x: %12d (%s)\n",
- bit_map[i].bit, bit_map[i].count, bit_map[i].name);
- }
-}
/***********************************************************************
* Emit all state:
*/
-#include "intel_regions.h"
-#include "intel_tex.h"
#include "brw_context.h"
/**
/* Code to layout images in a mipmap tree for i965.
*/
-#include "intel_mipmap_tree.h"
-#include "intel_tex_layout.h"
-#include "intel_chipset.h"
+#include "brw_tex_layout.h"
#define FILE_DEBUG_FLAG DEBUG_MIPTREE
typedef uint8_t GLboolean;
+#define GL_FALSE FALSE
+#define GL_TRUE TRUE
+
#endif
if (!vp->use_const_buffer)
return NULL;
- const_buffer = drm_intel_bo_alloc(intel->bufmgr, "vp_const_buffer",
+ const_buffer = brw->sws->bo_alloc(brw->sws,
+ BRW_BUFFER_TYPE_SHADER_CONSTANTS,
size, 64);
/* _NEW_PROGRAM_CONSTANTS */
struct brw_winsys_screen *sws;
void *bo;
unsigned offset;
+ unsigned size;
};
enum brw_buffer_usage {
BRW_BUFFER_TYPE_TEXTURE,
BRW_BUFFER_TYPE_SCANOUT, /**< a texture used for scanning out from */
BRW_BUFFER_TYPE_VERTEX,
+ BRW_BUFFER_TYPE_CURBE,
+ BRW_BUFFER_TYPE_QUERY,
+ BRW_BUFFER_TYPE_SHADER_CONSTANTS,
+ BRW_BUFFER_TYPE_WM_SCRATCH,
+ BRW_BUFFER_TYPE_BATCH,
};
uint8_t *map;
uint8_t *ptr;
size_t size;
+ struct {
+ uint8_t *end_ptr;
+ } emit;
+
size_t relocs;
size_t max_relocs;
/**
* Buffer functions.
*/
+
/*@{*/
/**
* Create a buffer.
*/
- struct brw_winsys_buffer *(*buffer_create)(struct brw_winsys *iws,
- unsigned size,
- unsigned alignment,
- enum brw_buffer_type type);
-
+ struct brw_winsys_buffer *(*bo_alloc)( struct brw_winsys_screen *sws,
+ enum brw_buffer_type type,
+ unsigned size,
+ unsigned alignment );
/* Reference and unreference buffers:
*/
unsigned offset,
struct brw_winsys_buffer *b2);
+ void (*bo_subdata)(struct brw_winsys_buffer *dst,
+ size_t offset,
+ size_t size,
+ const void *data);
+
/**
* Map a buffer.
*/
void (*buffer_unmap)(struct brw_winsys *iws,
struct brw_winsys_buffer *buffer);
- /**
- * Write to a buffer.
- *
- * Arguments follows pipe_buffer_write.
- */
- int (*buffer_write)(struct brw_winsys *iws,
- struct brw_winsys_buffer *dst,
- size_t offset,
- size_t size,
- const void *data);
-
void (*buffer_destroy)(struct brw_winsys *iws,
struct brw_winsys_buffer *buffer);
/*@}*/
/**
- * Create i915 pipe_screen.
+ * Create brw pipe_screen.
*/
-struct pipe_screen *i915_create_screen(struct brw_winsys *iws, unsigned pci_id);
+struct pipe_screen *brw_create_screen(struct brw_winsys *iws, unsigned pci_id);
/**
- * Create a i915 pipe_context.
+ * Create a brw pipe_context.
*/
-struct pipe_context *i915_create_context(struct pipe_screen *screen);
+struct pipe_context *brw_create_context(struct pipe_screen *screen);
/**
* Get the brw_winsys buffer backing the texture.
* TODO UGLY
*/
struct pipe_texture;
-boolean i915_get_texture_buffer_brw(struct pipe_texture *texture,
+boolean brw_get_texture_buffer_brw(struct pipe_texture *texture,
struct brw_winsys_buffer **buffer,
unsigned *stride);
*
* TODO UGLY
*/
-struct pipe_texture * i915_texture_blanket_brw(struct pipe_screen *screen,
- struct pipe_texture *tmplt,
- unsigned pitch,
- struct brw_winsys_buffer *buffer);
+struct pipe_texture * brw_texture_blanket(struct pipe_screen *screen,
+ struct pipe_texture *tmplt,
+ unsigned pitch,
+ struct brw_winsys_buffer *buffer);
}
/* CACHE_NEW_VS_PROG */
- key->vp_outputs_written = brw->vs.prog_data->outputs_written & DO_SETUP_BITS;
+ key->vp_outputs_written = brw->vs.prog_data->outputs_written; /* bitmask */
/* The unique fragment program ID */
key->program_string_id = fp->id;
brw->wm.scratch_bo = NULL;
}
if (brw->wm.scratch_bo == NULL) {
- brw->wm.scratch_bo = dri_bo_alloc(intel->bufmgr,
- "wm scratch",
- total,
- 4096);
+ brw->wm.scratch_bo = brw->sws->bo_alloc(brw->sws,
+ BRW_BUFFER_TYPE_WM_SCRATCH,
+ total,
+ 4096);
}
}
*/
-#include "intel_mipmap_tree.h"
#include "brw_batchbuffer.h"
-#include "intel_tex.h"
-#include "intel_fbo.h"
-
#include "brw_context.h"
#include "brw_state.h"
#include "brw_defines.h"
if (!fp->use_const_buffer)
return NULL;
- const_buffer = drm_intel_bo_alloc(intel->bufmgr, "fp_const_buffer",
+ const_buffer = drm_intel_bo_alloc(intel->bufmgr,
+ BRW_BUFFER_TYPE_SHADER_CONSTANTS,
size, 64);
/* _NEW_PROGRAM_CONSTANTS */
}
old_nr_surfaces = brw->wm.nr_surfaces;
- brw->wm.nr_surfaces = MAX_DRAW_BUFFERS;
+ brw->wm.nr_surfaces = PIPE_MAX_COLOR_BUFS;
if (brw->wm.surf_bo[SURF_INDEX_FRAG_CONST_BUFFER] != NULL)
brw->wm.nr_surfaces = SURF_INDEX_FRAG_CONST_BUFFER + 1;
+++ /dev/null
-/*
- * Copyright © 2007 Intel Corporation
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- *
- * Authors:
- * Eric Anholt <eric@anholt.net>
- *
- */
-
-#define PCI_CHIP_I810 0x7121
-#define PCI_CHIP_I810_DC100 0x7123
-#define PCI_CHIP_I810_E 0x7125
-#define PCI_CHIP_I815 0x1132
-
-#define PCI_CHIP_I830_M 0x3577
-#define PCI_CHIP_845_G 0x2562
-#define PCI_CHIP_I855_GM 0x3582
-#define PCI_CHIP_I865_G 0x2572
-
-#define PCI_CHIP_I915_G 0x2582
-#define PCI_CHIP_E7221_G 0x258A
-#define PCI_CHIP_I915_GM 0x2592
-#define PCI_CHIP_I945_G 0x2772
-#define PCI_CHIP_I945_GM 0x27A2
-#define PCI_CHIP_I945_GME 0x27AE
-
-#define PCI_CHIP_Q35_G 0x29B2
-#define PCI_CHIP_G33_G 0x29C2
-#define PCI_CHIP_Q33_G 0x29D2
-
-#define PCI_CHIP_IGD_GM 0xA011
-#define PCI_CHIP_IGD_G 0xA001
-
-#define IS_IGDGM(devid) (devid == PCI_CHIP_IGD_GM)
-#define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G)
-#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid))
-
-#define PCI_CHIP_I965_G 0x29A2
-#define PCI_CHIP_I965_Q 0x2992
-#define PCI_CHIP_I965_G_1 0x2982
-#define PCI_CHIP_I946_GZ 0x2972
-#define PCI_CHIP_I965_GM 0x2A02
-#define PCI_CHIP_I965_GME 0x2A12
-
-#define PCI_CHIP_GM45_GM 0x2A42
-
-#define PCI_CHIP_IGD_E_G 0x2E02
-#define PCI_CHIP_Q45_G 0x2E12
-#define PCI_CHIP_G45_G 0x2E22
-#define PCI_CHIP_G41_G 0x2E32
-
-#define PCI_CHIP_ILD_G 0x0042
-#define PCI_CHIP_ILM_G 0x0046
-
-#define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \
- devid == PCI_CHIP_I915_GM || \
- devid == PCI_CHIP_I945_GM || \
- devid == PCI_CHIP_I945_GME || \
- devid == PCI_CHIP_I965_GM || \
- devid == PCI_CHIP_I965_GME || \
- devid == PCI_CHIP_GM45_GM || \
- IS_IGD(devid) || \
- devid == PCI_CHIP_ILM_G)
-
-#define IS_G45(devid) (devid == PCI_CHIP_IGD_E_G || \
- devid == PCI_CHIP_Q45_G || \
- devid == PCI_CHIP_G45_G || \
- devid == PCI_CHIP_G41_G)
-#define IS_GM45(devid) (devid == PCI_CHIP_GM45_GM)
-#define IS_G4X(devid) (IS_G45(devid) || IS_GM45(devid))
-
-#define IS_ILD(devid) (devid == PCI_CHIP_ILD_G)
-#define IS_ILM(devid) (devid == PCI_CHIP_ILM_G)
-#define IS_IGDNG(devid) (IS_ILD(devid) || IS_ILM(devid))
-
-#define IS_915(devid) (devid == PCI_CHIP_I915_G || \
- devid == PCI_CHIP_E7221_G || \
- devid == PCI_CHIP_I915_GM)
-
-#define IS_945(devid) (devid == PCI_CHIP_I945_G || \
- devid == PCI_CHIP_I945_GM || \
- devid == PCI_CHIP_I945_GME || \
- devid == PCI_CHIP_G33_G || \
- devid == PCI_CHIP_Q33_G || \
- devid == PCI_CHIP_Q35_G || IS_IGD(devid))
-
-#define IS_965(devid) (devid == PCI_CHIP_I965_G || \
- devid == PCI_CHIP_I965_Q || \
- devid == PCI_CHIP_I965_G_1 || \
- devid == PCI_CHIP_I965_GM || \
- devid == PCI_CHIP_I965_GME || \
- devid == PCI_CHIP_I946_GZ || \
- IS_G4X(devid) || \
- IS_IGDNG(devid))
-
-#define IS_9XX(devid) (IS_915(devid) || \
- IS_945(devid) || \
- IS_965(devid))
+++ /dev/null
-#include "intel_context.h"
-#include "intel_tex.h"
-#include "intel_chipset.h"
-
-
-
-
-int intel_compressed_num_bytes(GLuint mesaFormat)
-{
- int bytes = 0;
- switch(mesaFormat) {
-
- case MESA_FORMAT_RGB_FXT1:
- case MESA_FORMAT_RGBA_FXT1:
- case MESA_FORMAT_RGB_DXT1:
- case MESA_FORMAT_RGBA_DXT1:
- bytes = 2;
- break;
-
- case MESA_FORMAT_RGBA_DXT3:
- case MESA_FORMAT_RGBA_DXT5:
- bytes = 4;
- default:
- break;
- }
-
- return bytes;
-}
* Michel Dänzer <michel@tungstengraphics.com>
*/
-#include "intel_mipmap_tree.h"
#include "intel_tex_layout.h"
-#include "intel_context.h"
void intel_get_texture_alignment_unit(GLenum internalFormat, GLuint *w, GLuint *h)
{
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