* Makefile.am (CPU_DOCS): Add c-riscv.texi.
* Makefile.in: Regenerate.
* doc/all.texi: Set RISCV.
* doc/as.texinfo: Add RISCV options.
Add RISC-V-Dependent node.
Include c-riscv.texi.
* doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts.
+2016-11-04 Palmer Dabbelt <palmer@dabbelt.com>
+ Andrew Waterman <andrew@sifive.com>
+
+ * Makefile.am (CPU_DOCS): Add c-riscv.texi.
+ * Makefile.in: Regenerate.
+ * doc/all.texi: Set RISCV.
+ * doc/as.texinfo: Add RISCV options.
+ Add RISC-V-Dependent node.
+ Include c-riscv.texi.
+ * doc/c-riscv.texi: Rename RISC-V Options to RISC-V-Opts.
+
2016-11-03 Graham Markall <graham.markall@embecosm.com>
* testsuite/gas/arc/nps400-6.s: Change ldbit tests so that limm
c-pj.texi \
c-ppc.texi \
c-rl78.texi \
+ c-riscv.texi \
c-rx.texi \
c-s390.texi \
c-score.texi \
c-pj.texi \
c-ppc.texi \
c-rl78.texi \
+ c-riscv.texi \
c-rx.texi \
c-s390.texi \
c-score.texi \
@set PJ
@set PPC
@set RL78
+@set RISCV
@set RX
@set S390
@set SCORE
[@b{-mint-register=@var{number}}]
[@b{-mgcc-abi}|@b{-mrx-abi}]
@end ifset
+@ifset RISCV
+
+@emph{Target RISC-V options:}
+ [@b{-m32}|@b{-m64}]
+ [@b{-mrvc}]
+ [@b{-mhard-float}|@b{-msoft-float}]
+@end ifset
@ifset S390
@emph{Target s390 options:}
@ifset RL78
* RL78-Dependent:: RL78 Dependent Features
@end ifset
+@ifset RISCV
+* RISC-V-Dependent:: RISC-V Dependent Features
+@end ifset
@ifset RX
* RX-Dependent:: RX Dependent Features
@end ifset
@include c-rl78.texi
@end ifset
+@ifset RISCV
+@include c-riscv.texi
+@end ifset
+
@ifset RX
@include c-rx.texi
@end ifset
@cindex RISC-V support
@menu
-* RISC-V Options:: RISC-V Options
+* RISC-V-Opts:: RISC-V Options
@end menu
-@node RISC-V Options
+@node RISC-V-Opts
@section Options
The following table lists all availiable RISC-V specific options
Select the floating-point ABI, hard-float has F registers while soft-float
doesn't.
-@cindex @samp{-march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}} option, RISC-V
-@item -march=RV{32,64}{G,I}{M,}{A,}{F,}{D,}{C,}
+@cindex @samp{-march=ISA} option, RISC-V
+@item -march=ISA
Select the base isa, as specified by ISA. For example -march=RV32IMA.
@end table