children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
[system.disk0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 3 2012 13:46:22
-gem5 started Feb 3 2012 13:46:34
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:47:49
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 106949500
Exiting @ tick 1897464893500 because m5_exit instruction encountered
sim_ticks 1897464893500 # Number of ticks simulated
final_tick 1897464893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 100310 # Simulator instruction rate (inst/s)
-host_tick_rate 3391719918 # Simulator tick rate (ticks/s)
-host_mem_usage 326488 # Number of bytes of host memory used
-host_seconds 559.44 # Real time elapsed on the host
+host_inst_rate 189830 # Simulator instruction rate (inst/s)
+host_op_rate 189830 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6418636186 # Simulator tick rate (ticks/s)
+host_mem_usage 296280 # Number of bytes of host memory used
+host_seconds 295.62 # Real time elapsed on the host
sim_insts 56117221 # Number of instructions simulated
+sim_ops 56117221 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30408512 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1099328 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10470144 # Number of bytes written to this memory
system.l2c.sampled_refs 433566 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.725486 # Average number of references to valid blocks.
system.l2c.warmup_cycle 9252063000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 12005.589305 # Average occupied blocks per context
-system.l2c.occ_blocks::1 237.479904 # Average occupied blocks per context
-system.l2c.occ_blocks::2 22866.713220 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.183191 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.003624 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.348918 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1720206 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 147304 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 22866.713220 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 4068.067496 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 7937.521810 # Average occupied blocks per requestor
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+system.l2c.occ_blocks::cpu1.data 110.995347 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.348918 # Average percentage of cache occupancy
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+system.l2c.occ_percent::cpu0.data 0.121117 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.001930 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.001694 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.535733 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 955732 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 764474 # number of ReadReq hits
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system.l2c.ReadReq_hits::total 1867510 # number of ReadReq hits
-system.l2c.Writeback_hits::0 827202 # number of Writeback hits
+system.l2c.Writeback_hits::writebacks 827202 # number of Writeback hits
system.l2c.Writeback_hits::total 827202 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 175 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 45 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data 175 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 45 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 220 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 29 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 27 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 29 # number of SCUpgradeReq hits
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system.l2c.SCUpgradeReq_hits::total 56 # number of SCUpgradeReq hits
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system.l2c.ReadExReq_hits::total 179275 # number of ReadExReq hits
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system.l2c.demand_hits::total 2046785 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1888386 # number of overall hits
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system.l2c.overall_hits::total 2046785 # number of overall hits
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system.l2c.ReadReq_misses::total 309626 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 2447 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 562 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data 2447 # number of UpgradeReq misses
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system.l2c.UpgradeReq_misses::total 3009 # number of UpgradeReq misses
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system.l2c.SCUpgradeReq_misses::total 129 # number of SCUpgradeReq misses
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system.l2c.ReadExReq_misses::total 124634 # number of ReadExReq misses
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system.l2c.overall_misses::total 434260 # number of overall misses
-system.l2c.ReadReq_miss_latency 16117985000 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 4084000 # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency 629500 # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 6538201500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 22656186500 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 22656186500 # number of overall miss cycles
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system.l2c.ReadReq_accesses::total 2177136 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 827202 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 827202 # number of Writeback accesses(hits+misses)
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41697 # number of replacements
system.iocache.tagsinuse 0.463236 # Cycle average of tags in use
system.iocache.sampled_refs 41713 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1709322783000 # Cycle when the warmup percentage was hit.
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.iew.wb_fanout 0.742958 # average fanout of values written-back
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system.cpu0.commit.commitNonSpecStalls 637663 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 648245 # The number of times a branch was mispredicted
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system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu0.commit.loads 8594447 # Number of loads committed
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system.cpu0.quiesceCycles 3682779567 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu0.committedInsts 50529139 # Number of Instructions Simulated
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system.cpu0.committedInsts_total 50529139 # Number of Instructions Simulated
system.cpu0.cpi 2.219390 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 2.219390 # CPI: Total CPI of All Threads
system.cpu0.icache.sampled_refs 970922 # Sample count of references to valid blocks.
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system.cpu0.icache.blocked_cycles::no_mshrs 1297498 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 107 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
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-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11963.801814 # average ReadReq mshr miss latency
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-system.cpu0.icache.overall_avg_mshr_miss_latency 11963.801814 # average overall mshr miss latency
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-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu0.dcache.blocked_cycles::no_mshrs 888039305 # number of cycles access was blocked
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system.cpu0.dcache.blocked::no_mshrs 98700 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 24000 # average number of cycles each access was blocked
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.iew.wb_fanout 0.731621 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts 5811574 # The number of committed instructions
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system.cpu1.commit.commitSquashedInsts 1309607 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 75493 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 100450 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
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system.cpu1.commit.loads 1153406 # Number of loads committed
system.cpu1.idleCycles 697375 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 3784961926 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 5588082 # Number of Instructions Simulated
+system.cpu1.committedOps 5588082 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 5588082 # Number of Instructions Simulated
system.cpu1.cpi 1.783238 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 1.783238 # CPI: Total CPI of All Threads
system.cpu1.icache.sampled_refs 111117 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 8.431635 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1874818624000 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.blocked_cycles::no_mshrs 96999 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.icache.cache_copies 0 # number of cache copies performed
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system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu1.dcache.StoreCondReq_accesses::total 15618 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 1941190 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 1941190 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1941190 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 1941190 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 1941190 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1941190 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.086383 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.223140 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.081053 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044500 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.136216 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.136216 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 16774.910398 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 32825.555028 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13096.556381 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12057.553957 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 26355.910764 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 26355.910764 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.086383 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.223140 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.081053 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044500 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.136216 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.136216 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 86281997 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 6886 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 35937 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits 62835 # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits 134042 # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits 295 # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits 196877 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 196877 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses 43747 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 23797 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 1186 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses 695 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 67544 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 67544 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 555340000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency 753314485 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 11632000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 6287000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency 1308654485 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 1308654485 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 19116500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 320800500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 339917000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035456 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.033642 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.064908 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.044500 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.034795 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.034795 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.356184 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31655.859352 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 9807.757167 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9046.043165 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 19374.844324 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 35937 # number of writebacks
+system.cpu1.dcache.writebacks::total 35937 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62835 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 62835 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 134042 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 134042 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 295 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 295 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 196877 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 196877 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 196877 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 196877 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 43747 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 43747 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 23797 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 23797 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 1186 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 1186 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 695 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 695 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 67544 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 67544 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 67544 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 67544 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 555340000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 555340000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 753314485 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 753314485 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 11632000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 11632000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6287000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6287000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1308654485 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 1308654485 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1308654485 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 1308654485 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 19116500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 19116500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 320800500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 320800500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 339917000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 339917000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035456 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.033642 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.064908 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.044500 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034795 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 9807.757167 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9046.043165 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 6366 # number of quiesce instructions executed
children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
boot_cpu_frequency=500
boot_osflags=root=/dev/hda1 console=ttyS0
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/m5/system/binaries/console
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
physmem=system.physmem
readfile=tests/halt.sh
symbolfile=
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
[system.disk0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.disk2]
[system.disk2.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.intrctrl]
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
[system.simple_disk.disk]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
read_only=true
[system.terminal]
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 3 2012 13:46:22
-gem5 started Feb 3 2012 13:46:34
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:47:47
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1859850554500 because m5_exit instruction encountered
sim_ticks 1859850554500 # Number of ticks simulated
final_tick 1859850554500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 100457 # Simulator instruction rate (inst/s)
-host_tick_rate 3519496587 # Simulator tick rate (ticks/s)
-host_mem_usage 323652 # Number of bytes of host memory used
-host_seconds 528.44 # Real time elapsed on the host
+host_inst_rate 188989 # Simulator instruction rate (inst/s)
+host_op_rate 188989 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6621174751 # Simulator tick rate (ticks/s)
+host_mem_usage 292896 # Number of bytes of host memory used
+host_seconds 280.89 # Real time elapsed on the host
sim_insts 53085804 # Number of instructions simulated
+sim_ops 53085804 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 29820864 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1064000 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10193536 # Number of bytes written to this memory
system.l2c.sampled_refs 424249 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.673006 # Average number of references to valid blocks.
system.l2c.warmup_cycle 5619831000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 12305.465353 # Average occupied blocks per context
-system.l2c.occ_blocks::1 22620.354669 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.187767 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.345159 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1800764 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 22620.354669 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 4081.669847 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 8223.795506 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.345159 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.062281 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.125485 # Average percentage of cache occupancy
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system.iocache.ReadReq_accesses::total 173 # number of ReadReq accesses(hits+misses)
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system.iocache.WriteReq_accesses::total 41552 # number of WriteReq accesses(hits+misses)
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system.iocache.overall_accesses::total 41725 # number of overall (read+write) accesses
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system.iocache.blocked_cycles::no_mshrs 64612060 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 10475 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.iew.wb_fanout 0.742132 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 56280196 # The number of committed instructions
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system.cpu.commit.commitSquashedInsts 9036196 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 667545 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 701106 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 80658204 # Number of insts commited each cycle
-system.cpu.commit.count 56280196 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 15504446 # Number of memory references committed
system.cpu.commit.loads 9112319 # Number of loads committed
system.cpu.idleCycles 34112637 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 3603423163 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu.committedInsts 53085804 # Number of Instructions Simulated
+system.cpu.committedOps 53085804 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 53085804 # Number of Instructions Simulated
system.cpu.cpi 2.190256 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.190256 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 1005097 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 7.945272 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 23358400000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 509.963959 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.996023 # Average percentage of cache occupancy
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system.cpu.icache.ReadReq_hits::total 7985770 # number of ReadReq hits
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system.cpu.icache.ReadReq_misses::total 1065446 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1065446 # number of demand (read+write) misses
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system.cpu.icache.ReadReq_accesses::total 9051216 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_accesses::total 9051216 # number of overall (read+write) accesses
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-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 1315496 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 121 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 234 # number of writebacks
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-system.cpu.icache.ReadReq_mshr_miss_latency 12047333996 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency 12047333996 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.111069 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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-system.cpu.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.writebacks::total 234 # number of writebacks
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+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12047333996 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 12047333996 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 12047333996 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.111069 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1403406 # number of replacements
system.cpu.dcache.tagsinuse 511.996008 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1403918 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 8.609145 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 19221000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.996008 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999992 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 7453772 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 511.996008 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999992 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999992 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 7453772 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7453772 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 4220462 # number of WriteReq hits
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system.cpu.dcache.WriteReq_hits::total 4220462 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 192050 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 192050 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 192050 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 220033 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 220033 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 220033 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 11674234 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 11674234 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 11674234 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 11674234 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 11674234 # number of overall hits
system.cpu.dcache.overall_hits::total 11674234 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 1809182 # number of ReadReq misses
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system.cpu.dcache.ReadReq_misses::total 1809182 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 1936475 # number of WriteReq misses
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system.cpu.dcache.WriteReq_misses::total 1936475 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 22599 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 22599 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 22599 # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::0 2 # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses
system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::0 3745657 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses::total 3745657 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 3745657 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data 3745657 # number of overall misses
system.cpu.dcache.overall_misses::total 3745657 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 38930236000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 57815325976 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 338636000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency 28500 # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency 96745561976 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 96745561976 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 9262954 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.ReadReq_miss_latency::total 38930236000 # number of ReadReq miss cycles
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+system.cpu.dcache.LoadLockedReq_miss_latency::total 338636000 # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 28500 # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total 28500 # number of StoreCondReq miss cycles
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system.cpu.dcache.ReadReq_accesses::total 9262954 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 6156937 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_accesses::total 6156937 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 214649 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 214649 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 214649 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 220035 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 220035 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 220035 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 15419891 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 15419891 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15419891 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 15419891 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15419891 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15419891 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.195314 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.314519 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.105284 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::0 0.000009 # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.242911 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.242911 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 14250 # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 25828.729640 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 25828.729640 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.195314 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.314519 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.105284 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000009 # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.242911 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.242911 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839 # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 14250 # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 920169326 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 212000 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 101826 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 834955 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 721461 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 1637588 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 5103 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 2359049 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 2359049 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1087721 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 298887 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 17496 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses 2 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1386608 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1386608 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 24804888500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 8509686826 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 206420500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 22000 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 33314575326 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 33314575326 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 904009500 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1234178998 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 2138188498 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.117427 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.048545 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.081510 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000009 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.089923 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.089923 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 11000 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 834955 # number of writebacks
+system.cpu.dcache.writebacks::total 834955 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 721461 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 721461 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 1637588 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 1637588 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 5103 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 5103 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 2359049 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 2359049 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2359049 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2359049 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1087721 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1087721 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298887 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 298887 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17496 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 17496 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1386608 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1386608 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1386608 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1386608 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 24804888500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 24804888500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8509686826 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8509686826 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 206420500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 206420500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 33314575326 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 33314575326 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 33314575326 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 33314575326 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 904009500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 904009500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1234178998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1234178998 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2138188498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 2138188498 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.117427 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.048545 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.081510 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.089923 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 11000 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 6433 # number of quiesce instructions executed
[system]
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu0]
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prioritizeRequests=false
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size=32768
subblock_size=0
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-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 3 2012 14:00:40
-gem5 started Feb 3 2012 14:01:00
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:40:16
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2582494330500 because m5_exit instruction encountered
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sim_freq 1000000000000 # Frequency of simulated ticks
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.iew.iewIQFullEvents 62296 # Number of times the IQ has become full, causing a stall
system.cpu0.iew.iewLSQFullEvents 5639 # Number of times the LSQ has become full, causing a stall
system.cpu0.iew.memOrderViolationEvents 20483 # Number of memory order violations
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system.cpu0.iew.predictedNotTakenIncorrect 135852 # Number of branches that were predicted not taken incorrectly
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system.cpu0.iew.iewExecutedInsts 79552569 # Number of executed instructions
system.cpu0.iew.iewExecLoadInsts 42849690 # Number of load instructions executed
system.cpu0.iew.iewExecSquashedInsts 723060 # Number of squashed instructions skipped in execute
system.cpu0.iew.wb_rate 0.132406 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.537861 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts 41923639 # The number of committed instructions
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system.cpu0.commit.commitSquashedInsts 10377261 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 1044424 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 567428 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 108046246 # Number of insts commited each cycle
-system.cpu0.commit.count 41923639 # Number of instructions committed
+system.cpu0.commit.committedInsts 31935522 # Number of instructions committed
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system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 15936098 # Number of memory references committed
system.cpu0.commit.loads 9243307 # Number of loads committed
system.cpu0.timesIdled 1454145 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 242719810 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.quiesceCycles 4812449027 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 41797812 # Number of Instructions Simulated
-system.cpu0.committedInsts_total 41797812 # Number of Instructions Simulated
-system.cpu0.cpi 8.433071 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 8.433071 # CPI: Total CPI of All Threads
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-system.cpu0.ipc_total 0.118581 # IPC: Total IPC of All Threads
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+system.cpu0.committedOps 41797812 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 31809695 # Number of Instructions Simulated
+system.cpu0.cpi 11.081021 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 11.081021 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.090244 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.090244 # IPC: Total IPC of All Threads
system.cpu0.int_regfile_reads 354190813 # number of integer regfile reads
system.cpu0.int_regfile_writes 46128461 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3999 # number of floating regfile reads
system.cpu0.icache.sampled_refs 539299 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 10.826951 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 16020224000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 511.612990 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.999244 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_accesses::total 6422349 # number of ReadReq accesses(hits+misses)
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system.cpu0.icache.overall_accesses::total 6422349 # number of overall (read+write) accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450 # average ReadReq miss latency
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-system.cpu0.icache.overall_avg_miss_latency::0 14981.780450 # average overall miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 1633991 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 240 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 29665 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits 44065 # number of ReadReq MSHR hits
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-system.cpu0.icache.overall_mshr_hits 44065 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 539320 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 539320 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 539320 # number of overall MSHR misses
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-system.cpu0.icache.ReadReq_mshr_miss_latency 6552239991 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 6552239991 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 6552239991 # number of overall MSHR miss cycles
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-system.cpu0.icache.overall_mshr_uncacheable_latency 6685500 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.083976 # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
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-system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
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-system.cpu0.icache.demand_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12149.076598 # average overall mshr miss latency
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-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu0.icache.demand_mshr_miss_latency::total 6552239991 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598 # average overall mshr miss latency
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system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 372182 # number of replacements
-system.cpu0.dcache.tagsinuse 487.975562 # Cycle average of tags in use
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system.cpu0.dcache.total_refs 12779920 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 372694 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 34.290651 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 49147000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 487.992960 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -0.017397 # Average occupied blocks per context
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system.cpu0.dcache.demand_hits::total 12313322 # number of demand (read+write) hits
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system.cpu0.dcache.demand_misses::total 2327705 # number of demand (read+write) misses
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system.cpu0.dcache.WriteReq_accesses::total 6210780 # number of WriteReq accesses(hits+misses)
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system.cpu0.dcache.LoadLockedReq_accesses::total 231253 # number of LoadLockedReq accesses(hits+misses)
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system.cpu0.dcache.demand_accesses::total 14641027 # number of demand (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 14641027 # number of overall (read+write) accesses
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-system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0 0.158985 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.158985 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.158985 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 6780486 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 1857500 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 854 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 327766 # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits 223882 # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits 1685987 # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits 318 # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits 1909869 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 1909869 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 239530 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 178306 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 9724 # number of LoadLockedReq MSHR misses
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-system.cpu0.dcache.ReadReq_mshr_miss_latency 2943060000 # number of ReadReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
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-system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498 # number of overall MSHR uncacheable cycles
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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
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-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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-system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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-system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673 # average ReadReq mshr miss latency
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-system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333 # average overall mshr miss latency
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-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.iew.wb_rate 0.640894 # insts written-back per cycle
system.cpu1.iew.wb_fanout 0.545985 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts 38086237 # The number of committed instructions
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system.cpu1.commit.commitSquashedInsts 18573771 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 519501 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 450480 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 47701192 # Number of insts commited each cycle
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system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 12651383 # Number of memory references committed
system.cpu1.commit.loads 7112761 # Number of loads committed
system.cpu1.timesIdled 450197 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu1.idleCycles 18365285 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 5095139417 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 38061683 # Number of Instructions Simulated
-system.cpu1.committedInsts_total 38061683 # Number of Instructions Simulated
-system.cpu1.cpi 1.814944 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.814944 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.550981 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.550981 # IPC: Total IPC of All Threads
+system.cpu1.committedInsts 30012429 # Number of Instructions Simulated
+system.cpu1.committedOps 38061683 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 30012429 # Number of Instructions Simulated
+system.cpu1.cpi 2.301707 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 2.301707 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.434460 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.434460 # IPC: Total IPC of All Threads
system.cpu1.int_regfile_reads 222861231 # number of integer regfile reads
system.cpu1.int_regfile_writes 47167724 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4217 # number of floating regfile reads
system.cpu1.icache.sampled_refs 486098 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 15.809518 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 74234723000 # Cycle when the warmup percentage was hit.
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system.cpu1.icache.overall_misses::total 527035 # number of overall misses
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system.cpu1.icache.demand_accesses::total 8212010 # number of demand (read+write) accesses
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system.cpu1.icache.overall_accesses::total 8212010 # number of overall (read+write) accesses
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-system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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-system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
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-system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14710.097047 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 1321997 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 170 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 18538 # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits 40914 # number of ReadReq MSHR hits
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-system.cpu1.icache.ReadReq_mshr_misses 486121 # number of ReadReq MSHR misses
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-system.cpu1.icache.demand_mshr_miss_latency 5799471497 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 5799471497 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency 2517500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 2517500 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.059196 # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
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-system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11930.098673 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 272200 # number of replacements
system.cpu1.dcache.tagsinuse 447.953212 # Cycle average of tags in use
system.cpu1.dcache.sampled_refs 272587 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 38.212252 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 66688833000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 447.953212 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.874909 # Average percentage of cache occupancy
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system.cpu1.dcache.ReadReq_hits::total 7085363 # number of ReadReq hits
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system.cpu1.dcache.WriteReq_hits::total 3139669 # number of WriteReq hits
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system.cpu1.dcache.demand_hits::total 10225032 # number of demand (read+write) hits
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system.cpu1.dcache.overall_hits::total 10225032 # number of overall hits
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system.cpu1.dcache.WriteReq_misses::total 1273508 # number of WriteReq misses
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system.cpu1.dcache.LoadLockedReq_misses::total 12669 # number of LoadLockedReq misses
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system.cpu1.dcache.StoreCondReq_misses::total 11046 # number of StoreCondReq misses
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system.cpu1.dcache.demand_misses::total 1596795 # number of demand (read+write) misses
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system.cpu1.dcache.overall_misses::total 1596795 # number of overall misses
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system.cpu1.dcache.ReadReq_accesses::total 7408650 # number of ReadReq accesses(hits+misses)
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system.cpu1.dcache.WriteReq_accesses::total 4413177 # number of WriteReq accesses(hits+misses)
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system.cpu1.dcache.LoadLockedReq_accesses::total 88029 # number of LoadLockedReq accesses(hits+misses)
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system.cpu1.dcache.StoreCondReq_accesses::total 83668 # number of StoreCondReq accesses(hits+misses)
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system.cpu1.dcache.demand_accesses::total 11821827 # number of demand (read+write) accesses
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system.cpu1.dcache.overall_accesses::total 11821827 # number of overall (read+write) accesses
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-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
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-system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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-system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 7922.551150 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_mshrs 13033547 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 5494000 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 3077 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593 # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 223077 # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits 133946 # number of ReadReq MSHR hits
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-system.cpu1.dcache.LoadLockedReq_mshr_hits 1008 # number of LoadLockedReq MSHR hits
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-system.cpu1.dcache.ReadReq_mshr_misses 189341 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 116248 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 11661 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses 11046 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 305589 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 305589 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.cpu1.dcache.WriteReq_mshr_miss_latency 3452864547 # number of WriteReq MSHR miss cycles
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-system.cpu1.dcache.demand_mshr_miss_latency 5942801547 # number of demand (read+write) MSHR miss cycles
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-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.025557 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.132468 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
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-system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
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-system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8505.231112 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 4915.535035 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 223077 # number of writebacks
+system.cpu1.dcache.writebacks::total 223077 # number of writebacks
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+system.cpu1.dcache.ReadReq_mshr_hits::total 133946 # number of ReadReq MSHR hits
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+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200 # average ReadReq mshr miss latency
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+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132 # average overall mshr miss latency
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+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
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-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1308174844926 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1308174844926 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 55723 # number of quiesce instructions executed
[system]
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
flags_addr=268435504
gic_cpu_addr=520093952
init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
[system.cf0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
read_only=true
[system.cpu]
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 3 2012 14:00:40
-gem5 started Feb 3 2012 14:01:01
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:39:00
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 2503580880500 because m5_exit instruction encountered
sim_ticks 2503580880500 # Number of ticks simulated
final_tick 2503580880500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 56444 # Simulator instruction rate (inst/s)
-host_tick_rate 1840259079 # Simulator tick rate (ticks/s)
-host_mem_usage 413160 # Number of bytes of host memory used
-host_seconds 1360.45 # Real time elapsed on the host
-sim_insts 76789886 # Number of instructions simulated
+host_inst_rate 80550 # Simulator instruction rate (inst/s)
+host_op_rate 104045 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3392180683 # Simulator tick rate (ticks/s)
+host_mem_usage 382816 # Number of bytes of host memory used
+host_seconds 738.04 # Real time elapsed on the host
+sim_insts 59449329 # Number of instructions simulated
+sim_ops 76789886 # Number of ops (including micro ops) simulated
system.nvmem.bytes_read 64 # Number of bytes read from this memory
system.nvmem.bytes_inst_read 64 # Number of instructions bytes read from this memory
system.nvmem.bytes_written 0 # Number of bytes written to this memory
system.l2c.sampled_refs 150314 # Sample count of references to valid blocks.
system.l2c.avg_refs 11.946226 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 11478.014025 # Average occupied blocks per context
-system.l2c.occ_blocks::1 14356.915365 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.175141 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.219069 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1349535 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 153277 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 14304.535648 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 48.618373 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 3.761343 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 6047.704729 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 5430.309296 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.218270 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker 0.000742 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker 0.000057 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.092281 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.082860 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.394210 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 143695 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 9582 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 973305 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 376230 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1502812 # number of ReadReq hits
-system.l2c.Writeback_hits::0 630148 # number of Writeback hits
+system.l2c.Writeback_hits::writebacks 630148 # number of Writeback hits
system.l2c.Writeback_hits::total 630148 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 47 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data 47 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 47 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 17 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data 17 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 17 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 105970 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data 105970 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 105970 # number of ReadExReq hits
-system.l2c.demand_hits::0 1455505 # number of demand (read+write) hits
-system.l2c.demand_hits::1 153277 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker 143695 # number of demand (read+write) hits
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+system.l2c.demand_hits::cpu.data 482200 # number of demand (read+write) hits
system.l2c.demand_hits::total 1608782 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1455505 # number of overall hits
-system.l2c.overall_hits::1 153277 # number of overall hits
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+system.l2c.overall_hits::cpu.data 482200 # number of overall hits
system.l2c.overall_hits::total 1608782 # number of overall hits
-system.l2c.ReadReq_misses::0 36088 # number of ReadReq misses
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+system.l2c.ReadReq_misses::cpu.data 19000 # number of ReadReq misses
system.l2c.ReadReq_misses::total 36238 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 3252 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data 3252 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 3252 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 4 # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses
system.l2c.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 140397 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data 140397 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 140397 # number of ReadExReq misses
-system.l2c.demand_misses::0 176485 # number of demand (read+write) misses
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system.l2c.demand_misses::total 176635 # number of demand (read+write) misses
-system.l2c.overall_misses::0 176485 # number of overall misses
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system.l2c.overall_misses::total 176635 # number of overall misses
-system.l2c.ReadReq_miss_latency 1895542500 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 1059500 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 7383005500 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 9278548000 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 9278548000 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 1385623 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 153427 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker 7004000 # number of ReadReq miss cycles
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+system.l2c.ReadReq_miss_latency::cpu.inst 894670500 # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_miss_latency::cpu.data 1059500 # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total 1059500 # number of UpgradeReq miss cycles
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+system.l2c.demand_miss_latency::cpu.data 8376030000 # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total 9278548000 # number of demand (read+write) miss cycles
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+system.l2c.overall_miss_latency::total 9278548000 # number of overall miss cycles
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system.l2c.ReadReq_accesses::total 1539050 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 630148 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 630148 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 630148 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 3299 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data 3299 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 3299 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 21 # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data 21 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 21 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 246367 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data 246367 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246367 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 1631990 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 1785417 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 1631990 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 153427 # number of overall (read+write) accesses
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system.l2c.overall_accesses::total 1785417 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.026045 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.000978 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.027022 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.985753 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 0.190476 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.569869 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.108141 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.000978 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.109119 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.108141 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.000978 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.109119 # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52525.562514 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 12636950 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 12689475.562514 # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 325.799508 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52586.632905 # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 inf # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total inf # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0 52574.145111 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 61856986.666667 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 61909560.811778 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 52574.145111 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 61856986.666667 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 61909560.811778 # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000932 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.001667 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst 0.017254 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data 0.048073 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data 0.985753 # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data 0.190476 # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data 0.569869 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker 0.000932 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker 0.001667 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst 0.017254 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data 0.248438 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker 0.000932 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker 0.001667 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst 0.017254 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data 0.248438 # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792 # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368 # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 325.799508 # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905 # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792 # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52548.228637 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 102643 # number of writebacks
-system.l2c.ReadReq_mshr_hits 94 # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits 94 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 94 # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses 36144 # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses 3252 # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses 4 # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses 140397 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 176541 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 176541 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 1450468000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 131324500 # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency 160000 # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 5639183500 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 7089651500 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 7089651500 # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131770082500 # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency 32364127897 # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 164134210397 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.026085 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 0.235578 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 0.261663 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 0.985753 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total inf # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0 0.190476 # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1 inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total inf # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 0.569869 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 inf # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total inf # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.108175 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.150651 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 1.258827 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.108175 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.150651 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 1.258827 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40000 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40158.668525 # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks 102643 # number of writebacks
+system.l2c.writebacks::total 102643 # number of writebacks
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+system.l2c.overall_mshr_hits::cpu.data 80 # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total 94 # number of overall MSHR hits
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+system.l2c.UpgradeReq_mshr_misses::total 3252 # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses
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+system.l2c.ReadExReq_mshr_misses::total 140397 # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker 134 # number of demand (read+write) MSHR misses
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+system.l2c.demand_mshr_misses::cpu.inst 17074 # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data 159317 # number of demand (read+write) MSHR misses
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+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker 5376000 # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker 651000 # number of ReadReq MSHR miss cycles
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+system.l2c.UpgradeReq_mshr_miss_latency::total 131324500 # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data 160000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total 160000 # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data 5639183500 # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total 5639183500 # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker 5376000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker 651000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst 685402500 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data 6398222000 # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total 7089651500 # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker 5376000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker 651000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst 685402500 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data 6398222000 # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total 7089651500 # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst 4738500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000 # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500 # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 32364127897 # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total 32364127897 # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst 4738500 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897 # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164134210397 # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.047871 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.985753 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data 0.190476 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.569869 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000932 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.001667 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst 0.017240 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data 0.248313 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 40000 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.iew.iewIQFullEvents 84296 # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents 7341 # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents 32675 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 852505 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 852504 # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect 256815 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1109320 # Number of branch mispredicts detected at execute
+system.cpu.iew.branchMispredicts 1109319 # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts 123469909 # Number of executed instructions
system.cpu.iew.iewExecLoadInsts 52917262 # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts 3434775 # Number of squashed instructions skipped in execute
system.cpu.iew.wb_rate 0.209988 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.543006 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 76940267 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 59599710 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 76940267 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 27835988 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1499707 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 978113 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 151014616 # Number of insts commited each cycle
-system.cpu.commit.count 76940267 # Number of instructions committed
+system.cpu.commit.committedInsts 59599710 # Number of instructions committed
+system.cpu.commit.committedOps 76940267 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27459843 # Number of memory references committed
system.cpu.commit.loads 15680763 # Number of loads committed
system.cpu.timesIdled 1877181 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 260374175 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 4591130340 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 76789886 # Number of Instructions Simulated
-system.cpu.committedInsts_total 76789886 # Number of Instructions Simulated
-system.cpu.cpi 5.416643 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 5.416643 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.184616 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.184616 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 59449329 # Number of Instructions Simulated
+system.cpu.committedOps 76789886 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 59449329 # Number of Instructions Simulated
+system.cpu.cpi 6.996604 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 6.996604 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.142926 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.142926 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 559798057 # number of integer regfile reads
system.cpu.int_regfile_writes 89741069 # number of integer regfile writes
system.cpu.fp_regfile_reads 8257 # number of floating regfile reads
system.cpu.icache.sampled_refs 991689 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13.144904 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 6445921000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 511.615293 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.999249 # Average percentage of cache occupancy
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system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 572893 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 336628 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 2716799 # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits 1453 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 3053427 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 3053427 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 385916 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 249574 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 12049 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses 21 # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 635490 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 635490 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 5245615500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 8926036935 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 161663500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency 398500 # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 14171652435 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 14171652435 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 42287348315 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.025491 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024393 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.038446 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0 0.000074 # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.025048 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.025048 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476 # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 572893 # number of writebacks
+system.cpu.dcache.writebacks::total 572893 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 336628 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 336628 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2716799 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 2716799 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1453 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3053427 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3053427 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3053427 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3053427 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385916 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385916 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249574 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249574 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12049 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12049 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 21 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 21 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 635490 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 635490 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 635490 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 635490 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5245615500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5245615500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8926036935 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8926036935 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 161663500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 161663500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 398500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 398500 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14171652435 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 14171652435 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14171652435 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 14171652435 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 42287348315 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 42287348315 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.025491 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.038446 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000074 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025048 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1307927966543 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1307927966543 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 87993 # number of quiesce instructions executed
[system]
type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
acpi_description_table_pointer=system.acpi_description_table_pointer
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
e820_table=system.e820_table
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
load_addr_mask=18446744073709551615
mem_mode=timing
memories=system.physmem
oem_revision=0
oem_table_id=
+[system.apicbridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
[system.bridge]
type=Bridge
delay=50000
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
type=IntrControl
sys=system
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
[system.iobus]
type=Bus
block_size=64
use_default_range=true
width=64
default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
[system.iocache]
type=BaseCache
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.membus.badaddr_responder]
type=IsaFake
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
-Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 3 2012 12:36:19
-gem5 started Feb 3 2012 12:37:07
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:31:16
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5163317092500 because m5_exit instruction encountered
sim_ticks 5163317092500 # Number of ticks simulated
final_tick 5163317092500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 210982 # Simulator instruction rate (inst/s)
-host_tick_rate 1295931182 # Simulator tick rate (ticks/s)
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-host_seconds 3984.25 # Real time elapsed on the host
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+host_op_rate 364169 # Simulator op (including micro ops) rate (op/s)
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system.physmem.bytes_read 15861056 # Number of bytes read from this memory
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system.physmem.bytes_written 12134976 # Number of bytes written to this memory
system.l2c.sampled_refs 200841 # Sample count of references to valid blocks.
system.l2c.avg_refs 18.809212 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.l2c.Writeback_accesses::total 1603120 # number of Writeback accesses(hits+misses)
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 47580 # number of replacements
system.iocache.tagsinuse 0.183883 # Cycle average of tags in use
system.iocache.sampled_refs 47596 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 4996389534000 # Cycle when the warmup percentage was hit.
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system.iocache.blocked_cycles::no_mshrs 68485452 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 11259 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.cpu.iew.wb_rate 1.850453 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.573064 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 840604148 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 426565585 # The number of committed instructions
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system.cpu.commit.commitSquashedInsts 30510484 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1519690 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1250933 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 302314482 # Number of insts commited each cycle
-system.cpu.commit.count 840604148 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 23747567 # Number of memory references committed
system.cpu.commit.loads 15324009 # Number of loads committed
system.cpu.timesIdled 2858532 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 155577248 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.quiesceCycles 9864170951 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 840604148 # Number of Instructions Simulated
-system.cpu.committedInsts_total 840604148 # Number of Instructions Simulated
-system.cpu.cpi 0.550153 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.550153 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.817677 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.817677 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 426565585 # Number of Instructions Simulated
+system.cpu.committedOps 840604148 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 426565585 # Number of Instructions Simulated
+system.cpu.cpi 1.084149 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.084149 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.922382 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.922382 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1406313694 # number of integer regfile reads
system.cpu.int_regfile_writes 857070459 # number of integer regfile writes
system.cpu.fp_regfile_reads 62 # number of floating regfile reads
system.cpu.icache.sampled_refs 1020665 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 8.413769 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 56648796000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 509.928344 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.995954 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0 8587640 # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst 509.928344 # Average occupied blocks per requestor
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system.cpu.icache.ReadReq_hits::total 8587640 # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses::0 1084449 # number of ReadReq misses
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system.cpu.icache.ReadReq_misses::total 1084449 # number of ReadReq misses
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system.cpu.icache.demand_misses::total 1084449 # number of demand (read+write) misses
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system.cpu.icache.overall_misses::total 1084449 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 16282601991 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency 16282601991 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0 9672089 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_miss_latency::total 16282601991 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 16282601991 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 9672089 # number of ReadReq accesses(hits+misses)
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system.cpu.icache.overall_accesses::total 9672089 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0 0.112121 # miss rate for ReadReq accesses
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-system.cpu.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::0 15014.631385 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 15014.631385 # average overall miss latency
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-system.cpu.icache.overall_avg_miss_latency::total inf # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 2694492 # number of cycles access was blocked
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system.cpu.icache.blocked::no_mshrs 263 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 1551 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 60108 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses 1024341 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses 1024341 # number of overall MSHR misses
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-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12098.129912 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.itb_walker_cache.tagsinuse 6.010935 # Cycle average of tags in use
system.cpu.itb_walker_cache.sampled_refs 8564 # Sample count of references to valid blocks.
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+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 36169 # number of overall (read+write) accesses
system.cpu.itb_walker_cache.overall_accesses::total 36169 # number of overall (read+write) accesses
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system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
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system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
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-system.cpu.itb_walker_cache.overall_mshr_miss_latency 92324000 # number of overall MSHR miss cycles
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system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.038055 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.123297 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.123297 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14959.217746 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33453.979457 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17144.672676 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 27702492 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 4792 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 1550496 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 1018010 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 22803 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 1040813 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 1040813 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 1371571 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 297402 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 1668973 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 1668973 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 18013626000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 9484899492 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 27498525492 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 27498525492 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 85207760000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1392508500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 86600268500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.101123 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.035345 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.075940 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.075940 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13133.571649 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31892.520871 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16476.315370 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 1550496 # number of writebacks
+system.cpu.dcache.writebacks::total 1550496 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1018010 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 1018010 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 22803 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 22803 # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 1040813 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 1040813 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 1040813 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 1040813 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1371571 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1371571 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 297402 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 297402 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1668973 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1668973 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1668973 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1668973 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 18013626000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 18013626000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 9484899492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 9484899492 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 27498525492 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 27498525492 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 27498525492 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 27498525492 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 85207760000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 85207760000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1392508500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1392508500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 86600268500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 86600268500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.101123 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.035345 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075940 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13133.571649 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31892.520871 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16476.315370 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=200000000
time_sync_spin_threshold=200000
[system]
type=SparcSystem
children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
-boot_cpu_frequency=1
boot_osflags=a
hypervisor_addr=1099243257856
hypervisor_bin=/dist/m5/system/binaries/q_new.bin
kernel=
load_addr_mask=1099511627775
mem_mode=atomic
-memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
+memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc
num_work_ids=16
nvram=system.nvram
nvram_addr=133429198848
system=system
tracer=system.cpu.tracer
width=1
+workload=
dcache_port=system.membus.port[11]
icache_port=system.membus.port[10]
image=system.disk0.image
pio_addr=134217728000
pio_latency=2
-platform=system.t1000
system=system
pio=system.iobus.port[15]
pio_addr=0
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
pio_addr=644245094400
pio_latency=2
pio_size=4294967296
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=549755813888
pio_latency=2
pio_size=4294967296
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473024
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473088
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473152
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=725849473216
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407616
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407680
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407744
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=734439407808
pio_latency=2
pio_size=8
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=648540061696
pio_latency=2
pio_size=16384
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=1095216660480
pio_latency=2
pio_size=268435456
-platform=system.t1000
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
type=DumbTOD
pio_addr=1099255906296
pio_latency=2
-platform=system.t1000
system=system
time=Thu Jan 1 00:00:00 2009
pio=system.membus.port[1]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:05:05
-gem5 started Jan 23 2012 06:26:23
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:02:46
gem5 executing on zizzer
-command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
Global frequency set at 2000000000 ticks per second
- 0: system.t1000.htod: Real-time clock set to Thu Jan 1 00:00:00 2009
-
- 0: system.t1000.htod: Real-time clock set to 1230768000
info: No kernel set for full system simulation. Assuming you know what you're doing...
info: Entering event queue @ 0. Starting simulation...
info: Ignoring write to SPARC ERROR regsiter
sim_ticks 2233777512 # Number of ticks simulated
final_tick 2233777512 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 2000000000 # Frequency of simulated ticks
-host_inst_rate 3505728 # Simulator instruction rate (inst/s)
-host_tick_rate 3512989 # Simulator tick rate (ticks/s)
-host_mem_usage 500940 # Number of bytes of host memory used
-host_seconds 635.86 # Real time elapsed on the host
-sim_insts 2229160714 # Number of instructions simulated
+host_inst_rate 4520258 # Simulator instruction rate (inst/s)
+host_op_rate 4522035 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 4531400 # Simulator tick rate (ticks/s)
+host_mem_usage 500812 # Number of bytes of host memory used
+host_seconds 492.96 # Real time elapsed on the host
+sim_insts 2228284650 # Number of instructions simulated
+sim_ops 2229160714 # Number of ops (including micro ops) simulated
system.hypervisor_desc.bytes_read 16792 # Number of bytes read from this memory
system.hypervisor_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.hypervisor_desc.bytes_written 0 # Number of bytes written to this memory
system.hypervisor_desc.num_other 0 # Number of other requests responded to by this memory
system.hypervisor_desc.bw_read 15035 # Total read bandwidth from this memory (bytes/s)
system.hypervisor_desc.bw_total 15035 # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read 1128688 # Number of bytes read from this memory
+system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
+system.rom.bytes_written 0 # Number of bytes written to this memory
+system.rom.num_reads 195123 # Number of read requests responded to by this memory
+system.rom.num_writes 0 # Number of write requests responded to by this memory
+system.rom.num_other 0 # Number of other requests responded to by this memory
+system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
system.physmem2.bytes_read 9813991967 # Number of bytes read from this memory
system.physmem2.bytes_inst_read 8318106840 # Number of instructions bytes read from this memory
system.physmem2.bytes_written 897268422 # Number of bytes written to this memory
system.nvram.bw_read 254 # Total read bandwidth from this memory (bytes/s)
system.nvram.bw_write 82 # Write bandwidth from this memory (bytes/s)
system.nvram.bw_total 337 # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
-system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
-system.partition_desc.bytes_written 0 # Number of bytes written to this memory
-system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
-system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
-system.partition_desc.num_other 0 # Number of other requests responded to by this memory
-system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read 1128688 # Number of bytes read from this memory
-system.rom.bytes_inst_read 432296 # Number of instructions bytes read from this memory
-system.rom.bytes_written 0 # Number of bytes written to this memory
-system.rom.num_reads 195123 # Number of read requests responded to by this memory
-system.rom.num_writes 0 # Number of write requests responded to by this memory
-system.rom.num_other 0 # Number of other requests responded to by this memory
-system.rom.bw_read 1010564 # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read 387054 # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total 1010564 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read 709825348 # Number of bytes read from this memory
system.physmem.bytes_inst_read 612291324 # Number of instructions bytes read from this memory
system.physmem.bytes_written 15400223 # Number of bytes written to this memory
system.physmem.bw_inst_read 548211557 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write 13788502 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total 649326593 # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read 4846 # Number of bytes read from this memory
+system.partition_desc.bytes_inst_read 0 # Number of instructions bytes read from this memory
+system.partition_desc.bytes_written 0 # Number of bytes written to this memory
+system.partition_desc.num_reads 608 # Number of read requests responded to by this memory
+system.partition_desc.num_writes 0 # Number of write requests responded to by this memory
+system.partition_desc.num_other 0 # Number of other requests responded to by this memory
+system.partition_desc.bw_read 4339 # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total 4339 # Total bandwidth to/from this memory (bytes/s)
system.cpu.numCycles 2233777513 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2229160714 # Number of instructions executed
+system.cpu.committedInsts 2228284650 # Number of instructions committed
+system.cpu.committedOps 2229160714 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1839325658 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 14608322 # Number of float alu accesses
system.cpu.num_func_calls 44037246 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:21
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
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final_tick 274500333500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 601856964 # Number of instructions simulated
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system.physmem.bytes_read 5894016 # Number of bytes read from this memory
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system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 349039879 # Number of Integer instructions committed
system.cpu.comFloats 24 # Number of Floating Point instructions committed
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system.cpu.cpi 0.912178 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.912178 # CPI: Total CPI of All Threads
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+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.006442 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002958 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73797 # number of replacements
system.cpu.l2cache.tagsinuse 17695.095192 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 89683 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.969593 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1638.137841 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16056.957351 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.049992 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.490019 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 170051 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 408188 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 194105 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 364156 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 364156 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 32019 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 60075 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 92094 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 92094 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1674917000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3134446000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 4809363000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 4809363000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 202070 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 408188 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 254180 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 456250 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 456250 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.158455 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.236348 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.201850 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.201850 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52222.327187 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52222.327187 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16056.957351 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 28.224139 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1609.913702 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.490019 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000861 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.049131 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.540011 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data 170051 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 170051 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 408188 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 408188 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 194105 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 194105 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 364156 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 364156 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 364156 # number of overall hits
+system.cpu.l2cache.overall_hits::total 364156 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 31164 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 32019 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 60075 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 60075 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 91239 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 92094 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 855 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 91239 # number of overall misses
+system.cpu.l2cache.overall_misses::total 92094 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 44769000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1630148000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1674917000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3134446000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3134446000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 44769000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4764594000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 4809363000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 44769000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4764594000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 4809363000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 855 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 201215 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 202070 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 408188 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 408188 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 254180 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 254180 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 855 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 456250 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 855 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 456250 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154879 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236348 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.200351 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.200351 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 1295000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 127 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 59345 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 32019 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 60075 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 92094 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 92094 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1281026000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2406899500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 3687925500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 3687925500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158455 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236348 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.201850 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.201850 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 59345 # number of writebacks
+system.cpu.l2cache.writebacks::total 59345 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 855 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31164 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 32019 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60075 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 60075 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 855 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 91239 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 92094 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 855 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 91239 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 92094 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 34345000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246681000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1281026000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2406899500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2406899500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 34345000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3653580500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 3687925500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 34345000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3653580500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 3687925500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154879 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236348 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200351 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:26
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 144450185500 # Number of ticks simulated
final_tick 144450185500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 205040 # Simulator instruction rate (inst/s)
-host_tick_rate 52370107 # Simulator tick rate (ticks/s)
-host_mem_usage 208620 # Number of bytes of host memory used
-host_seconds 2758.26 # Real time elapsed on the host
+host_inst_rate 270959 # Simulator instruction rate (inst/s)
+host_op_rate 270959 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69206896 # Simulator tick rate (ticks/s)
+host_mem_usage 211048 # Number of bytes of host memory used
+host_seconds 2087.22 # Real time elapsed on the host
sim_insts 565552443 # Number of instructions simulated
+sim_ops 565552443 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5936768 # Number of bytes read from this memory
system.physmem.bytes_inst_read 60416 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3797120 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.790402 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 601856963 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 601856963 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 84796787 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 4132184 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 276422432 # Number of insts commited each cycle
-system.cpu.commit.count 601856963 # Number of instructions committed
+system.cpu.commit.committedInsts 601856963 # Number of instructions committed
+system.cpu.commit.committedOps 601856963 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 153965363 # Number of memory references committed
system.cpu.commit.loads 114514042 # Number of loads committed
system.cpu.timesIdled 2221 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 68890 # Total number of cycles that the CPU has spent unscheduled due to idling
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system.cpu.committedInsts_total 565552443 # Number of Instructions Simulated
system.cpu.cpi 0.510829 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.510829 # CPI: Total CPI of All Threads
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-system.cpu.l2cache.occ_blocks::1 15917.792095 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.053220 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.485772 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 186750 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 423044 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 196218 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 382968 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 382968 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 32958 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 59804 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 92762 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 92762 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1133680000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2065878500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 3199558500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 3199558500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 219708 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 423044 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 256022 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 475730 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 475730 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.150008 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.233589 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.194989 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.194989 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34492.125008 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34492.125008 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15917.792095 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 36.116254 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1707.803688 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.485772 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001102 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.052118 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.538993 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data 186750 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 186750 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 423044 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 423044 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 196218 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 196218 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 382968 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 382968 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 382968 # number of overall hits
+system.cpu.l2cache.overall_hits::total 382968 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 944 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 32014 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 32958 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 59804 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 59804 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 944 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 91818 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 92762 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 944 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 91818 # number of overall misses
+system.cpu.l2cache.overall_misses::total 92762 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32444500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101235500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1133680000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2065878500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2065878500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 32444500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 3167114000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 3199558500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 32444500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 3167114000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 3199558500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 944 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 218764 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 219708 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 423044 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 423044 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 256022 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 256022 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 944 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 474786 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 475730 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 944 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 474786 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 475730 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.146340 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.233589 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.193388 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.193388 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34369.173729 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.560005 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34544.152565 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34369.173729 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34493.389096 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 370500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 72 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 59330 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 32958 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 59804 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 92762 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 92762 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1022345000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1877543500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 2899888500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 2899888500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.150008 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.233589 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.194989 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.194989 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 59330 # number of writebacks
+system.cpu.l2cache.writebacks::total 59330 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 944 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32014 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 32958 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 59804 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 59804 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 944 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 91818 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 92762 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 944 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 91818 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 92762 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29409000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 992936000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1022345000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1877543500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1877543500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29409000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2870479500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 2899888500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29409000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2870479500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 2899888500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.146340 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.233589 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193388 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:30
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 300930958000 # Number of ticks simulated
final_tick 300930958000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4527143 # Simulator instruction rate (inst/s)
-host_tick_rate 2263589972 # Simulator tick rate (ticks/s)
-host_mem_usage 198960 # Number of bytes of host memory used
-host_seconds 132.94 # Real time elapsed on the host
+host_inst_rate 5630967 # Simulator instruction rate (inst/s)
+host_op_rate 5630966 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2815505896 # Simulator tick rate (ticks/s)
+host_mem_usage 200704 # Number of bytes of host memory used
+host_seconds 106.88 # Real time elapsed on the host
sim_insts 601856964 # Number of instructions simulated
+sim_ops 601856964 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2782990928 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2407447588 # Number of instructions bytes read from this memory
system.physmem.bytes_written 152669504 # Number of bytes written to this memory
system.cpu.numCycles 601861917 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 601856964 # Number of instructions executed
+system.cpu.committedInsts 601856964 # Number of instructions committed
+system.cpu.committedOps 601856964 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 563959696 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1520 # Number of float alu accesses
system.cpu.num_func_calls 2395217 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:31
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
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final_tick 765623032000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2199350 # Simulator instruction rate (inst/s)
-host_tick_rate 2797795440 # Simulator tick rate (ticks/s)
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-host_seconds 273.65 # Real time elapsed on the host
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sim_insts 601856964 # Number of instructions simulated
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system.physmem.bytes_read 5889984 # Number of bytes read from this memory
system.physmem.bytes_inst_read 50880 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3797824 # Number of bytes written to this memory
system.cpu.numCycles 1531246064 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.ReadExReq_misses 60069 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 92031 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 92031 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1662024000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3123588000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 4785612000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 4785612000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 202027 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 408190 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 254163 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 456190 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 456190 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.158207 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.236340 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.201738 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.201738 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16101.078831 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 29.487971 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1692.948088 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.491366 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000900 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.051665 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.543931 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data 170065 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 170065 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 408190 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 408190 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 194094 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 194094 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data 364159 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 364159 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data 364159 # number of overall hits
+system.cpu.l2cache.overall_hits::total 364159 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 795 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 31167 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 31962 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 60069 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 60069 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 795 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 91236 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 92031 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 795 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 91236 # number of overall misses
+system.cpu.l2cache.overall_misses::total 92031 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 41340000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1620684000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1662024000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3123588000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3123588000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 41340000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4744272000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 4785612000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 41340000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4744272000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 4785612000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 795 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 201232 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 202027 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 408190 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 408190 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 254163 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 254163 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 795 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 455395 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 456190 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 795 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 455395 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 456190 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154881 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.236340 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.200345 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.200345 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 59341 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 31962 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 60069 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 92031 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 92031 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1278480000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2402760000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 3681240000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 3681240000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.158207 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.236340 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.201738 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.201738 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 59341 # number of writebacks
+system.cpu.l2cache.writebacks::total 59341 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 795 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31167 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 31962 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60069 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 60069 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 795 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 91236 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 92031 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 795 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 91236 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 92031 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 31800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1246680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1278480000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2402760000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2402760000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 31800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3649440000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 3681240000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3649440000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 3681240000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154881 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.236340 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200345 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:23
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:39:44
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 177116942500 # Number of ticks simulated
final_tick 177116942500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 89657 # Simulator instruction rate (inst/s)
-host_tick_rate 26362655 # Simulator tick rate (ticks/s)
-host_mem_usage 256136 # Number of bytes of host memory used
-host_seconds 6718.48 # Real time elapsed on the host
-sim_insts 602359810 # Number of instructions simulated
+host_inst_rate 193712 # Simulator instruction rate (inst/s)
+host_op_rate 204690 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60186856 # Simulator tick rate (ticks/s)
+host_mem_usage 223404 # Number of bytes of host memory used
+host_seconds 2942.78 # Real time elapsed on the host
+sim_insts 570051603 # Number of instructions simulated
+sim_ops 602359810 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5833792 # Number of bytes read from this memory
system.physmem.bytes_inst_read 46976 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3720320 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.835552 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.643966 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 602359861 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 570051654 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 602359861 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 100193357 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 6347 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 4062580 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 339017045 # Number of insts commited each cycle
-system.cpu.commit.count 602359861 # Number of instructions committed
+system.cpu.commit.committedInsts 570051654 # Number of instructions committed
+system.cpu.commit.committedOps 602359861 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 219173611 # Number of memory references committed
system.cpu.commit.loads 148952596 # Number of loads committed
system.cpu.rob.rob_writes 1419524916 # The number of ROB writes
system.cpu.timesIdled 37353 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 840358 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 602359810 # Number of Instructions Simulated
-system.cpu.committedInsts_total 602359810 # Number of Instructions Simulated
-system.cpu.cpi 0.588077 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.588077 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.700458 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.700458 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 570051603 # Number of Instructions Simulated
+system.cpu.committedOps 602359810 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 570051603 # Number of Instructions Simulated
+system.cpu.cpi 0.621407 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.621407 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.609252 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.609252 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3275977261 # number of integer regfile reads
system.cpu.int_regfile_writes 676006750 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.sampled_refs 765 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 97283.071895 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 657.275674 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.320935 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 74421550 # number of ReadReq hits
-system.cpu.icache.demand_hits 74421550 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 74421550 # number of overall hits
-system.cpu.icache.ReadReq_misses 996 # number of ReadReq misses
-system.cpu.icache.demand_misses 996 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 996 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 34937500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 34937500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 34937500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 74422546 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 74422546 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 74422546 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000013 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000013 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000013 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35077.811245 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35077.811245 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35077.811245 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 657.275674 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.320935 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.320935 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 74421550 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 74421550 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 74421550 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 74421550 # number of demand (read+write) hits
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-system.cpu.l2cache.ReadReq_miss_latency 1126263500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2003081500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 3129345000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 3129345000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 198679 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 395250 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 247382 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 446061 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 446061 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.165131 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.235890 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.204373 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.204373 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34326.919913 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34326.919913 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15926.163884 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 35.771827 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1845.364487 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.486028 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001092 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.056316 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.543436 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 30 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 165841 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 165871 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 395250 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 395250 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 189027 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 189027 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 30 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 354868 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 354898 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 30 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 354868 # number of overall hits
+system.cpu.l2cache.overall_hits::total 354898 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 735 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 32073 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 32808 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 58355 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 58355 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 735 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 90428 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 91163 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 735 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 90428 # number of overall misses
+system.cpu.l2cache.overall_misses::total 91163 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 25238000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1101025500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1126263500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2003081500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2003081500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 25238000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 3104107000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 3129345000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 25238000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 3104107000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 3129345000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 765 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 197914 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 198679 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 395250 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 395250 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 247382 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 247382 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 765 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 445296 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 446061 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 765 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 445296 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 446061 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.960784 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162055 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235890 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.960784 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.203074 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.960784 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.203074 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34337.414966 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.734450 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34325.790421 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34337.414966 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34326.834609 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 2057500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 352 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 58130 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 32798 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 58355 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 91153 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 91153 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1019340000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1822214500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 2841554500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 2841554500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165080 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235890 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.204351 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.204351 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.334106 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31226.364493 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.461104 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 58130 # number of writebacks
+system.cpu.l2cache.writebacks::total 58130 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 1 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 9 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 1 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 9 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 1 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 9 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 10 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 734 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32064 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 32798 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58355 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 58355 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 734 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 90419 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 91153 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 734 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 90419 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 91153 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22853000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 996487000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1019340000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1822214500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1822214500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22853000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2818701500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 2841554500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22853000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2818701500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 2841554500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162010 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235890 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.959477 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.203054 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:36:54
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:43:07
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 301191370000 # Number of ticks simulated
final_tick 301191370000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2998309 # Simulator instruction rate (inst/s)
-host_tick_rate 1499211130 # Simulator tick rate (ticks/s)
-host_mem_usage 210136 # Number of bytes of host memory used
-host_seconds 200.90 # Real time elapsed on the host
-sim_insts 602359851 # Number of instructions simulated
+host_inst_rate 3224710 # Simulator instruction rate (inst/s)
+host_op_rate 3407474 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1703801368 # Simulator tick rate (ticks/s)
+host_mem_usage 212692 # Number of bytes of host memory used
+host_seconds 176.78 # Real time elapsed on the host
+sim_insts 570051644 # Number of instructions simulated
+sim_ops 602359851 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2680160157 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2280298136 # Number of instructions bytes read from this memory
system.physmem.bytes_written 236359611 # Number of bytes written to this memory
system.cpu.numCycles 602382741 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 602359851 # Number of instructions executed
+system.cpu.committedInsts 570051644 # Number of instructions committed
+system.cpu.committedOps 602359851 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:40:26
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:45:54
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 796762926000 # Number of ticks simulated
final_tick 796762926000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1450316 # Simulator instruction rate (inst/s)
-host_tick_rate 1924652930 # Simulator tick rate (ticks/s)
-host_mem_usage 219100 # Number of bytes of host memory used
-host_seconds 413.98 # Real time elapsed on the host
-sim_insts 600398281 # Number of instructions simulated
+host_inst_rate 1806630 # Simulator instruction rate (inst/s)
+host_op_rate 1907867 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2531848956 # Simulator tick rate (ticks/s)
+host_mem_usage 221588 # Number of bytes of host memory used
+host_seconds 314.70 # Real time elapsed on the host
+sim_insts 568539343 # Number of instructions simulated
+sim_ops 600398281 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5759488 # Number of bytes read from this memory
system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3704704 # Number of bytes written to this memory
system.cpu.numCycles 1593525852 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 600398281 # Number of instructions executed
+system.cpu.committedInsts 568539343 # Number of instructions committed
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system.cpu.num_int_alu_accesses 533522639 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 1993546 # number of times a function call or return occured
system.cpu.icache.sampled_refs 643 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 886584.590980 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 577.728532 # Average occupied blocks per context
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-system.cpu.icache.ReadReq_misses 643 # number of ReadReq misses
-system.cpu.icache.demand_misses 643 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 643 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 34874000 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency 54236.391913 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency 54236.391913 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 433468 # number of replacements
system.cpu.dcache.tagsinuse 4094.222434 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 437564 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 537031000 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.overall_mshr_misses::cpu.data 437564 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 437564 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3386826000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3386826000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5180170000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 5180170000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8566996000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 8566996000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8566996000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8566996000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001284 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.003569 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002014 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 71804 # number of replacements
system.cpu.l2cache.tagsinuse 17904.014680 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 87286 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.718237 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1762.179345 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16141.835335 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.053777 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.492610 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 158918 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 392392 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 189297 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 348215 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 348215 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 31541 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 58451 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 89992 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 89992 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1640132000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3039452000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 4679584000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 4679584000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 190459 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 392392 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 247748 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 438207 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 438207 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.165605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.235929 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.205364 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.205364 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16141.835335 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 24.672100 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1737.507245 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.492610 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000753 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.053025 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.546387 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 27 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 158891 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 158918 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 392392 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 392392 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 189297 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 189297 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 27 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 348188 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 348215 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 27 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 348188 # number of overall hits
+system.cpu.l2cache.overall_hits::total 348215 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 616 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 30925 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 31541 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 58451 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 58451 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 616 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 89376 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 89992 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 616 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 89376 # number of overall misses
+system.cpu.l2cache.overall_misses::total 89992 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1608100000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1640132000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3039452000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3039452000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4647552000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 4679584000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4647552000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 4679584000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 643 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 189816 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 190459 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 392392 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 392392 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 247748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 247748 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 643 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 437564 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 438207 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 643 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 437564 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 438207 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.958009 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.162921 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235929 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.958009 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.204258 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.958009 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.204258 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 57886 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 31541 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 58451 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 89992 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 89992 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1261640000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2338040000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 3599680000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 3599680000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.165605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235929 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.205364 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.205364 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 57886 # number of writebacks
+system.cpu.l2cache.writebacks::total 57886 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 616 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30925 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 31541 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 58451 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 58451 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 616 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 89376 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 89992 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 616 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 89376 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 89992 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 24640000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1237000000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1261640000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2338040000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2338040000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3575040000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 3599680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3575040000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 3599680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.162921 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235929 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.958009 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.204258 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:17:40
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:12
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 408816360000 # Number of ticks simulated
final_tick 408816360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 175830 # Simulator instruction rate (inst/s)
-host_tick_rate 51139829 # Simulator tick rate (ticks/s)
-host_mem_usage 215728 # Number of bytes of host memory used
-host_seconds 7994.10 # Real time elapsed on the host
-sim_insts 1405604152 # Number of instructions simulated
+host_inst_rate 218783 # Simulator instruction rate (inst/s)
+host_op_rate 219472 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63832966 # Simulator tick rate (ticks/s)
+host_mem_usage 214000 # Number of bytes of host memory used
+host_seconds 6404.47 # Real time elapsed on the host
+sim_insts 1401188958 # Number of instructions simulated
+sim_ops 1405604152 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 6021376 # Number of bytes read from this memory
system.physmem.bytes_inst_read 81792 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3792448 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.812578 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.959383 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.loads 402512844 # Number of loads committed
system.cpu.rob.rob_writes 3363039880 # The number of ROB writes
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system.cpu.idleCycles 357787 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1405604152 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1405604152 # Number of Instructions Simulated
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-system.cpu.cpi_total 0.581695 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 1.719114 # IPC: Total IPC of All Threads
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+system.cpu.cpi_total 0.583528 # CPI: Total CPI of All Threads
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system.cpu.int_regfile_reads 2016058791 # number of integer regfile reads
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+system.cpu.dcache.demand_mshr_hits::total 2246356 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 2246356 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 2246356 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 212185 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 212185 # number of ReadReq MSHR misses
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+system.cpu.dcache.WriteReq_mshr_misses::total 267257 # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data 7 # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total 7 # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 479442 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 479442 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 479442 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 479442 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1589383500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1589383500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3625603341 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3625603341 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data 247000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total 247000 # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5214986841 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 5214986841 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5214986841 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 5214986841 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000958 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001602 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data 0.005279 # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001235 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7490.555412 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839 # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286 # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 75859 # number of replacements
system.cpu.l2cache.tagsinuse 17814.801426 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 91380 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.084154 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 2079.678027 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15735.123399 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.063467 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.480198 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 179822 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 426654 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 206842 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 386664 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 386664 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 33662 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 60422 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 94084 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 94084 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1145731000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2079178500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 3224909500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 3224909500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 213484 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 426654 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 267264 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 480748 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 480748 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.157679 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.226076 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.195703 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.195703 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34276.917435 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34276.917435 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15735.123399 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 94.212469 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1985.465558 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.480198 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.002875 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.060592 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.543665 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 179801 # number of ReadReq hits
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+system.cpu.l2cache.Writeback_hits::writebacks 426654 # number of Writeback hits
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+system.cpu.l2cache.Writeback_accesses::writebacks 426654 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 426654 # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::total 480748 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.983834 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.152622 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.226076 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.983834 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.193568 # miss rate for demand accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data 0.193568 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34231.220657 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34028.640687 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34410.951309 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34231.220657 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34277.546710 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 59257 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 33662 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 60422 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 94084 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 94084 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1043686000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1892150500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 2935836500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 2935836500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157679 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.226076 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.195703 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.195703 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 59257 # number of writebacks
+system.cpu.l2cache.writebacks::total 59257 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1278 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32384 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 60422 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 60422 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1278 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 92806 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 94084 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1278 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 92806 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 94084 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 39610000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1004076000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1043686000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1892150500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1892150500 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2896226500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 2935836500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 39610000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2896226500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 2935836500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.152622 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.226076 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.983834 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.193568 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30993.740219 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.311265 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.588693 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30993.740219 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31207.319570 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:18:03
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:17
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 744764119000 # Number of ticks simulated
final_tick 744764119000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3773289 # Simulator instruction rate (inst/s)
-host_tick_rate 1886650577 # Simulator tick rate (ticks/s)
-host_mem_usage 205844 # Number of bytes of host memory used
-host_seconds 394.75 # Real time elapsed on the host
-sim_insts 1489523295 # Number of instructions simulated
+host_inst_rate 4631105 # Simulator instruction rate (inst/s)
+host_op_rate 4644873 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2322443893 # Simulator tick rate (ticks/s)
+host_mem_usage 203508 # Number of bytes of host memory used
+host_seconds 320.68 # Real time elapsed on the host
+sim_insts 1485108101 # Number of instructions simulated
+sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 7326269637 # Number of bytes read from this memory
system.physmem.bytes_inst_read 5940452044 # Number of instructions bytes read from this memory
system.physmem.bytes_written 614672063 # Number of bytes written to this memory
system.cpu.numCycles 1489528239 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1489523295 # Number of instructions executed
+system.cpu.committedInsts 1485108101 # Number of instructions committed
+system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:19:05
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:19
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 2064258667000 # Number of ticks simulated
final_tick 2064258667000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1766930 # Simulator instruction rate (inst/s)
-host_tick_rate 2448703239 # Simulator tick rate (ticks/s)
-host_mem_usage 214556 # Number of bytes of host memory used
-host_seconds 843.00 # Real time elapsed on the host
-sim_insts 1489523295 # Number of instructions simulated
+host_inst_rate 2132645 # Simulator instruction rate (inst/s)
+host_op_rate 2138986 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2964317062 # Simulator tick rate (ticks/s)
+host_mem_usage 212372 # Number of bytes of host memory used
+host_seconds 696.37 # Real time elapsed on the host
+sim_insts 1485108101 # Number of instructions simulated
+sim_ops 1489523295 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5909952 # Number of bytes read from this memory
system.physmem.bytes_inst_read 70592 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3778240 # Number of bytes written to this memory
system.cpu.numCycles 4128517334 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1489523295 # Number of instructions executed
+system.cpu.committedInsts 1485108101 # Number of instructions committed
+system.cpu.committedOps 1489523295 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1319481298 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 8454127 # Number of float alu accesses
system.cpu.num_func_calls 1207835 # number of times a function call or return occured
system.cpu.icache.sampled_refs 1107 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1341564.503162 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 906.450625 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.442603 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1485111905 # number of ReadReq hits
-system.cpu.icache.demand_hits 1485111905 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1485111905 # number of overall hits
-system.cpu.icache.ReadReq_misses 1107 # number of ReadReq misses
-system.cpu.icache.demand_misses 1107 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 1107 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 61824000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 61824000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 61824000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1485113012 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses 1485113012 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55848.238482 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55848.238482 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55848.238482 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 906.450625 # Average occupied blocks per requestor
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 449125 # number of replacements
system.cpu.dcache.tagsinuse 4095.226955 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 453221 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1255.254644 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 566994000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.ReadReq_mshr_misses 193486 # number of ReadReq MSHR misses
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-system.cpu.dcache.SwapReq_mshr_misses 7 # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 453214 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 453214 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3439376000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 5377764000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency 371000 # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 8817140000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 8817140000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000481 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001557 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate 0.005279 # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.000796 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.000796 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693 # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 53000 # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.dcache.writebacks::total 407009 # number of writebacks
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+system.cpu.dcache.demand_mshr_miss_latency::total 8817140000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8817140000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8817140000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000481 # mshr miss rate for ReadReq accesses
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 74112 # number of replacements
system.cpu.l2cache.tagsinuse 17723.305524 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 89611 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.765989 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1873.919591 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15849.385934 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.057187 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.483685 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 162275 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 407009 # number of Writeback hits
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-system.cpu.l2cache.ReadReq_accesses 194593 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 407009 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 259735 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 454328 # number of demand (read+write) accesses
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-system.cpu.l2cache.ReadReq_miss_rate 0.166080 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.231101 # miss rate for ReadExReq accesses
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-system.cpu.l2cache.overall_miss_rate 0.203252 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15849.385934 # Average occupied blocks per requestor
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+system.cpu.l2cache.occ_blocks::cpu.data 1801.118460 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.483685 # Average percentage of cache occupancy
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+system.cpu.l2cache.occ_percent::cpu.data 0.054966 # Average percentage of cache occupancy
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+system.cpu.l2cache.overall_miss_rate::cpu.data 0.201315 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 59035 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 32318 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 60025 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 92343 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 92343 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1292720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2401000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 3693720000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 3693720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.166080 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.231101 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.203252 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.203252 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 59035 # number of writebacks
+system.cpu.l2cache.writebacks::total 59035 # number of writebacks
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+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 31215 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.231101 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996387 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.201315 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 9 2012 12:45:55
-gem5 started Feb 9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:08:06
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 586834596000 # Number of ticks simulated
final_tick 586834596000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 99458 # Simulator instruction rate (inst/s)
-host_tick_rate 35994653 # Simulator tick rate (ticks/s)
-host_mem_usage 253740 # Number of bytes of host memory used
-host_seconds 16303.38 # Real time elapsed on the host
-sim_insts 1621493982 # Number of instructions simulated
+host_inst_rate 106927 # Simulator instruction rate (inst/s)
+host_op_rate 197018 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71302744 # Simulator tick rate (ticks/s)
+host_mem_usage 220908 # Number of bytes of host memory used
+host_seconds 8230.18 # Real time elapsed on the host
+sim_insts 880025312 # Number of instructions simulated
+sim_ops 1621493982 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5879616 # Number of bytes read from this memory
system.physmem.bytes_inst_read 57024 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3743488 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.495458 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.672132 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1621493982 # The number of committed instructions
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system.cpu.commit.commitSquashedInsts 350742946 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 7896364 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1125303290 # Number of insts commited each cycle
-system.cpu.commit.count 1621493982 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 607228182 # Number of memory references committed
system.cpu.commit.loads 419042125 # Number of loads committed
system.cpu.rob.rob_writes 3992764754 # The number of ROB writes
system.cpu.timesIdled 21723 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 94408 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1621493982 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1621493982 # Number of Instructions Simulated
-system.cpu.cpi 0.723820 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.723820 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.381560 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.381560 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 880025312 # Number of Instructions Simulated
+system.cpu.committedOps 1621493982 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 880025312 # Number of Instructions Simulated
+system.cpu.cpi 1.333677 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.333677 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.749807 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.749807 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3268959976 # number of integer regfile reads
system.cpu.int_regfile_writes 1746565098 # number of integer regfile writes
system.cpu.fp_regfile_reads 12 # number of floating regfile reads
system.cpu.icache.sampled_refs 894 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 152721.416107 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 807.278486 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.394179 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_misses 1228 # number of ReadReq misses
-system.cpu.icache.demand_misses 1228 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 1228 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 43195500 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency 43195500 # number of overall miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency 35175.488599 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency 35175.488599 # average overall miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tagsinuse 4094.269422 # Cycle average of tags in use
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+system.cpu.dcache.demand_mshr_hits::total 3523 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3523 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3523 # number of overall MSHR hits
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+system.cpu.dcache.ReadReq_mshr_misses::total 213614 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249521 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 249521 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 463135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 463135 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 463135 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 463135 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 1523998500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 1523998500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2469759000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2469759000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3993757500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 3993757500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3993757500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 3993757500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000880 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001326 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.001075 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 7134.356831 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 9898.000569 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 8623.311777 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 73601 # number of replacements
system.cpu.l2cache.tagsinuse 17971.586292 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 89223 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 5.075451 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1981.498209 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15990.088083 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.060471 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.487979 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 181345 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 409999 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 190815 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 372160 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 372160 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 33162 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 58707 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 91869 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 91869 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1129684500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2008512000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 3138196500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 3138196500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 214507 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 409999 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 249522 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 464029 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 464029 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.154596 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.235278 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.197981 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.197981 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34159.471639 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34159.471639 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15990.088083 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 59.987883 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1921.510326 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.487979 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001831 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.058640 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.548449 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 181342 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 181345 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 409999 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 409999 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 190815 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 190815 # number of ReadExReq hits
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+system.cpu.l2cache.overall_hits::total 372160 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 891 # number of ReadReq misses
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+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1099141000 # number of ReadReq miss cycles
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+system.cpu.l2cache.Writeback_accesses::writebacks 409999 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 409999 # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::cpu.data 463135 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 464029 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996644 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.151072 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.235278 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996644 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.196439 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996644 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.196439 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34280.022447 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34059.713055 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34212.478921 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34280.022447 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.291015 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 58492 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 33162 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 58707 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 91869 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 91869 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1028173500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1819949000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 2848122500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 2848122500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.154596 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.235278 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.197981 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.197981 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 58492 # number of writebacks
+system.cpu.l2cache.writebacks::total 58492 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 891 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 32271 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 33162 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_mshr_misses::total 58707 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 891 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 90978 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 91869 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 891 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 90978 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 91869 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27674500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1000499000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1028173500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1819949000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1819949000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27674500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2820448000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 2848122500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27674500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2820448000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 2848122500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.151072 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.235278 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996644 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.196439 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.044893 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.036782 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:33:19
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:08:56
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 963992704000 # Number of ticks simulated
final_tick 963992704000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2202720 # Simulator instruction rate (inst/s)
-host_tick_rate 1309536712 # Simulator tick rate (ticks/s)
-host_mem_usage 204800 # Number of bytes of host memory used
-host_seconds 736.13 # Real time elapsed on the host
-sim_insts 1621493983 # Number of instructions simulated
+host_inst_rate 1632386 # Simulator instruction rate (inst/s)
+host_op_rate 3007760 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1788140018 # Simulator tick rate (ticks/s)
+host_mem_usage 210284 # Number of bytes of host memory used
+host_seconds 539.10 # Real time elapsed on the host
+sim_insts 880025313 # Number of instructions simulated
+sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11334586825 # Number of bytes read from this memory
system.physmem.bytes_inst_read 9492133912 # Number of instructions bytes read from this memory
system.physmem.bytes_written 864451000 # Number of bytes written to this memory
system.cpu.numCycles 1927985409 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1621493983 # Number of instructions executed
+system.cpu.committedInsts 880025313 # Number of instructions committed
+system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:37:10
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:11:10
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 1803258587000 # Number of ticks simulated
final_tick 1803258587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1279975 # Simulator instruction rate (inst/s)
-host_tick_rate 1423455894 # Simulator tick rate (ticks/s)
-host_mem_usage 213784 # Number of bytes of host memory used
-host_seconds 1266.82 # Real time elapsed on the host
-sim_insts 1621493983 # Number of instructions simulated
+host_inst_rate 972144 # Simulator instruction rate (inst/s)
+host_op_rate 1791227 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1992018099 # Simulator tick rate (ticks/s)
+host_mem_usage 219200 # Number of bytes of host memory used
+host_seconds 905.24 # Real time elapsed on the host
+sim_insts 880025313 # Number of instructions simulated
+sim_ops 1621493983 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 5725952 # Number of bytes read from this memory
system.physmem.bytes_inst_read 46208 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3712448 # Number of bytes written to this memory
system.cpu.numCycles 3606517174 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1621493983 # Number of instructions executed
+system.cpu.committedInsts 880025313 # Number of instructions committed
+system.cpu.committedOps 1621493983 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1621354493 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1643373.986150 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 660.186297 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.322357 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1186516018 # number of ReadReq hits
-system.cpu.icache.demand_hits 1186516018 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1186516018 # number of overall hits
-system.cpu.icache.ReadReq_misses 722 # number of ReadReq misses
-system.cpu.icache.demand_misses 722 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 722 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 40432000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 40432000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 40432000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1186516740 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1186516740 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1186516740 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000001 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000001 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000001 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 660.186297 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.322357 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.322357 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1186516018 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1186516018 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1186516018 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1186516018 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1186516018 # number of overall hits
+system.cpu.icache.overall_hits::total 1186516018 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 722 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 722 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 722 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 722 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 722 # number of overall misses
+system.cpu.icache.overall_misses::total 722 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 40432000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 40432000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 40432000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 40432000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 40432000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 40432000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1186516740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1186516740 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1186516740 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1186516740 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1186516740 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1186516740 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000001 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000001 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000001 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 722 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 722 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 722 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 38266000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 38266000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 38266000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000001 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000001 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000001 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 722 # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::total 722 # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total 722 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 38266000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 38266000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 38266000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 38266000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 38266000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for ReadReq accesses
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+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000001 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 437952 # number of replacements
system.cpu.dcache.tagsinuse 4094.896939 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 442048 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 1372.670239 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 778540000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4094.896939 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999731 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 418844799 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 187941335 # number of WriteReq hits
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-system.cpu.dcache.overall_hits 606786134 # number of overall hits
-system.cpu.dcache.ReadReq_misses 197326 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 244722 # number of WriteReq misses
-system.cpu.dcache.demand_misses 442048 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 442048 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 4043270000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 5872734000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 9916004000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 9916004000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 419042125 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 188186057 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 607228182 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 607228182 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000471 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.001300 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.000728 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.000728 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 22431.962140 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 22431.962140 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4094.896939 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999731 # Average percentage of cache occupancy
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+system.cpu.dcache.overall_misses::total 442048 # number of overall misses
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+system.cpu.dcache.overall_miss_latency::total 9916004000 # number of overall miss cycles
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756 # average WriteReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 396372 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 197326 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 244722 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 442048 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 442048 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3451292000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 5138568000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 8589860000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 8589860000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.000471 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.001300 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.000728 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.000728 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 396372 # number of writebacks
+system.cpu.dcache.writebacks::total 396372 # number of writebacks
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+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3451292000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3451292000 # number of ReadReq MSHR miss cycles
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+system.cpu.dcache.demand_mshr_miss_latency::total 8589860000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8589860000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 8589860000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000471 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.001300 # mshr miss rate for WriteReq accesses
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+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000728 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 71208 # number of replacements
system.cpu.l2cache.tagsinuse 18056.923092 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 86793 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 4.873826 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 1869.199731 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 16187.723361 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.057043 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.494010 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 166833 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 396372 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 186469 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 353302 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 353302 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 31215 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 58253 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 89468 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 89468 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1623180000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3029156000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 4652336000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 4652336000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 198048 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 396372 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 244722 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 442770 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 442770 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.157613 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.238037 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.202064 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.202064 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16187.723361 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 48.180025 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1821.019706 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.494010 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001470 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.055573 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.551054 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data 166833 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 166833 # number of ReadReq hits
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+system.cpu.l2cache.Writeback_hits::total 396372 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 186469 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 186469 # number of ReadExReq hits
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+system.cpu.l2cache.demand_miss_latency::cpu.data 4614792000 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.Writeback_accesses::writebacks 396372 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 396372 # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.ReadExReq_accesses::total 244722 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.overall_accesses::total 442770 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.154531 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.238037 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.200761 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.200761 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 58007 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 31215 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 58253 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 89468 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 89468 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1248600000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2330120000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 3578720000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 3578720000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.157613 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.238037 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.202064 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.202064 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 58007 # number of writebacks
+system.cpu.l2cache.writebacks::total 58007 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 722 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 30493 # number of ReadReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.data 88746 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 89468 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 722 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 88746 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 89468 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 28880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1219720000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1248600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2330120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2330120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 28880000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3549840000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 28880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3549840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 3578720000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.154531 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.238037 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200761 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:46:15
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 33080570000 # Number of ticks simulated
final_tick 33080570000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 45520 # Simulator instruction rate (inst/s)
-host_tick_rate 16502276 # Simulator tick rate (ticks/s)
-host_mem_usage 388968 # Number of bytes of host memory used
-host_seconds 2004.61 # Real time elapsed on the host
-sim_insts 91249885 # Number of instructions simulated
+host_inst_rate 183696 # Simulator instruction rate (inst/s)
+host_op_rate 185015 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 67072888 # Simulator tick rate (ticks/s)
+host_mem_usage 356156 # Number of bytes of host memory used
+host_seconds 493.20 # Real time elapsed on the host
+sim_insts 90599331 # Number of instructions simulated
+sim_ops 91249885 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 997440 # Number of bytes read from this memory
system.physmem.bytes_inst_read 44864 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2048 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.549573 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.621804 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 91262494 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 90611940 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 91262494 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 26696996 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 554844 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1392644 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 62124345 # Number of insts commited each cycle
-system.cpu.commit.count 91262494 # Number of instructions committed
+system.cpu.commit.committedInsts 90611940 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 27322621 # Number of memory references committed
system.cpu.commit.loads 22575872 # Number of loads committed
system.cpu.rob.rob_writes 239939856 # The number of ROB writes
system.cpu.timesIdled 1543 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 29796 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 91249885 # Number of Instructions Simulated
-system.cpu.committedInsts_total 91249885 # Number of Instructions Simulated
-system.cpu.cpi 0.725055 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.725055 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.379207 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.379207 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 90599331 # Number of Instructions Simulated
+system.cpu.committedOps 91249885 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 90599331 # Number of Instructions Simulated
+system.cpu.cpi 0.730261 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.730261 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.369374 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.369374 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 496902735 # number of integer regfile reads
system.cpu.int_regfile_writes 120936098 # number of integer regfile writes
system.cpu.fp_regfile_reads 197 # number of floating regfile reads
system.cpu.icache.sampled_refs 722 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 20420.790859 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.overall_misses 916 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 32376000 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency 35344.978166 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35344.978166 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35344.978166 # average overall miss latency
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-system.cpu.icache.ReadReq_mshr_miss_rate 0.000049 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086 # average ReadReq mshr miss latency
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-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 943456 # number of replacements
system.cpu.dcache.tagsinuse 3558.808733 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 947552 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 30.414448 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12353041000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_mshrs 23239503 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.WriteReq_mshr_miss_latency 1081063056 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 3334139556 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 3334139556 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.035782 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.009404 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.031615 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.031615 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2495.026727 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.366123 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 3518.683974 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 3518.683974 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 744 # number of replacements
system.cpu.l2cache.tagsinuse 9229.669691 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 15569 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 102.561115 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 392.792276 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 8836.877415 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.011987 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.269680 # Average percentage of cache occupancy
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-system.cpu.l2cache.Writeback_hits 942907 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 31267 # number of ReadExReq hits
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-system.cpu.l2cache.ReadReq_misses 1057 # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_accesses 902470 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 942907 # number of Writeback accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864 # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency 34304.071818 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 8836.877415 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 199.760007 # Average occupied blocks per requestor
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864 # average ReadExReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 32 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 10 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1047 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 14538 # number of ReadExReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses 15585 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 32560500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 451777500 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_miss_latency 484338000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.001160 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.317389 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.016435 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.016435 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 32 # number of writebacks
+system.cpu.l2cache.writebacks::total 32 # number of writebacks
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.970914 # mshr miss rate for demand accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:47:31
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:51:19
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 54240666000 # Number of ticks simulated
final_tick 54240666000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2777644 # Simulator instruction rate (inst/s)
-host_tick_rate 1651027932 # Simulator tick rate (ticks/s)
-host_mem_usage 342980 # Number of bytes of host memory used
-host_seconds 32.85 # Real time elapsed on the host
-sim_insts 91252969 # Number of instructions simulated
+host_inst_rate 3177444 # Simulator instruction rate (inst/s)
+host_op_rate 3200257 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1902228216 # Simulator tick rate (ticks/s)
+host_mem_usage 345536 # Number of bytes of host memory used
+host_seconds 28.51 # Real time elapsed on the host
+sim_insts 90602415 # Number of instructions simulated
+sim_ops 91252969 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 521339715 # Number of bytes read from this memory
system.physmem.bytes_inst_read 431323116 # Number of instructions bytes read from this memory
system.physmem.bytes_written 18908138 # Number of bytes written to this memory
system.cpu.numCycles 108481333 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 91252969 # Number of instructions executed
+system.cpu.committedInsts 90602415 # Number of instructions committed
+system.cpu.committedOps 91252969 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 96832 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:48:15
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:51:58
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 148086239000 # Number of ticks simulated
final_tick 148086239000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1300672 # Simulator instruction rate (inst/s)
-host_tick_rate 2111359212 # Simulator tick rate (ticks/s)
-host_mem_usage 351948 # Number of bytes of host memory used
-host_seconds 70.14 # Real time elapsed on the host
-sim_insts 91226321 # Number of instructions simulated
+host_inst_rate 1696896 # Simulator instruction rate (inst/s)
+host_op_rate 1709063 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2774293546 # Simulator tick rate (ticks/s)
+host_mem_usage 354444 # Number of bytes of host memory used
+host_seconds 53.38 # Real time elapsed on the host
+sim_insts 90576869 # Number of instructions simulated
+sim_ops 91226321 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 986112 # Number of bytes read from this memory
system.physmem.bytes_inst_read 36992 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2048 # Number of bytes written to this memory
system.cpu.numCycles 296172478 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 91226321 # Number of instructions executed
+system.cpu.committedInsts 90576869 # Number of instructions committed
+system.cpu.committedOps 91226321 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 72525682 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses
system.cpu.num_func_calls 96832 # number of times a function call or return occured
system.cpu.icache.sampled_refs 599 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 180016.996661 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 510.335448 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.249187 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 107830181 # number of ReadReq hits
-system.cpu.icache.demand_hits 107830181 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 107830181 # number of overall hits
-system.cpu.icache.ReadReq_misses 599 # number of ReadReq misses
-system.cpu.icache.demand_misses 599 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 599 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 32662000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 32662000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 32662000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 107830780 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 107830780 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 107830780 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000006 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000006 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000006 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54527.545910 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54527.545910 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54527.545910 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 510.335448 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.249187 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.249187 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 107830181 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 107830181 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 107830181 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 107830181 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 107830181 # number of overall hits
+system.cpu.icache.overall_hits::total 107830181 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses
+system.cpu.icache.overall_misses::total 599 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 32662000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 32662000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 32662000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 32662000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 32662000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 32662000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 107830780 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 107830780 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 107830780 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 107830780 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 107830780 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 107830780 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 599 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 599 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 599 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 30865000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 30865000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 30865000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000006 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000006 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000006 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 599 # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 30865000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 30865000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 30865000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 30865000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 30865000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 942702 # number of replacements
system.cpu.dcache.tagsinuse 3568.549501 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 946798 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 27.825751 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 54479156000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 3568.549501 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.871228 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 21649219 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 4688372 # number of WriteReq hits
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-system.cpu.dcache.StoreCondReq_hits 3887 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 26337591 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 26337591 # number of overall hits
-system.cpu.dcache.ReadReq_misses 900189 # number of ReadReq misses
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-system.cpu.dcache.ReadReq_miss_latency 12614490000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 1263542000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 13878032000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 13878032000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 22549408 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 4734981 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 3887 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 3887 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 27284389 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 27284389 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.039921 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.009844 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.034701 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.034701 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14657.859438 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14657.859438 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 3568.549501 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.871228 # Average percentage of cache occupancy
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+system.cpu.dcache.WriteReq_hits::total 4688372 # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total 3887 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 3887 # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data 26337591 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 26337591 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 900189 # number of ReadReq misses
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:20:13
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:49
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 122215830000 # Number of ticks simulated
final_tick 122215830000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3409932 # Simulator instruction rate (inst/s)
-host_tick_rate 1709135687 # Simulator tick rate (ticks/s)
-host_mem_usage 338176 # Number of bytes of host memory used
-host_seconds 71.51 # Real time elapsed on the host
-sim_insts 243835278 # Number of instructions simulated
+host_inst_rate 4048457 # Simulator instruction rate (inst/s)
+host_op_rate 4048623 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2029262264 # Simulator tick rate (ticks/s)
+host_mem_usage 335836 # Number of bytes of host memory used
+host_seconds 60.23 # Real time elapsed on the host
+sim_insts 243825163 # Number of instructions simulated
+sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1306360053 # Number of bytes read from this memory
system.physmem.bytes_inst_read 977686044 # Number of instructions bytes read from this memory
system.physmem.bytes_written 91606089 # Number of bytes written to this memory
system.cpu.numCycles 244431661 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.committedInsts 243825163 # Number of instructions committed
+system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:21:35
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:58:00
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 362430887000 # Number of ticks simulated
final_tick 362430887000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1587659 # Simulator instruction rate (inst/s)
-host_tick_rate 2359857170 # Simulator tick rate (ticks/s)
-host_mem_usage 346888 # Number of bytes of host memory used
-host_seconds 153.58 # Real time elapsed on the host
-sim_insts 243835278 # Number of instructions simulated
+host_inst_rate 1947938 # Simulator instruction rate (inst/s)
+host_op_rate 1948018 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2895487158 # Simulator tick rate (ticks/s)
+host_mem_usage 344700 # Number of bytes of host memory used
+host_seconds 125.17 # Real time elapsed on the host
+sim_insts 243825163 # Number of instructions simulated
+sim_ops 243835278 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1001472 # Number of bytes read from this memory
system.physmem.bytes_inst_read 56256 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2560 # Number of bytes written to this memory
system.cpu.numCycles 724861774 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 243835278 # Number of instructions executed
+system.cpu.committedInsts 243825163 # Number of instructions committed
+system.cpu.committedOps 243835278 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 194726506 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 11630 # Number of float alu accesses
system.cpu.num_func_calls 4252956 # number of times a function call or return occured
system.cpu.icache.sampled_refs 882 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 277120.895692 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 725.567632 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.354281 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 244420630 # number of ReadReq hits
-system.cpu.icache.demand_hits 244420630 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 244420630 # number of overall hits
-system.cpu.icache.ReadReq_misses 882 # number of ReadReq misses
-system.cpu.icache.demand_misses 882 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 882 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 49266000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 49266000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 49266000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 244421512 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 244421512 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 244421512 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55857.142857 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55857.142857 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55857.142857 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 725.567632 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.354281 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.354281 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 244420630 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 244420630 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 244420630 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 244420630 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 244420630 # number of overall hits
+system.cpu.icache.overall_hits::total 244420630 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 882 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 882 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 882 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 882 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 882 # number of overall misses
+system.cpu.icache.overall_misses::total 882 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 49266000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 49266000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 49266000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 49266000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 49266000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 49266000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 244421512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 244421512 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 244421512 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 244421512 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 244421512 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 244421512 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 882 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 882 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 882 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 46620000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 46620000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 46620000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 882 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 882 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 882 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 882 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 882 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 882 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 46620000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 46620000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 46620000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 46620000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 46620000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 46620000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 935475 # number of replacements
system.cpu.dcache.tagsinuse 3563.824259 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 939571 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 110.887522 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 134373316000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 3563.824259 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.870074 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 81327577 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 22855241 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits 3882 # number of SwapReq hits
-system.cpu.dcache.demand_hits 104182818 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 104182818 # number of overall hits
-system.cpu.dcache.ReadReq_misses 892857 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 46710 # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses 4 # number of SwapReq misses
-system.cpu.dcache.demand_misses 939567 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 939567 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 12508482000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 1265712000 # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency 98000 # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency 13774194000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 13774194000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 82220434 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 22901951 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses 3886 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 105122385 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 105122385 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.010859 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.002040 # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate 0.001029 # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate 0.008938 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.008938 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279 # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency 24500 # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14660.150899 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14660.150899 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 3563.824259 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.870074 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.870074 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 81327577 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 81327577 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 22855241 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 22855241 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 3882 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 3882 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 104182818 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 104182818 # number of demand (read+write) hits
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+system.cpu.dcache.overall_hits::total 104182818 # number of overall hits
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 35160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 590760000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 625920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 35160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 590760000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 625920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000226 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.311834 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996599 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015719 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
max_stack_size=67108864
output=cout
pid=100
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 9 2012 12:45:55
-gem5 started Feb 9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:13:01
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 70046988500 # Number of ticks simulated
final_tick 70046988500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 78701 # Simulator instruction rate (inst/s)
-host_tick_rate 19816485 # Simulator tick rate (ticks/s)
-host_mem_usage 388420 # Number of bytes of host memory used
-host_seconds 3534.78 # Real time elapsed on the host
-sim_insts 278192519 # Number of instructions simulated
+host_inst_rate 120922 # Simulator instruction rate (inst/s)
+host_op_rate 212925 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 53613076 # Simulator tick rate (ticks/s)
+host_mem_usage 355612 # Number of bytes of host memory used
+host_seconds 1306.53 # Real time elapsed on the host
+sim_insts 157988582 # Number of instructions simulated
+sim_ops 278192519 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 3895936 # Number of bytes read from this memory
system.physmem.bytes_inst_read 65216 # Number of instructions bytes read from this memory
system.physmem.bytes_written 892288 # Number of bytes written to this memory
system.cpu.iew.wb_rate 2.229177 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.730584 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 278192519 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 157988582 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 278192519 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 65103374 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 446 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1332005 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 130436298 # Number of insts commited each cycle
-system.cpu.commit.count 278192519 # Number of instructions committed
+system.cpu.commit.committedInsts 157988582 # Number of instructions committed
+system.cpu.commit.committedOps 278192519 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 122219139 # Number of memory references committed
system.cpu.commit.loads 90779388 # Number of loads committed
system.cpu.rob.rob_writes 695479183 # The number of ROB writes
system.cpu.timesIdled 23894 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 787486 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 278192519 # Number of Instructions Simulated
-system.cpu.committedInsts_total 278192519 # Number of Instructions Simulated
-system.cpu.cpi 0.503586 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.503586 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.985756 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.985756 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 157988582 # Number of Instructions Simulated
+system.cpu.committedOps 278192519 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 157988582 # Number of Instructions Simulated
+system.cpu.cpi 0.886735 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.886735 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.127733 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.127733 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 554395898 # number of integer regfile reads
system.cpu.int_regfile_writes 279799467 # number of integer regfile writes
system.cpu.fp_regfile_reads 352 # number of floating regfile reads
system.cpu.icache.sampled_refs 1024 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 27551.352539 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 822.534021 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.401628 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 28212585 # number of ReadReq hits
-system.cpu.icache.demand_hits 28212585 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 28212585 # number of overall hits
-system.cpu.icache.ReadReq_misses 1300 # number of ReadReq misses
-system.cpu.icache.demand_misses 1300 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 1300 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 46952500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 46952500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 46952500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 28213885 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 28213885 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 28213885 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000046 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000046 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000046 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36117.307692 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36117.307692 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36117.307692 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 822.534021 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.401628 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.401628 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 28212585 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 28212585 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 28212585 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 28212585 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 28212585 # number of overall hits
+system.cpu.icache.overall_hits::total 28212585 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1300 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1300 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1300 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1300 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1300 # number of overall misses
+system.cpu.icache.overall_misses::total 1300 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 46952500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 46952500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 46952500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 46952500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 46952500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 46952500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 28213885 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 28213885 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 28213885 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 28213885 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 28213885 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 28213885 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000046 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000046 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000046 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 275 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 275 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 275 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 1025 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 1025 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 1025 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 36071500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 36071500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 36071500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000036 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000036 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000036 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.707317 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35191.707317 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 275 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 275 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 275 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 275 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 275 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 275 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1025 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 1025 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 1025 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 1025 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 1025 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 1025 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 36071500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 36071500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 36071500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000036 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 2072906 # number of replacements
system.cpu.dcache.tagsinuse 4073.029614 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 2077002 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.308300 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 23588256000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4073.029614 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.994392 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 46135653 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 31353751 # number of WriteReq hits
-system.cpu.dcache.demand_hits 77489404 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 77489404 # number of overall hits
-system.cpu.dcache.ReadReq_misses 2289012 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 86000 # number of WriteReq misses
-system.cpu.dcache.demand_misses 2375012 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 2375012 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 13766771000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 1501245288 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 15268016288 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 15268016288 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 48424665 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 31439751 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 79864416 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 79864416 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.047270 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.002735 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.029738 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.029738 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 6014.285203 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 17456.340558 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 6428.605956 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 6428.605956 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4073.029614 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.994392 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.994392 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 46135653 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 46135653 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 31353751 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 31353751 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 77489404 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 77489404 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 77489404 # number of overall hits
+system.cpu.dcache.overall_hits::total 77489404 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 2289012 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 2289012 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 86000 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 86000 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 2375012 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 2375012 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 2375012 # number of overall misses
+system.cpu.dcache.overall_misses::total 2375012 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 13766771000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 13766771000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 1501245288 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 1501245288 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 15268016288 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 31643000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 1856136500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 1887779500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.015211 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.358943 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995117 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.028818 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:52:52
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:18:06
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 168950072000 # Number of ticks simulated
final_tick 168950072000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2042288 # Simulator instruction rate (inst/s)
-host_tick_rate 1240309006 # Simulator tick rate (ticks/s)
-host_mem_usage 339312 # Number of bytes of host memory used
-host_seconds 136.22 # Real time elapsed on the host
-sim_insts 278192520 # Number of instructions simulated
+host_inst_rate 1605694 # Simulator instruction rate (inst/s)
+host_op_rate 2827368 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1717098424 # Simulator tick rate (ticks/s)
+host_mem_usage 344660 # Number of bytes of host memory used
+host_seconds 98.39 # Real time elapsed on the host
+sim_insts 157988583 # Number of instructions simulated
+sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2458815679 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1741569664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 243173115 # Number of bytes written to this memory
system.cpu.numCycles 337900145 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 278192520 # Number of instructions executed
+system.cpu.committedInsts 157988583 # Number of instructions committed
+system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:55:19
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:19:55
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 370010840000 # Number of ticks simulated
final_tick 370010840000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1163147 # Simulator instruction rate (inst/s)
-host_tick_rate 1547047043 # Simulator tick rate (ticks/s)
-host_mem_usage 348152 # Number of bytes of host memory used
-host_seconds 239.17 # Real time elapsed on the host
-sim_insts 278192520 # Number of instructions simulated
+host_inst_rate 912216 # Simulator instruction rate (inst/s)
+host_op_rate 1606265 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2136418129 # Simulator tick rate (ticks/s)
+host_mem_usage 353708 # Number of bytes of host memory used
+host_seconds 173.19 # Real time elapsed on the host
+sim_insts 157988583 # Number of instructions simulated
+sim_ops 278192520 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 4900800 # Number of bytes read from this memory
system.physmem.bytes_inst_read 51712 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1885440 # Number of bytes written to this memory
system.cpu.numCycles 740021680 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 278192520 # Number of instructions executed
+system.cpu.committedInsts 157988583 # Number of instructions committed
+system.cpu.committedOps 278192520 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 278186228 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 40 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.icache.sampled_refs 808 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 269425.001238 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 666.191948 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.325289 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 217695401 # number of ReadReq hits
-system.cpu.icache.demand_hits 217695401 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 217695401 # number of overall hits
-system.cpu.icache.ReadReq_misses 808 # number of ReadReq misses
-system.cpu.icache.demand_misses 808 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 808 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 45248000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 45248000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 45248000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 217696209 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 217696209 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 217696209 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000004 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000004 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000004 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 666.191948 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.325289 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.325289 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 217695401 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 217695401 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 217695401 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 217695401 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 217695401 # number of overall hits
+system.cpu.icache.overall_hits::total 217695401 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 808 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 808 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 808 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 808 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 808 # number of overall misses
+system.cpu.icache.overall_misses::total 808 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 45248000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 45248000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 45248000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 45248000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 45248000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 45248000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 217696209 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 217696209 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 217696209 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 217696209 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 217696209 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 217696209 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000004 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000004 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000004 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 808 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 808 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 808 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 42824000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 42824000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 42824000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 808 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 808 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 808 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 42824000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 42824000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 42824000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 42824000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 42824000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 42824000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
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+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 808 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33309 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 34117 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42458 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 42458 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 808 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 75767 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 76575 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 808 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 75767 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 76575 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 32320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1332360000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1364680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1698320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1698320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 32320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3030680000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 3063000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 32320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3030680000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 3063000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.016988 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.400136 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.036659 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:53:02
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 274128411000 # Number of ticks simulated
final_tick 274128411000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67477 # Simulator instruction rate (inst/s)
-host_tick_rate 32262353 # Simulator tick rate (ticks/s)
-host_mem_usage 260864 # Number of bytes of host memory used
-host_seconds 8496.85 # Real time elapsed on the host
-sim_insts 573341187 # Number of instructions simulated
+host_inst_rate 133293 # Simulator instruction rate (inst/s)
+host_op_rate 150155 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 71792865 # Simulator tick rate (ticks/s)
+host_mem_usage 228092 # Number of bytes of host memory used
+host_seconds 3818.32 # Real time elapsed on the host
+sim_insts 508954626 # Number of instructions simulated
+sim_ops 573341187 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 15240192 # Number of bytes read from this memory
system.physmem.bytes_inst_read 229568 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10959680 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.265299 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.595401 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 574685071 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 510298510 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 574685071 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 312438031 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3878199 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 20478103 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 495250570 # Number of insts commited each cycle
-system.cpu.commit.count 574685071 # Number of instructions committed
+system.cpu.commit.committedInsts 510298510 # Number of instructions committed
+system.cpu.commit.committedOps 574685071 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 184376791 # Number of memory references committed
system.cpu.commit.loads 126772935 # Number of loads committed
system.cpu.rob.rob_writes 1823647630 # The number of ROB writes
system.cpu.timesIdled 94158 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 3785113 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 573341187 # Number of Instructions Simulated
-system.cpu.committedInsts_total 573341187 # Number of Instructions Simulated
-system.cpu.cpi 0.956249 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.956249 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.045753 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.045753 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 508954626 # Number of Instructions Simulated
+system.cpu.committedOps 573341187 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 508954626 # Number of Instructions Simulated
+system.cpu.cpi 1.077221 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.077221 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.928314 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.928314 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3289345591 # number of integer regfile reads
system.cpu.int_regfile_writes 815117578 # number of integer regfile writes
system.cpu.fp_regfile_reads 16 # number of floating regfile reads
system.cpu.icache.sampled_refs 14723 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 9617.789581 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1062.179544 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.518642 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 141602717 # number of ReadReq hits
-system.cpu.icache.demand_hits 141602717 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 141602717 # number of overall hits
-system.cpu.icache.ReadReq_misses 16509 # number of ReadReq misses
-system.cpu.icache.demand_misses 16509 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 16509 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 235489500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 235489500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 235489500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 141619226 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 141619226 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 141619226 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000117 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000117 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000117 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 14264.310376 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 14264.310376 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 14264.310376 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1062.179544 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.518642 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.518642 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 141602717 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 141602717 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 141602717 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 141602717 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 141602717 # number of overall hits
+system.cpu.icache.overall_hits::total 141602717 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 16509 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 16509 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 16509 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 16509 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 16509 # number of overall misses
+system.cpu.icache.overall_misses::total 16509 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 235489500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 235489500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 235489500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 235489500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 235489500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 235489500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 141619226 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 141619226 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 141619226 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 141619226 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 141619226 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 141619226 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000117 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000117 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000117 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 1 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 1646 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 1646 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 1646 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 14863 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 14863 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 14863 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 154537000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 154537000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 154537000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000105 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000105 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000105 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks 1 # number of writebacks
+system.cpu.icache.writebacks::total 1 # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1646 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1646 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1646 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1646 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1646 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1646 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 14863 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 14863 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 14863 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 14863 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 14863 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 14863 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 154537000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 154537000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 154537000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 154537000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 154537000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 154537000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000105 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1212291 # number of replacements
system.cpu.dcache.tagsinuse 4058.220860 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1216387 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 167.546345 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 5623769000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4058.220860 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.990777 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 146308743 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 52772298 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 2488014 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 2231920 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 199081041 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 199081041 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1241922 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 1467008 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 55 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 2708930 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 2708930 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 14257023500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 24962643993 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 523000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 39219667493 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 39219667493 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 147550665 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 54239306 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 2488069 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 2231920 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 201789971 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 201789971 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.008417 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.027047 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.000022 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.013425 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.013425 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898 # average ReadReq miss latency
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-system.cpu.dcache.overall_avg_miss_latency 14477.918401 # average overall miss latency
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system.cpu.l2cache.tagsinuse 21063.326998 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 239342 # Sample count of references to valid blocks.
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-system.cpu.l2cache.demand_mshr_hits 22 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 22 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 129707 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 35 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 108423 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 238130 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 238130 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4027357500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1085000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3362010000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 7389367500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 7389367500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.145695 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.267176 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.318107 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.193428 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.193428 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.654221 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.273152 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.813001 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 171245 # number of writebacks
+system.cpu.l2cache.writebacks::total 171245 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 3 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 19 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 3 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 19 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 3 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 19 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 22 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3587 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 126120 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 129707 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 35 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 35 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 108423 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 108423 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3587 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 234543 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 238130 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3587 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 234543 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 238130 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 111526500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3915831000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4027357500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 1085000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 1085000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3362010000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3362010000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 111526500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7277841000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 7389367500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 111526500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7277841000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 7389367500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.144048 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.267176 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.318107 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.243616 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.192821 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:54:41
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:54:26
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 290498972000 # Number of ticks simulated
final_tick 290498972000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3123764 # Simulator instruction rate (inst/s)
-host_tick_rate 1589318228 # Simulator tick rate (ticks/s)
-host_mem_usage 213568 # Number of bytes of host memory used
-host_seconds 182.78 # Real time elapsed on the host
-sim_insts 570968176 # Number of instructions simulated
+host_inst_rate 2958479 # Simulator instruction rate (inst/s)
+host_op_rate 3334501 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1696537892 # Simulator tick rate (ticks/s)
+host_mem_usage 216124 # Number of bytes of host memory used
+host_seconds 171.23 # Real time elapsed on the host
+sim_insts 506581615 # Number of instructions simulated
+sim_ops 570968176 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2489298238 # Number of bytes read from this memory
system.physmem.bytes_inst_read 2066445536 # Number of instructions bytes read from this memory
system.physmem.bytes_written 216067624 # Number of bytes written to this memory
system.cpu.numCycles 580997945 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 570968176 # Number of instructions executed
+system.cpu.committedInsts 506581615 # Number of instructions committed
+system.cpu.committedOps 570968176 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:54:55
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:54:39
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 722234364000 # Number of ticks simulated
final_tick 722234364000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1518630 # Simulator instruction rate (inst/s)
-host_tick_rate 1927485562 # Simulator tick rate (ticks/s)
-host_mem_usage 222536 # Number of bytes of host memory used
-host_seconds 374.70 # Real time elapsed on the host
-sim_insts 569034848 # Number of instructions simulated
+host_inst_rate 1769028 # Simulator instruction rate (inst/s)
+host_op_rate 1993395 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2530070907 # Simulator tick rate (ticks/s)
+host_mem_usage 225284 # Number of bytes of host memory used
+host_seconds 285.46 # Real time elapsed on the host
+sim_insts 504986861 # Number of instructions simulated
+sim_ops 569034848 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 14797056 # Number of bytes read from this memory
system.physmem.bytes_inst_read 188608 # Number of instructions bytes read from this memory
system.physmem.bytes_written 11027328 # Number of bytes written to this memory
system.cpu.numCycles 1444468728 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 569034848 # Number of instructions executed
+system.cpu.committedInsts 504986861 # Number of instructions committed
+system.cpu.committedOps 569034848 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 470727703 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 15725605 # number of times a function call or return occured
system.cpu.icache.sampled_refs 11521 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 44839.845847 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 984.426148 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.480677 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 516599864 # number of ReadReq hits
-system.cpu.icache.demand_hits 516599864 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 516599864 # number of overall hits
-system.cpu.icache.ReadReq_misses 11521 # number of ReadReq misses
-system.cpu.icache.demand_misses 11521 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 11521 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 285068000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 285068000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 285068000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 516611385 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 516611385 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 516611385 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000022 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000022 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000022 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 24743.338252 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 24743.338252 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 24743.338252 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 984.426148 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.480677 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.480677 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 516599864 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 516599864 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 516599864 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 516599864 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 516599864 # number of overall hits
+system.cpu.icache.overall_hits::total 516599864 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 11521 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 11521 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 11521 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 11521 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 11521 # number of overall misses
+system.cpu.icache.overall_misses::total 11521 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 285068000 # number of ReadReq miss cycles
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+system.cpu.l2cache.demand_misses::total 231204 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2947 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 228257 # number of overall misses
+system.cpu.l2cache.overall_misses::total 231204 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 153244000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5627752000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 5780996000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6241612000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6241612000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 153244000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 11869364000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 12022608000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 153244000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 11869364000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 12022608000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 11521 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 782658 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 794179 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1025440 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1025440 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 356260 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 356260 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 11521 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1138918 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1150439 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 11521 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1138918 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1150439 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.255794 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.138280 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.336920 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.255794 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.200416 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.255794 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.200416 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 172302 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 111173 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 120031 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 231204 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 231204 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 4446920000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4801240000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 9248160000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 9248160000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.139985 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.336920 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.200970 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.200970 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 172302 # number of writebacks
+system.cpu.l2cache.writebacks::total 172302 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2947 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 108226 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 111173 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 120031 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 120031 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2947 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 228257 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 231204 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2947 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 228257 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 231204 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 117880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4329040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 4446920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4801240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4801240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 117880000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9130280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 9248160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 117880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9130280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 9248160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.138280 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.336920 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.255794 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.200416 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
max_stack_size=67108864
output=cout
pid=100
-Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 9 2012 12:45:55
-gem5 started Feb 9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:22:59
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 488026375000 # Number of ticks simulated
final_tick 488026375000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 87795 # Simulator instruction rate (inst/s)
-host_tick_rate 28022613 # Simulator tick rate (ticks/s)
-host_mem_usage 289796 # Number of bytes of host memory used
-host_seconds 17415.45 # Real time elapsed on the host
-sim_insts 1528988756 # Number of instructions simulated
+host_inst_rate 101458 # Simulator instruction rate (inst/s)
+host_op_rate 187607 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 59880945 # Simulator tick rate (ticks/s)
+host_mem_usage 257144 # Number of bytes of host memory used
+host_seconds 8149.94 # Real time elapsed on the host
+sim_insts 826877144 # Number of instructions simulated
+sim_ops 1528988756 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 37539712 # Number of bytes read from this memory
system.physmem.bytes_inst_read 347136 # Number of instructions bytes read from this memory
system.physmem.bytes_written 26338560 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.917211 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.675773 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1528988756 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 826877144 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1528988756 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 745779287 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 553 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 16577287 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 856525585 # Number of insts commited each cycle
-system.cpu.commit.count 1528988756 # Number of instructions committed
+system.cpu.commit.committedInsts 826877144 # Number of instructions committed
+system.cpu.commit.committedOps 1528988756 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 533262345 # Number of memory references committed
system.cpu.commit.loads 384102160 # Number of loads committed
system.cpu.rob.rob_writes 4651204201 # The number of ROB writes
system.cpu.timesIdled 418807 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 18030123 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1528988756 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1528988756 # Number of Instructions Simulated
-system.cpu.cpi 0.638365 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.638365 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.566502 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.566502 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 826877144 # Number of Instructions Simulated
+system.cpu.committedOps 1528988756 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 826877144 # Number of Instructions Simulated
+system.cpu.cpi 1.180408 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.180408 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.847164 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.847164 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 3175693593 # number of integer regfile reads
system.cpu.int_regfile_writes 1742205758 # number of integer regfile writes
system.cpu.fp_regfile_reads 120 # number of floating regfile reads
system.cpu.icache.sampled_refs 11601 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 16693.315749 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 973.820201 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.475498 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 193665655 # number of ReadReq hits
-system.cpu.icache.demand_hits 193665655 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 193665655 # number of overall hits
-system.cpu.icache.ReadReq_misses 234749 # number of ReadReq misses
-system.cpu.icache.demand_misses 234749 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 234749 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 1699920500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 1699920500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 1699920500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 193900404 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 193900404 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 193900404 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.001211 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.001211 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.001211 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 7241.438728 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 7241.438728 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 7241.438728 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 973.820201 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.475498 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.475498 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 193665655 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 193665655 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 193665655 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 193665655 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 193665655 # number of overall hits
+system.cpu.icache.overall_hits::total 193665655 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 234749 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 234749 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 234749 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 234749 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 234749 # number of overall misses
+system.cpu.icache.overall_misses::total 234749 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 1699920500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 1699920500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 1699920500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 1699920500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 1699920500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 1699920500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 193900404 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 193900404 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 193900404 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 193900404 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 193900404 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 193900404 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001211 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.001211 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.001211 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 7241.438728 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 7241.438728 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 4 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 2040 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 2040 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 2040 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 232709 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8467808500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 8467808500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 185788500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 19876745000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 20062533500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 185788500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 19876745000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 20062533500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 11556 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1762180 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1773736 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 2229936 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 2229936 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 221060 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 221060 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 771154 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 771154 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 11556 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2533334 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2544890 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 11556 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2533334 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2544890 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.469367 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.189556 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.994169 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.320461 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.469367 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.229404 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.469367 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.229404 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.042035 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34155.220159 # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 43.909342 # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34265.284775 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.042035 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34202.022861 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 411540 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 339456 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 219771 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 247125 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 586581 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 586581 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 10530013500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 6813351000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 7661828500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 18191842000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 18191842000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191379 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.994169 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.320461 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.230494 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.230494 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 411540 # number of writebacks
+system.cpu.l2cache.writebacks::total 411540 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5424 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 334032 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 339456 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 219771 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 219771 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 247125 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 247125 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 5424 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 581157 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 586581 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 5424 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 581157 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 586581 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 168319500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 10361694000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10530013500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 6813351000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 6813351000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7661828500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7661828500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 168319500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18023522500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18191842000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 168319500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18023522500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18191842000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.189556 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.994169 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.320461 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.469367 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229404 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31032.356195 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.063946 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31002.047586 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31003.858371 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31032.356195 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.172860 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:59:28
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:26:26
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 885229360000 # Number of ticks simulated
final_tick 885229360000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2258239 # Simulator instruction rate (inst/s)
-host_tick_rate 1307438877 # Simulator tick rate (ticks/s)
-host_mem_usage 208528 # Number of bytes of host memory used
-host_seconds 677.07 # Real time elapsed on the host
-sim_insts 1528988757 # Number of instructions simulated
+host_inst_rate 1663979 # Simulator instruction rate (inst/s)
+host_op_rate 3076883 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1781404357 # Simulator tick rate (ticks/s)
+host_mem_usage 214024 # Number of bytes of host memory used
+host_seconds 496.93 # Real time elapsed on the host
+sim_insts 826877145 # Number of instructions simulated
+sim_ops 1528988757 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 10832432532 # Number of bytes read from this memory
system.physmem.bytes_inst_read 8546776872 # Number of instructions bytes read from this memory
system.physmem.bytes_written 991849460 # Number of bytes written to this memory
system.cpu.numCycles 1770458721 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1528988757 # Number of instructions executed
+system.cpu.committedInsts 826877145 # Number of instructions committed
+system.cpu.committedOps 1528988757 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1528317615 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:10:56
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:34:54
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 1658729604000 # Number of ticks simulated
final_tick 1658729604000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1326745 # Simulator instruction rate (inst/s)
-host_tick_rate 1439324936 # Simulator tick rate (ticks/s)
-host_mem_usage 217512 # Number of bytes of host memory used
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-system.cpu.l2cache.overall_miss_latency 30139674000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 1730228 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 2223170 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 791044 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 2521272 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 2521272 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.191637 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.313551 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.229888 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.229888 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000.010352 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000.010352 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 13679.064710 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 30.006309 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 7519.122292 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.417452 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.000916 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.229465 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.647833 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 493 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 1398159 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1398652 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 2223170 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 2223170 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 543011 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 543011 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 493 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 1941170 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1941663 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 493 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 1941170 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1941663 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2321 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 329255 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 331576 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 248033 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 248033 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2321 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 577288 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 579609 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2321 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 577288 # number of overall misses
+system.cpu.l2cache.overall_misses::total 579609 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 120692000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 17121260000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 17241952000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 12897722000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 12897722000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 120692000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 30018982000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 30139674000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 120692000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 30018982000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 30139674000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 2814 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1727414 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1730228 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 2223170 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 2223170 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 791044 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 791044 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 2814 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 2518458 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 2521272 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 2814 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 2518458 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 2521272 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.824805 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.190606 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.313551 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.824805 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.229223 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.824805 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.229223 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 411709 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 331576 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 248033 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 579609 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 579609 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13263040000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 9921320000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 23184360000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 23184360000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.191637 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.313551 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.229888 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.229888 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 411709 # number of writebacks
+system.cpu.l2cache.writebacks::total 411709 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2321 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 329255 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 331576 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 248033 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 248033 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2321 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 577288 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 579609 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2321 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 577288 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 579609 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 92840000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13170200000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13263040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9921320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9921320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 92840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23091520000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 23184360000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 92840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23091520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 23184360000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.190606 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.313551 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.824805 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229223 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:43
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 139995113500 # Number of ticks simulated
final_tick 139995113500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 118986 # Simulator instruction rate (inst/s)
-host_tick_rate 41783300 # Simulator tick rate (ticks/s)
-host_mem_usage 214012 # Number of bytes of host memory used
-host_seconds 3350.50 # Real time elapsed on the host
+host_inst_rate 154307 # Simulator instruction rate (inst/s)
+host_op_rate 154307 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54186341 # Simulator tick rate (ticks/s)
+host_mem_usage 215920 # Number of bytes of host memory used
+host_seconds 2583.59 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
+sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 469184 # Number of bytes read from this memory
system.physmem.bytes_inst_read 214784 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
system.cpu.comInts 112239074 # Number of Integer instructions committed
system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
-system.cpu.committedInsts 398664595 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 398664595 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.702320 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.702320 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 3897 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12536.687708 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1829.847469 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.893480 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 48855472 # number of ReadReq hits
-system.cpu.icache.demand_hits 48855472 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 48855472 # number of overall hits
-system.cpu.icache.ReadReq_misses 4376 # number of ReadReq misses
-system.cpu.icache.demand_misses 4376 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 4376 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 214318500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 214318500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 214318500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 48859848 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 48859848 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 48859848 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000090 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000090 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000090 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 48975.891225 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 48975.891225 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 48975.891225 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1829.847469 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.893480 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.893480 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 48855472 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 48855472 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 48855472 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 48855472 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 48855472 # number of overall hits
+system.cpu.icache.overall_hits::total 48855472 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4376 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4376 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4376 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4376 # number of demand (read+write) misses
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+system.cpu.l2cache.ReadReq_misses::total 4186 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 3145 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 3145 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 3356 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 3975 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 7331 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 3356 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 3975 # number of overall misses
+system.cpu.l2cache.overall_misses::total 7331 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 175581500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 43628000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 219209500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 164966000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 164966000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 175581500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 208594000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 384175500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 175581500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 208594000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 384175500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 3897 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 947 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 4844 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 3205 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 3205 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 3897 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8049 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 3897 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8049 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.861175 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876452 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981279 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.861175 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.861175 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 4186 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 3145 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 7331 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 7331 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 168226500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 126764000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 294990500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 294990500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.864162 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981279 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.910796 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.910796 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3356 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 830 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4186 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3145 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3145 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3356 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7331 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3356 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7331 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 134709500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33517000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 168226500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 126764000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 126764000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 134709500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 160281000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 294990500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 134709500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 160281000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 294990500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876452 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981279 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.861175 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:45
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 89480174500 # Number of ticks simulated
final_tick 89480174500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 190161 # Simulator instruction rate (inst/s)
-host_tick_rate 45305657 # Simulator tick rate (ticks/s)
-host_mem_usage 214676 # Number of bytes of host memory used
-host_seconds 1975.03 # Real time elapsed on the host
+host_inst_rate 246728 # Simulator instruction rate (inst/s)
+host_op_rate 246728 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 58782597 # Simulator tick rate (ticks/s)
+host_mem_usage 216860 # Number of bytes of host memory used
+host_seconds 1522.22 # Real time elapsed on the host
sim_insts 375574794 # Number of instructions simulated
+sim_ops 375574794 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 475840 # Number of bytes read from this memory
system.physmem.bytes_inst_read 219968 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.713332 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 398664569 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 398664569 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 60016815 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 215 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3547729 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 169731918 # Number of insts commited each cycle
-system.cpu.commit.count 398664569 # Number of instructions committed
+system.cpu.commit.committedInsts 398664569 # Number of instructions committed
+system.cpu.commit.committedOps 398664569 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 168275214 # Number of memory references committed
system.cpu.commit.loads 94754486 # Number of loads committed
system.cpu.timesIdled 2712 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 121803 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 375574794 # Number of Instructions Simulated
+system.cpu.committedOps 375574794 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 375574794 # Number of Instructions Simulated
system.cpu.cpi 0.476497 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.476497 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 4037 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14342.037156 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1834.326922 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.895667 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 57898804 # number of ReadReq hits
-system.cpu.icache.demand_hits 57898804 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 57898804 # number of overall hits
-system.cpu.icache.ReadReq_misses 5282 # number of ReadReq misses
-system.cpu.icache.demand_misses 5282 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 5282 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 167914000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 167914000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 167914000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 57904086 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 57904086 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 57904086 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000091 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000091 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000091 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 31789.852329 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 31789.852329 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 31789.852329 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1834.326922 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.895667 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.895667 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 57898804 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 57898804 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 57898804 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 57898804 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 57898804 # number of overall hits
+system.cpu.icache.overall_hits::total 57898804 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 5282 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 5282 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 5282 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 5282 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 5282 # number of overall misses
+system.cpu.icache.overall_misses::total 5282 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 167914000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 167914000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 167914000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 167914000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 167914000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 167914000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 57904086 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 57904086 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 57904086 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 57904086 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 57904086 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 57904086 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000091 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000091 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000091 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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+system.cpu.l2cache.demand_miss_latency::cpu.data 138404000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 256555500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 118151500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 138404000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 256555500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 4037 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 998 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 5035 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 671 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 671 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 3195 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 3195 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 4037 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4193 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 8230 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 4037 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4193 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 8230 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.851375 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.869739 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.979656 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.851375 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.953494 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.851375 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.953494 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34376.345650 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34576.036866 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34630.031949 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34376.345650 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34618.309155 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 4305 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 3130 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 7435 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 7435 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 134314000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 98534000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 232848000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 232848000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.855015 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.979656 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.903402 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.903402 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3437 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 868 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4305 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3130 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3130 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3437 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3998 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7435 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3437 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3998 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7435 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 107040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27274000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 134314000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 98534000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 98534000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 107040000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 125808000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 232848000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 107040000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 125808000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 232848000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.869739 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.979656 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.851375 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.953494 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:11:11
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 199332411500 # Number of ticks simulated
final_tick 199332411500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3927016 # Simulator instruction rate (inst/s)
-host_tick_rate 1963508553 # Simulator tick rate (ticks/s)
-host_mem_usage 204908 # Number of bytes of host memory used
-host_seconds 101.52 # Real time elapsed on the host
+host_inst_rate 4966970 # Simulator instruction rate (inst/s)
+host_op_rate 4966969 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2483485434 # Simulator tick rate (ticks/s)
+host_mem_usage 206672 # Number of bytes of host memory used
+host_seconds 80.26 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
+sim_ops 398664595 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 2257107875 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1594658604 # Number of instructions bytes read from this memory
system.physmem.bytes_written 492356798 # Number of bytes written to this memory
system.cpu.numCycles 398664824 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 398664595 # Number of instructions executed
+system.cpu.committedInsts 398664595 # Number of instructions committed
+system.cpu.committedOps 398664595 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365907 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:03
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 567343170000 # Number of ticks simulated
final_tick 567343170000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1814376 # Simulator instruction rate (inst/s)
-host_tick_rate 2582053806 # Simulator tick rate (ticks/s)
-host_mem_usage 213620 # Number of bytes of host memory used
-host_seconds 219.73 # Real time elapsed on the host
+host_inst_rate 2193403 # Simulator instruction rate (inst/s)
+host_op_rate 2193403 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3121451222 # Simulator tick rate (ticks/s)
+host_mem_usage 215564 # Number of bytes of host memory used
+host_seconds 181.76 # Real time elapsed on the host
sim_insts 398664609 # Number of instructions simulated
+sim_ops 398664609 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 459520 # Number of bytes read from this memory
system.physmem.bytes_inst_read 205120 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 1134686340 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 398664609 # Number of instructions executed
+system.cpu.committedInsts 398664609 # Number of instructions committed
+system.cpu.committedOps 398664609 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 316365921 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 155295119 # Number of float alu accesses
system.cpu.num_func_calls 16015498 # number of times a function call or return occured
system.cpu.icache.sampled_refs 3673 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 108538.250204 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1795.131074 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.876529 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 398660993 # number of ReadReq hits
-system.cpu.icache.demand_hits 398660993 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 398660993 # number of overall hits
-system.cpu.icache.ReadReq_misses 3673 # number of ReadReq misses
-system.cpu.icache.demand_misses 3673 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 3673 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 186032000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 186032000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 186032000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 398664666 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 398664666 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 398664666 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 50648.516199 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 50648.516199 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 50648.516199 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1795.131074 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.876529 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.876529 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 398660993 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 398660993 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 398660993 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 398660993 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 398660993 # number of overall hits
+system.cpu.icache.overall_hits::total 398660993 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 3673 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 3673 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 3673 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 3673 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 3673 # number of overall misses
+system.cpu.icache.overall_misses::total 3673 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 186032000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 186032000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 186032000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 186032000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 186032000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 186032000 # number of overall miss cycles
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+system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 3202 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 3673 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4152 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 7825 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 3673 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4152 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 7825 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.872584 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.876842 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.981262 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.872584 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.957370 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.872584 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.957370 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 4038 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 3142 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 161520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 125680000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 287200000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 287200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.873459 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.981262 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.917572 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.917572 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3205 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 833 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4038 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 3142 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 3142 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3205 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 3975 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7180 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3205 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 3975 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7180 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 128200000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 33320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 161520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 125680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 125680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 128200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 159000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 287200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 128200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 159000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 287200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876842 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.981262 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.872584 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.957370 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:57:28
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 104492506500 # Number of ticks simulated
final_tick 104492506500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80425 # Simulator instruction rate (inst/s)
-host_tick_rate 24075162 # Simulator tick rate (ticks/s)
-host_mem_usage 264476 # Number of bytes of host memory used
-host_seconds 4340.26 # Real time elapsed on the host
-sim_insts 349066034 # Number of instructions simulated
+host_inst_rate 158423 # Simulator instruction rate (inst/s)
+host_op_rate 202536 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 60628822 # Simulator tick rate (ticks/s)
+host_mem_usage 231676 # Number of bytes of host memory used
+host_seconds 1723.48 # Real time elapsed on the host
+sim_insts 273038258 # Number of instructions simulated
+sim_ops 349066034 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 464000 # Number of bytes read from this memory
system.physmem.bytes_inst_read 192512 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.769576 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.508145 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 349066646 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 273038870 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 349066646 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 49103053 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 3555641 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 3227876 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 201258644 # Number of insts commited each cycle
-system.cpu.commit.count 349066646 # Number of instructions committed
+system.cpu.commit.committedInsts 273038870 # Number of instructions committed
+system.cpu.commit.committedOps 349066646 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 177024831 # Number of memory references committed
system.cpu.commit.loads 94649000 # Number of loads committed
system.cpu.rob.rob_writes 803956224 # The number of ROB writes
system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 112680 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 349066034 # Number of Instructions Simulated
-system.cpu.committedInsts_total 349066034 # Number of Instructions Simulated
-system.cpu.cpi 0.598698 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.598698 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.670292 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.670292 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 273038258 # Number of Instructions Simulated
+system.cpu.committedOps 349066034 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 273038258 # Number of Instructions Simulated
+system.cpu.cpi 0.765406 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.765406 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.306497 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.306497 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1781918480 # number of integer regfile reads
system.cpu.int_regfile_writes 235832393 # number of integer regfile writes
system.cpu.fp_regfile_reads 188783884 # number of floating regfile reads
system.cpu.icache.sampled_refs 15988 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2578.238179 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1842.733120 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.899772 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 41220872 # number of ReadReq hits
-system.cpu.icache.demand_hits 41220872 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 41220872 # number of overall hits
-system.cpu.icache.ReadReq_misses 16648 # number of ReadReq misses
-system.cpu.icache.demand_misses 16648 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 16648 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 201025000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 201025000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 201025000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 41237520 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 41237520 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 41237520 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000404 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000404 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000404 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 12075.024027 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 12075.024027 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 12075.024027 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1842.733120 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.899772 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.899772 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 41220872 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 41220872 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 41220872 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 41220872 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 41220872 # number of overall hits
+system.cpu.icache.overall_hits::total 41220872 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 16648 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 16648 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 16648 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 16648 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 16648 # number of overall misses
+system.cpu.icache.overall_misses::total 16648 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 201025000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 201025000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 201025000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 201025000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 201025000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 201025000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 41237520 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 41237520 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 41237520 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 41237520 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 41237520 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 41237520 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000404 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000404 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000404 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12075.024027 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 637 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 637 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 637 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 16011 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 16011 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 16011 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 135953500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 135953500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 135953500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000388 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000388 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000388 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 8491.256011 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 8491.256011 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 637 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 637 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 637 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 637 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 637 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 637 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 16011 # number of ReadReq MSHR misses
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+system.cpu.l2cache.ReadReq_accesses::cpu.inst 15988 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1749 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 17737 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 1034 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 1034 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 23 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 23 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2845 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2845 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 15988 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4594 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 20582 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 15988 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4594 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 20582 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.188767 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.835334 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 1 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.993322 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.188767 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.933174 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.188767 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.933174 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34258.449304 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34419.917864 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.114650 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34258.449304 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34456.962911 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 55 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 55 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 55 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 4424 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 23 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 2826 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 7250 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 7250 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 137822500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 713000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 88418000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 226240500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 226240500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.249422 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.993322 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.352250 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.352250 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.367993 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31287.331918 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.586207 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 45 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 45 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 45 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 55 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3008 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1416 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4424 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 23 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 23 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2826 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 2826 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3008 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4242 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 7250 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3008 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4242 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 7250 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 93473500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 44349000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 137822500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 713000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 713000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 88418000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 88418000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 93473500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 132767000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 226240500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 93473500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 132767000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 226240500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.809605 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.993322 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.188141 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.923378 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.966755 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31319.915254 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31287.331918 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.966755 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.208392 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:01:21
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:59:35
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 212344048000 # Number of ticks simulated
final_tick 212344048000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2434260 # Simulator instruction rate (inst/s)
-host_tick_rate 1480812932 # Simulator tick rate (ticks/s)
-host_mem_usage 218160 # Number of bytes of host memory used
-host_seconds 143.40 # Real time elapsed on the host
-sim_insts 349065408 # Number of instructions simulated
+host_inst_rate 2097833 # Simulator instruction rate (inst/s)
+host_op_rate 2681977 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1631504750 # Simulator tick rate (ticks/s)
+host_mem_usage 220728 # Number of bytes of host memory used
+host_seconds 130.15 # Real time elapsed on the host
+sim_insts 273037671 # Number of instructions simulated
+sim_ops 349065408 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1875350709 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1394641440 # Number of instructions bytes read from this memory
system.physmem.bytes_written 400047783 # Number of bytes written to this memory
system.cpu.numCycles 424688097 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 349065408 # Number of instructions executed
+system.cpu.committedInsts 273037671 # Number of instructions committed
+system.cpu.committedOps 349065408 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 279584926 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 114216705 # Number of float alu accesses
system.cpu.num_func_calls 12433363 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:03:55
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:01:56
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 525854475000 # Number of ticks simulated
final_tick 525854475000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1206167 # Simulator instruction rate (inst/s)
-host_tick_rate 1819018700 # Simulator tick rate (ticks/s)
-host_mem_usage 227092 # Number of bytes of host memory used
-host_seconds 289.09 # Real time elapsed on the host
-sim_insts 348687131 # Number of instructions simulated
+host_inst_rate 1153060 # Simulator instruction rate (inst/s)
+host_op_rate 1474144 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2223154070 # Simulator tick rate (ticks/s)
+host_mem_usage 229624 # Number of bytes of host memory used
+host_seconds 236.54 # Real time elapsed on the host
+sim_insts 272739291 # Number of instructions simulated
+sim_ops 348687131 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 437312 # Number of bytes read from this memory
system.physmem.bytes_inst_read 167040 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 1051708950 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 348687131 # Number of instructions executed
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system.cpu.icache.avg_refs 22344.725758 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.icache.ReadReq_miss_latency 328062000 # number of ReadReq miss cycles
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-system.cpu.l2cache.overall_miss_latency 355316000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 17209 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 998 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 2872 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 20081 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 20081 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.231100 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.994429 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.340272 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.340272 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 341.613272 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 2402.300580 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 731.759070 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.010425 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.073312 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.022332 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.106069 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 12993 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 239 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 13232 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 998 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 998 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 16 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 16 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 12993 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 255 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 13248 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 12993 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 255 # number of overall hits
+system.cpu.l2cache.overall_hits::total 13248 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2610 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1367 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 3977 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 2856 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 2856 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2610 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 4223 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 6833 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2610 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 4223 # number of overall misses
+system.cpu.l2cache.overall_misses::total 6833 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 135720000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 71084000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 206804000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 148512000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 148512000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 135720000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 219596000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 355316000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 135720000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 219596000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 355316000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 15603 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1606 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 17209 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 998 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 998 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 2872 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 2872 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 15603 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 4478 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 20081 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 15603 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 4478 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 20081 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.167276 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.851183 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.994429 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.167276 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.943055 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.167276 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.943055 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 3977 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 2856 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 6833 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 6833 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 159080000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 114240000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 273320000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 273320000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.231100 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994429 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.340272 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.340272 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2610 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1367 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3977 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 2856 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 2856 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2610 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 4223 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 6833 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2610 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 4223 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 6833 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 54680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 159080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 114240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 114240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 168920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 273320000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 168920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 273320000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.851183 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994429 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.167276 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.943055 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:26:04
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:28
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 643030478500 # Number of ticks simulated
final_tick 643030478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 153915 # Simulator instruction rate (inst/s)
-host_tick_rate 54289503 # Simulator tick rate (ticks/s)
-host_mem_usage 215008 # Number of bytes of host memory used
-host_seconds 11844.47 # Real time elapsed on the host
+host_inst_rate 198283 # Simulator instruction rate (inst/s)
+host_op_rate 198283 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69939236 # Simulator tick rate (ticks/s)
+host_mem_usage 217424 # Number of bytes of host memory used
+host_seconds 9194.13 # Real time elapsed on the host
sim_insts 1823043370 # Number of instructions simulated
+sim_ops 1823043370 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94779264 # Number of bytes read from this memory
system.physmem.bytes_inst_read 185664 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4281472 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.675414 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2008987604 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 2008987604 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 979738658 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 39 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 28886163 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1150060787 # Number of insts commited each cycle
-system.cpu.commit.count 2008987604 # Number of instructions committed
+system.cpu.commit.committedInsts 2008987604 # Number of instructions committed
+system.cpu.commit.committedOps 2008987604 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 721864922 # Number of memory references committed
system.cpu.commit.loads 511070026 # Number of loads committed
system.cpu.timesIdled 3507 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 125916 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1823043370 # Number of Instructions Simulated
+system.cpu.committedOps 1823043370 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1823043370 # Number of Instructions Simulated
system.cpu.cpi 0.705447 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.705447 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 9946 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 40046.175447 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1650.873085 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.806090 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 398299261 # number of ReadReq hits
-system.cpu.icache.demand_hits 398299261 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 398299261 # number of overall hits
-system.cpu.icache.ReadReq_misses 11100 # number of ReadReq misses
-system.cpu.icache.demand_misses 11100 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 11100 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 182477500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 182477500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 182477500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 398310361 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 398310361 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 398310361 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000028 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000028 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 16439.414414 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 16439.414414 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 16439.414414 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1650.873085 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.806090 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.806090 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 398299261 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 398299261 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 398299261 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 398299261 # number of demand (read+write) hits
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system.cpu.dcache.tagsinuse 4095.113983 # Cycle average of tags in use
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1480630 # number of replacements
system.cpu.l2cache.tagsinuse 31935.913288 # Cycle average of tags in use
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.Writeback_hits 107326 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 4750 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 60709 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 60709 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1414071 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 66855 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 1480926 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 1480926 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 48513510000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2349021500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 50862531500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 50862531500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 1470030 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 107326 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 71605 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 1541635 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 1541635 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.961933 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.933664 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.960620 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.960620 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34307.690349 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.063122 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34345.086453 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34345.086453 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 3059.437870 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 43.056925 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28833.418493 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.093367 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001314 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.879926 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.974607 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 7046 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 48913 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 55959 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 107326 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 107326 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 4750 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 4750 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 7046 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 53663 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 60709 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 7046 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 53663 # number of overall hits
+system.cpu.l2cache.overall_hits::total 60709 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2901 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1411170 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1414071 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 66855 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 66855 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2901 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1478025 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1480926 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2901 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1478025 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1480926 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 99564500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 48413945500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 48513510000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2349021500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2349021500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 99564500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 50762967000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 50862531500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 99564500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 50762967000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 50862531500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 9947 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1460083 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1470030 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 107326 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 107326 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 71605 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 71605 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 9947 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1531688 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1541635 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 9947 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1531688 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1541635 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.291646 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.966500 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.933664 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.291646 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.964965 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.291646 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.964965 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.751465 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34307.663499 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35136.063122 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.751465 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 37500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66898 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1414071 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 66855 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 1480926 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 1480926 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43837380500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2147695000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 45985075500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 45985075500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961933 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.933664 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.960620 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.960620 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks
+system.cpu.l2cache.writebacks::total 66898 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2901 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1411170 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1414071 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66855 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66855 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2901 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1478025 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1480926 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2901 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1478025 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1480926 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 90197000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43747183500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 43837380500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2147695000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2147695000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 90197000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45894878500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 45985075500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 90197000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45894878500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 45985075500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.966500 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.933664 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.291646 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964965 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:26:36
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:42
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 1004710587000 # Number of ticks simulated
final_tick 1004710587000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4051601 # Simulator instruction rate (inst/s)
-host_tick_rate 2026237516 # Simulator tick rate (ticks/s)
-host_mem_usage 204820 # Number of bytes of host memory used
-host_seconds 495.85 # Real time elapsed on the host
+host_inst_rate 5076159 # Simulator instruction rate (inst/s)
+host_op_rate 5076159 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2538627026 # Simulator tick rate (ticks/s)
+host_mem_usage 206544 # Number of bytes of host memory used
+host_seconds 395.77 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
+sim_ops 2008987605 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11607100996 # Number of bytes read from this memory
system.physmem.bytes_inst_read 8037684280 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1586125963 # Number of bytes written to this memory
system.cpu.numCycles 2009421175 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2008987605 # Number of instructions executed
+system.cpu.committedInsts 2008987605 # Number of instructions committed
+system.cpu.committedOps 2008987605 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1779374816 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 71831671 # Number of float alu accesses
system.cpu.num_func_calls 79910682 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:28:03
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:14:25
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 2813467842000 # Number of ticks simulated
final_tick 2813467842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1954286 # Simulator instruction rate (inst/s)
-host_tick_rate 2736861040 # Simulator tick rate (ticks/s)
-host_mem_usage 213480 # Number of bytes of host memory used
-host_seconds 1027.99 # Real time elapsed on the host
+host_inst_rate 2306294 # Simulator instruction rate (inst/s)
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+host_seconds 871.09 # Real time elapsed on the host
sim_insts 2008987605 # Number of instructions simulated
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system.physmem.bytes_read 94708160 # Number of bytes read from this memory
system.physmem.bytes_inst_read 152128 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4281472 # Number of bytes written to this memory
system.cpu.numCycles 5626935684 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.icache.avg_refs 189638.587675 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.demand_hits 60925 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 60925 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1412942 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 66873 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 1479815 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 1479815 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 73472984000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3477396000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 76950380000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 76950380000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 1468788 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 107612 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 71952 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 1540740 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.961978 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.929411 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.960457 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.960457 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 3081.828747 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 33.409968 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28814.603011 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.094050 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001020 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.879352 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.974421 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 8219 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 47627 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 55846 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 107612 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 107612 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 5079 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 5079 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 8219 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 52706 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 60925 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 8219 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 52706 # number of overall hits
+system.cpu.l2cache.overall_hits::total 60925 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 2377 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1410565 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 1412942 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 66873 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 66873 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 2377 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 1477438 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 1479815 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 2377 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 1477438 # number of overall misses
+system.cpu.l2cache.overall_misses::total 1479815 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 123604000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 73349380000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 73472984000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3477396000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3477396000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 123604000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 76826776000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 76950380000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 123604000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 76826776000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 76950380000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 10596 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 1458192 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 1468788 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 107612 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 107612 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 71952 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 71952 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 10596 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 1530144 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1540740 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 10596 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1530144 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1540740 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.224330 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.967338 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.929411 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.224330 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.965555 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.224330 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.965555 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66898 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1412942 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 66873 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 1479815 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 1479815 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 56517680000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2674920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 59192600000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 59192600000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.961978 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.929411 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.960457 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.960457 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 66898 # number of writebacks
+system.cpu.l2cache.writebacks::total 66898 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2377 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1410565 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1412942 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66873 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 66873 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2377 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1477438 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 1479815 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2377 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1477438 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 1479815 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 95080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 56422600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 56517680000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 95080000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 59097520000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 59192600000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 95080000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 59097520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 59192600000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.967338 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.929411 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.224330 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.965555 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:06:03
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 708285420500 # Number of ticks simulated
final_tick 708285420500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74841 # Simulator instruction rate (inst/s)
-host_tick_rate 28116271 # Simulator tick rate (ticks/s)
-host_mem_usage 262240 # Number of bytes of host memory used
-host_seconds 25191.30 # Real time elapsed on the host
-sim_insts 1885333786 # Number of instructions simulated
+host_inst_rate 110657 # Simulator instruction rate (inst/s)
+host_op_rate 150700 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 56615274 # Simulator tick rate (ticks/s)
+host_mem_usage 229476 # Number of bytes of host memory used
+host_seconds 12510.50 # Real time elapsed on the host
+sim_insts 1384379033 # Number of instructions simulated
+sim_ops 1885333786 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94806144 # Number of bytes read from this memory
system.physmem.bytes_inst_read 201024 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.741158 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.534869 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1885344802 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 1384390049 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1885344802 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 1192760864 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 211330 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 38418907 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1198732893 # Number of insts commited each cycle
-system.cpu.commit.count 1885344802 # Number of instructions committed
+system.cpu.commit.committedInsts 1384390049 # Number of instructions committed
+system.cpu.commit.committedOps 1885344802 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 908385853 # Number of memory references committed
system.cpu.commit.loads 631388869 # Number of loads committed
system.cpu.rob.rob_writes 6322749564 # The number of ROB writes
system.cpu.timesIdled 1340847 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 51326273 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1885333786 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1885333786 # Number of Instructions Simulated
-system.cpu.cpi 0.751363 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.751363 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.330914 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.330914 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 1384379033 # Number of Instructions Simulated
+system.cpu.committedOps 1885333786 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1384379033 # Number of Instructions Simulated
+system.cpu.cpi 1.023254 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.023254 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.977275 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.977275 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 12567200244 # number of integer regfile reads
system.cpu.int_regfile_writes 2359430733 # number of integer regfile writes
system.cpu.fp_regfile_reads 68800397 # number of floating regfile reads
system.cpu.icache.sampled_refs 28920 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 13283.635685 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1638.335274 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.799968 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 384163979 # number of ReadReq hits
-system.cpu.icache.demand_hits 384163979 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 384163979 # number of overall hits
-system.cpu.icache.ReadReq_misses 34037 # number of ReadReq misses
-system.cpu.icache.demand_misses 34037 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 34037 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 300707500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 300707500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 300707500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 384198016 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 384198016 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 384198016 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000089 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000089 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000089 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 8834.723977 # average ReadReq miss latency
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-system.cpu.l2cache.occ_percent::1 0.090545 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 76806 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 106815 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits 4 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits 6620 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 83426 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 83426 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 1415291 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses 4338 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses 66082 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 1481373 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 1481373 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 48556724500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2252633500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 50809358000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 50809358000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 1492097 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 106815 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses 4342 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 72702 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 1564799 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 1564799 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.948525 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate 0.999079 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.908943 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.946686 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.946686 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34308.650659 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.458279 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34298.828182 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34298.828182 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 2966.972548 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 53.821499 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 28949.663167 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.090545 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.001643 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.883474 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.975661 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 25776 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 51030 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 76806 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 106815 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 106815 # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total 4 # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 6620 # number of ReadExReq hits
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+system.cpu.l2cache.demand_hits::cpu.inst 25776 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 57650 # number of demand (read+write) hits
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+system.cpu.l2cache.overall_hits::cpu.data 57650 # number of overall hits
+system.cpu.l2cache.overall_hits::total 83426 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 3145 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 1412146 # number of ReadReq misses
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+system.cpu.l2cache.UpgradeReq_misses::cpu.data 4338 # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total 4338 # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 66082 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 66082 # number of ReadExReq misses
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+system.cpu.l2cache.demand_misses::cpu.data 1478228 # number of demand (read+write) misses
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+system.cpu.l2cache.overall_misses::cpu.data 1478228 # number of overall misses
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+system.cpu.l2cache.demand_miss_latency::cpu.data 50701527000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 50809358000 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data 50701527000 # number of overall miss cycles
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+system.cpu.l2cache.ReadReq_accesses::cpu.inst 28921 # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.Writeback_accesses::writebacks 106815 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 106815 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data 4342 # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total 4342 # number of UpgradeReq accesses(hits+misses)
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+system.cpu.l2cache.demand_accesses::cpu.data 1535878 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 1564799 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 28921 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 1535878 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 1564799 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.108745 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.965124 # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.999079 # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.908943 # miss rate for ReadExReq accesses
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+system.cpu.l2cache.demand_miss_rate::cpu.data 0.962464 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.108745 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.962464 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.486486 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34308.700021 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34088.458279 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.486486 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.854439 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 66099 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 27 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 27 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 27 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1415264 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 4338 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 66082 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 1481346 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 1481346 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 43971004500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 134478000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2048597500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 46019602000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 46019602000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.948507 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.999079 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908943 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.946669 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.946669 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118200 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072342 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 66099 # number of writebacks
+system.cpu.l2cache.writebacks::total 66099 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits
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+system.cpu.l2cache.demand_mshr_hits::cpu.data 23 # number of demand (read+write) MSHR hits
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+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 4338 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 4338 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66082 # number of ReadExReq MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3141 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1478205 # number of demand (read+write) MSHR misses
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+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3141 # number of overall MSHR misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 97624500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 43873380000 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 134478000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 134478000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2048597500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2048597500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 97624500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 45921977500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 46019602000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 97624500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 45921977500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 46019602000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.965108 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.999079 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.908943 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.108606 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.962449 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:17:45
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:09:56
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 945613131000 # Number of ticks simulated
final_tick 945613131000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2997522 # Simulator instruction rate (inst/s)
-host_tick_rate 1503443037 # Simulator tick rate (ticks/s)
-host_mem_usage 215364 # Number of bytes of host memory used
-host_seconds 628.97 # Real time elapsed on the host
-sim_insts 1885336367 # Number of instructions simulated
+host_inst_rate 2494982 # Simulator instruction rate (inst/s)
+host_op_rate 3397821 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1704217996 # Simulator tick rate (ticks/s)
+host_mem_usage 217680 # Number of bytes of host memory used
+host_seconds 554.87 # Real time elapsed on the host
+sim_insts 1384381614 # Number of instructions simulated
+sim_ops 1885336367 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8025491315 # Number of bytes read from this memory
system.physmem.bytes_inst_read 5561086040 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1123958396 # Number of bytes written to this memory
system.cpu.numCycles 1891226263 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1885336367 # Number of instructions executed
+system.cpu.committedInsts 1384381614 # Number of instructions committed
+system.cpu.committedOps 1885336367 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:28:26
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:19:22
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 2369901960000 # Number of ticks simulated
final_tick 2369901960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1407810 # Simulator instruction rate (inst/s)
-host_tick_rate 1780114775 # Simulator tick rate (ticks/s)
-host_mem_usage 224180 # Number of bytes of host memory used
-host_seconds 1331.32 # Real time elapsed on the host
-sim_insts 1874244950 # Number of instructions simulated
+host_inst_rate 1307856 # Simulator instruction rate (inst/s)
+host_op_rate 1774200 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2243399723 # Simulator tick rate (ticks/s)
+host_mem_usage 226844 # Number of bytes of host memory used
+host_seconds 1056.39 # Real time elapsed on the host
+sim_insts 1381604347 # Number of instructions simulated
+sim_ops 1874244950 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 94696320 # Number of bytes read from this memory
system.physmem.bytes_inst_read 144448 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4230336 # Number of bytes written to this memory
system.cpu.numCycles 4739803920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1874244950 # Number of instructions executed
+system.cpu.committedInsts 1381604347 # Number of instructions committed
+system.cpu.committedOps 1874244950 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1653698876 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 52289415 # Number of float alu accesses
system.cpu.num_func_calls 80344203 # number of times a function call or return occured
system.cpu.icache.sampled_refs 19803 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70204.095743 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1392.324437 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.679846 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1390251708 # number of ReadReq hits
-system.cpu.icache.demand_hits 1390251708 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1390251708 # number of overall hits
-system.cpu.icache.ReadReq_misses 19803 # number of ReadReq misses
-system.cpu.icache.demand_misses 19803 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 19803 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 372036000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 372036000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 372036000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1390271511 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1390271511 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1390271511 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000014 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000014 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000014 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 18786.850477 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 18786.850477 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 18786.850477 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1392.324437 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.679846 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1390251708 # number of ReadReq hits
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+system.cpu.icache.ReadReq_accesses::cpu.inst 1390271511 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 19803 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 19803 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 19803 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 312627000 # number of ReadReq MSHR miss cycles
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-system.cpu.icache.overall_mshr_miss_latency 312627000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000014 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.overall_mshr_miss_rate 0.000014 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1529557 # number of replacements
system.cpu.dcache.tagsinuse 4094.960333 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1533653 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 584.067849 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 997882000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.ReadReq_accesses 620335414 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602 # average ReadReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602 # average ReadReq mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 1478755 # number of replacements
system.cpu.l2cache.tagsinuse 31934.844118 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 1511475 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.049920 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 28893.420796 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 3041.423322 # Average occupied blocks per context
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-system.cpu.l2cache.occ_percent::1 0.092817 # Average percentage of cache occupancy
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-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 3041.423322 # Average occupied blocks per requestor
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1413537 # number of ReadReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses 1479630 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 56541480000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2643720000 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.954657 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.908120 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.952476 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.952476 # mshr miss rate for overall accesses
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-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.writebacks::total 66099 # number of writebacks
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:28:56
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:15:15
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 46914279500 # Number of ticks simulated
final_tick 46914279500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 107347 # Simulator instruction rate (inst/s)
-host_tick_rate 57007816 # Simulator tick rate (ticks/s)
-host_mem_usage 216192 # Number of bytes of host memory used
-host_seconds 822.94 # Real time elapsed on the host
+host_inst_rate 145791 # Simulator instruction rate (inst/s)
+host_op_rate 145791 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 77424105 # Simulator tick rate (ticks/s)
+host_mem_usage 218104 # Number of bytes of host memory used
+host_seconds 605.94 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11164096 # Number of bytes read from this memory
system.physmem.bytes_inst_read 599296 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7712960 # Number of bytes written to this memory
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
-system.cpu.committedInsts 88340673 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 88340673 # Number of Instructions Simulated (Total)
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+system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
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+system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 1.062122 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.062122 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 85656 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 143.171266 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1886.858130 # Average occupied blocks per context
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-system.cpu.icache.ReadReq_miss_latency 2068004000 # number of ReadReq miss cycles
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2088724500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2088724500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7254420000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 7254420000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9343144500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9343144500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9343144500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9343144500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 148060 # number of replacements
system.cpu.l2cache.tagsinuse 18663.556927 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 173405 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.757366 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 3005.792321 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15657.764606 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.091730 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.477837 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 103294 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 161216 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 12270 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 115564 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 115564 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 42939 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 131500 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 174439 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 174439 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 2242306500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 6854385000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 9096691500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 9096691500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 146233 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 161216 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 143770 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 290003 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 290003 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.293634 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.914655 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.601508 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.601508 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52148.266729 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52148.266729 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15657.764606 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1362.413436 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1643.378886 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.477837 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.041578 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.050152 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.569567 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 76292 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 27002 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 103294 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 161216 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 161216 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 12270 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 12270 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 76292 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 39272 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 115564 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 76292 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 39272 # number of overall hits
+system.cpu.l2cache.overall_hits::total 115564 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 9364 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 33575 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 42939 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 131500 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 131500 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 9364 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 165075 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 174439 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 9364 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 165075 # number of overall misses
+system.cpu.l2cache.overall_misses::total 174439 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 489614500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1752692000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 2242306500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6854385000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6854385000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 489614500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8607077000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 9096691500 # number of demand (read+write) miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data 8607077000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 9096691500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 85656 # number of ReadReq accesses(hits+misses)
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+system.cpu.l2cache.ReadReq_accesses::total 146233 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 161216 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 161216 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 143770 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 143770 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 85656 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 290003 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 85656 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 290003 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.109321 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.554253 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.914655 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.109321 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.807817 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.109321 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.807817 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 120515 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 42939 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 131500 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 174439 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 174439 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1718628500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5262711000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 6981339500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 6981339500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.293634 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.914655 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.601508 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.601508 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 120515 # number of writebacks
+system.cpu.l2cache.writebacks::total 120515 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 9364 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33575 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 42939 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131500 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 131500 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 9364 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 165075 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 174439 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 9364 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 165075 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 174439 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 375279000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343349500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1718628500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5262711000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5262711000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 375279000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6606060500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6981339500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 375279000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6606060500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6981339500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.554253 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.914655 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.109321 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807817 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:35:02
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:19:29
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 21259532000 # Number of ticks simulated
final_tick 21259532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 187781 # Simulator instruction rate (inst/s)
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system.physmem.bytes_written 7713344 # Number of bytes written to this memory
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system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
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system.cpu.commit.branchMispredicts 366565 # The number of times a branch was mispredicted
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system.cpu.idleCycles 394564 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 79591756 # Number of Instructions Simulated
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system.cpu.committedInsts_total 79591756 # Number of Instructions Simulated
system.cpu.cpi 0.534214 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.534214 # CPI: Total CPI of All Threads
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+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6012059000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6012059000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6012059000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6012059000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002971 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009813 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005787 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20602.704619 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33012.720197 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29264.875679 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 149119 # number of replacements
system.cpu.l2cache.tagsinuse 18923.797261 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 174485 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.784371 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 3200.297768 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15723.499493 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.097665 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.479843 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 108391 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 161613 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 12014 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 120405 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 120405 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 44050 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 131408 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 175458 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 175458 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1516062500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 4525488500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 6041551000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 6041551000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 152441 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 161613 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 143422 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 295863 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 295863 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.288964 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.916233 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.593038 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.593038 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34416.855846 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34438.455041 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34433.032407 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34433.032407 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15723.499493 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1497.146716 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1703.151052 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.479843 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.045689 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.051976 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.577508 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 80385 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 28006 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 108391 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 161613 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 161613 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 12014 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 12014 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 80385 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 40020 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 120405 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 80385 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 40020 # number of overall hits
+system.cpu.l2cache.overall_hits::total 120405 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 10042 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 34008 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 44050 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 131408 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 131408 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 10042 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 165416 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 175458 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 10042 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 165416 # number of overall misses
+system.cpu.l2cache.overall_misses::total 175458 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 344615000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1171447500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 1516062500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4525488500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4525488500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 344615000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 5696936000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 6041551000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 344615000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 5696936000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 6041551000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 90427 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 62014 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 152441 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 161613 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 161613 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 143422 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 143422 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 90427 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 205436 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 295863 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 90427 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 205436 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 295863 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.111051 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.548392 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.916233 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.111051 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.805195 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.111051 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.805195 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.367058 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34446.233239 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.455041 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.367058 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.054166 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.367058 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.054166 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 120521 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 44050 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 131408 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 175458 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 175458 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1367587500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 4118168500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 5485756000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 5485756000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.288964 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.916233 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.593038 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.593038 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.254257 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31338.795964 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31265.351252 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 120521 # number of writebacks
+system.cpu.l2cache.writebacks::total 120521 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10042 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 34008 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 44050 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131408 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 131408 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 10042 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 165416 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 175458 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 10042 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 165416 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 175458 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 312130500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1055457000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1367587500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4118168500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4118168500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 312130500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5173625500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 5485756000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 312130500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5173625500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 5485756000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.548392 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.916233 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.111051 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.805195 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.503485 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.550459 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31338.795964 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.503485 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31276.451492 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:42:17
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:25:10
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 44221003000 # Number of ticks simulated
final_tick 44221003000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3998504 # Simulator instruction rate (inst/s)
-host_tick_rate 2001543652 # Simulator tick rate (ticks/s)
-host_mem_usage 206876 # Number of bytes of host memory used
-host_seconds 22.09 # Real time elapsed on the host
+host_inst_rate 5044223 # Simulator instruction rate (inst/s)
+host_op_rate 5044217 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2524999281 # Simulator tick rate (ticks/s)
+host_mem_usage 208636 # Number of bytes of host memory used
+host_seconds 17.51 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 480454939 # Number of bytes read from this memory
system.physmem.bytes_inst_read 353752292 # Number of instructions bytes read from this memory
system.physmem.bytes_written 91652896 # Number of bytes written to this memory
system.cpu.numCycles 88442007 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 88340673 # Number of instructions executed
+system.cpu.committedInsts 88340673 # Number of instructions committed
+system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:42:49
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:25:32
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 134276988000 # Number of ticks simulated
final_tick 134276988000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1801981 # Simulator instruction rate (inst/s)
-host_tick_rate 2738992827 # Simulator tick rate (ticks/s)
-host_mem_usage 215584 # Number of bytes of host memory used
-host_seconds 49.02 # Real time elapsed on the host
+host_inst_rate 2261546 # Simulator instruction rate (inst/s)
+host_op_rate 2261545 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3437525661 # Simulator tick rate (ticks/s)
+host_mem_usage 217500 # Number of bytes of host memory used
+host_seconds 39.06 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
+sim_ops 88340673 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 11121920 # Number of bytes read from this memory
system.physmem.bytes_inst_read 558272 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7712384 # Number of bytes written to this memory
system.cpu.numCycles 268553976 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 88340673 # Number of instructions executed
+system.cpu.committedInsts 88340673 # Number of instructions committed
+system.cpu.committedOps 88340673 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 78039444 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 267757 # Number of float alu accesses
system.cpu.num_func_calls 3321606 # number of times a function call or return occured
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1156.021220 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1871.404551 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.913772 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 88361638 # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
-system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 76436 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 1436470000 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_miss_rate 0.000864 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency 18793.107960 # average ReadReq miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 200248 # number of replacements
system.cpu.dcache.tagsinuse 4078.858373 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 204344 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 943232000 # Cycle when the warmup percentage was hit.
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+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 147405 # number of replacements
system.cpu.l2cache.tagsinuse 18614.813333 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 172748 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.711777 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 2806.549776 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15808.263557 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.085649 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.482430 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 94901 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 161222 # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits 12099 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 107000 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 107000 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 42301 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 131479 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 173780 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 173780 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 2199652000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 6836908000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 9036560000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 9036560000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 137202 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 161222 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 143578 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 280780 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 280780 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.308312 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.915732 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.618919 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.618919 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15808.263557 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 1305.254425 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1501.295351 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.482430 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.039833 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.045816 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.568079 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 67713 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 27188 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 94901 # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks 161222 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 161222 # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data 12099 # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total 12099 # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 67713 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 39287 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 107000 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 67713 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 39287 # number of overall hits
+system.cpu.l2cache.overall_hits::total 107000 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 8723 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 33578 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 42301 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 131479 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 131479 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 8723 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 165057 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 173780 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 8723 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 165057 # number of overall misses
+system.cpu.l2cache.overall_misses::total 173780 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 453596000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1746056000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 2199652000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6836908000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 6836908000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 453596000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8582964000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 9036560000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 453596000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8582964000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 9036560000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 76436 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 60766 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 137202 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks 161222 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total 161222 # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 143578 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 143578 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 76436 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 204344 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 280780 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 76436 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 204344 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 280780 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.114122 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.552579 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.915732 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.114122 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.807741 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.114122 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.807741 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 120506 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 42301 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 131479 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 173780 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 173780 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1692040000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 5259160000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 6951200000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 6951200000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.308312 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.915732 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.618919 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.618919 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 120506 # number of writebacks
+system.cpu.l2cache.writebacks::total 120506 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 8723 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 33578 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 42301 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 131479 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 131479 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 8723 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 165057 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 173780 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 8723 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 165057 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 173780 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 348920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1343120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1692040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5259160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5259160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 348920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6602280000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 6951200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 348920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6602280000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 6951200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.552579 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.915732 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.114122 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.807741 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:25:27
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 31189496500 # Number of ticks simulated
final_tick 31189496500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 53036 # Simulator instruction rate (inst/s)
-host_tick_rate 16437569 # Simulator tick rate (ticks/s)
-host_mem_usage 264816 # Number of bytes of host memory used
-host_seconds 1897.45 # Real time elapsed on the host
-sim_insts 100634170 # Number of instructions simulated
+host_inst_rate 144507 # Simulator instruction rate (inst/s)
+host_op_rate 205068 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 63556485 # Simulator tick rate (ticks/s)
+host_mem_usage 231932 # Number of bytes of host memory used
+host_seconds 490.74 # Real time elapsed on the host
+sim_insts 70914922 # Number of instructions simulated
+sim_ops 100634170 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8651712 # Number of bytes read from this memory
system.physmem.bytes_inst_read 350080 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5661248 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.689926 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.519070 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 100639722 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 70920474 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 100639722 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 11954174 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 703033 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 788567 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 59169182 # Number of insts commited each cycle
-system.cpu.commit.count 100639722 # Number of instructions committed
+system.cpu.commit.committedInsts 70920474 # Number of instructions committed
+system.cpu.commit.committedOps 100639722 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 47865761 # Number of memory references committed
system.cpu.commit.loads 27308566 # Number of loads committed
system.cpu.rob.rob_writes 227096473 # The number of ROB writes
system.cpu.timesIdled 61617 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 1306838 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 100634170 # Number of Instructions Simulated
-system.cpu.committedInsts_total 100634170 # Number of Instructions Simulated
-system.cpu.cpi 0.619859 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.619859 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.613270 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.613270 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 70914922 # Number of Instructions Simulated
+system.cpu.committedOps 100634170 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 70914922 # Number of Instructions Simulated
+system.cpu.cpi 0.879631 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.879631 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.136840 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.136840 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 511674990 # number of integer regfile reads
system.cpu.int_regfile_writes 103897673 # number of integer regfile writes
system.cpu.fp_regfile_reads 166 # number of floating regfile reads
system.cpu.icache.sampled_refs 28166 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 432.448981 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1805.600642 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.881641 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 12180359 # number of ReadReq hits
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-system.cpu.icache.overall_hits 12180359 # number of overall hits
-system.cpu.icache.ReadReq_misses 29272 # number of ReadReq misses
-system.cpu.icache.demand_misses 29272 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 29272 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 357988500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 357988500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 357988500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 12209631 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 12209631 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 12209631 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.002397 # miss rate for ReadReq accesses
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-system.cpu.icache.overall_miss_rate 0.002397 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 12229.724652 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 12229.724652 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 12229.724652 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1805.600642 # Average occupied blocks per requestor
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+system.cpu.icache.ReadReq_misses::cpu.inst 29272 # number of ReadReq misses
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+system.cpu.icache.ReadReq_accesses::cpu.inst 12209631 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_mshr_hits 1063 # number of ReadReq MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses 28209 # number of ReadReq MSHR misses
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157892 # number of replacements
system.cpu.dcache.tagsinuse 4072.334227 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 161988 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 276.232869 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 306594000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.avg_blocked_cycles::no_targets 19050 # average number of cycles each access was blocked
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+system.cpu.dcache.demand_mshr_miss_latency::total 4698165500 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698165500 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4698165500 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002079 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005386 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003495 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18793.125034 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34253.834643 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28995.115193 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 114916 # number of replacements
system.cpu.l2cache.tagsinuse 18304.706842 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 133774 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.541817 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 2370.559791 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 15934.147051 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.072344 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.486272 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 50571 # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits 123474 # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits 14 # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits 4310 # number of ReadExReq hits
-system.cpu.l2cache.demand_hits 54881 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 54881 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 32667 # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses 30 # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses 102597 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 135264 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 135264 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 1118379000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3526118000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 4644497000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 4644497000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 83238 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses 123474 # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses 44 # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 106907 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 190145 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 190145 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.392453 # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate 0.681818 # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 0.959685 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.711373 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.711373 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34235.742492 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.626763 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34336.534481 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34336.534481 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15934.147051 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 839.668596 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 1530.891195 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks 0.486272 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst 0.025625 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.046719 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.558615 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 22667 # number of ReadReq hits
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+system.cpu.l2cache.Writeback_hits::writebacks 123474 # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total 123474 # number of Writeback hits
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+system.cpu.l2cache.overall_hits::cpu.data 32214 # number of overall hits
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+system.cpu.l2cache.overall_miss_latency::total 4644497000 # number of overall miss cycles
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+system.cpu.l2cache.Writeback_accesses::total 123474 # number of Writeback accesses(hits+misses)
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+system.cpu.l2cache.demand_accesses::cpu.data 161984 # number of demand (read+write) accesses
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+system.cpu.l2cache.overall_accesses::cpu.data 161984 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 190145 # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763 # average ReadExReq miss latency
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 88457 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 81 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 81 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 81 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 32586 # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses 30 # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 102597 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 135183 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 135183 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1012814500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency 931000 # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3197894500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 4210709000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 4210709000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.391480 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate 0.681818 # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.959685 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.710947 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.710947 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.277236 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31033.333333 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.473766 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31148.213903 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 88457 # number of writebacks
+system.cpu.l2cache.writebacks::total 88457 # number of writebacks
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+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 931000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 931000 # number of UpgradeReq MSHR miss cycles
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 169929500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4040779500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 4210709000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4040779500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 4210709000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.492329 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.681818 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.959685 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.194240 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.800777 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:35:25
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:26:23
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 53932162000 # Number of ticks simulated
final_tick 53932162000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3016681 # Simulator instruction rate (inst/s)
-host_tick_rate 1616735818 # Simulator tick rate (ticks/s)
-host_mem_usage 217624 # Number of bytes of host memory used
-host_seconds 33.36 # Real time elapsed on the host
-sim_insts 100632437 # Number of instructions simulated
+host_inst_rate 2464229 # Simulator instruction rate (inst/s)
+host_op_rate 3496968 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1874136829 # Simulator tick rate (ticks/s)
+host_mem_usage 220180 # Number of bytes of host memory used
+host_seconds 28.78 # Real time elapsed on the host
+sim_insts 70913189 # Number of instructions simulated
+sim_ops 100632437 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 419153654 # Number of bytes read from this memory
system.physmem.bytes_inst_read 312580308 # Number of instructions bytes read from this memory
system.physmem.bytes_written 78660211 # Number of bytes written to this memory
system.cpu.numCycles 107864325 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 100632437 # Number of instructions executed
+system.cpu.committedInsts 70913189 # Number of instructions committed
+system.cpu.committedOps 100632437 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3287514 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:36:06
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:27:02
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 133117442000 # Number of ticks simulated
final_tick 133117442000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1410680 # Simulator instruction rate (inst/s)
-host_tick_rate 1881780580 # Simulator tick rate (ticks/s)
-host_mem_usage 226592 # Number of bytes of host memory used
-host_seconds 70.74 # Real time elapsed on the host
-sim_insts 99791663 # Number of instructions simulated
+host_inst_rate 1269489 # Simulator instruction rate (inst/s)
+host_op_rate 1800168 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2401339947 # Simulator tick rate (ticks/s)
+host_mem_usage 229088 # Number of bytes of host memory used
+host_seconds 55.43 # Real time elapsed on the host
+sim_insts 70373636 # Number of instructions simulated
+sim_ops 99791663 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8570688 # Number of bytes read from this memory
system.physmem.bytes_inst_read 294208 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5660736 # Number of bytes written to this memory
system.cpu.numCycles 266234884 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 99791663 # Number of instructions executed
+system.cpu.committedInsts 70373636 # Number of instructions committed
+system.cpu.committedOps 99791663 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 91472788 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses
system.cpu.num_func_calls 3287514 # number of times a function call or return occured
system.cpu.icache.sampled_refs 18908 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4131.910831 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1736.182852 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.847746 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 78126170 # number of ReadReq hits
-system.cpu.icache.demand_hits 78126170 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 78126170 # number of overall hits
-system.cpu.icache.ReadReq_misses 18908 # number of ReadReq misses
-system.cpu.icache.demand_misses 18908 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 18908 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 457786000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 457786000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 457786000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 78145078 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 78145078 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 78145078 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000242 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000242 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000242 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 24211.233340 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 24211.233340 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 24211.233340 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1736.182852 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.847746 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.847746 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 78126170 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 78126170 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 78126170 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 78126170 # number of demand (read+write) hits
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+system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 18908 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 18908 # number of overall misses
+system.cpu.icache.overall_misses::total 18908 # number of overall misses
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+system.cpu.icache.ReadReq_miss_latency::total 457786000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 457786000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 457786000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 457786000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 457786000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 78145078 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 78145078 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 78145078 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 78145078 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 78145078 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses
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+system.cpu.icache.overall_miss_rate::cpu.inst 0.000242 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340 # average ReadReq miss latency
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 18908 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 18908 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 18908 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 401062000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 401062000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 401062000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000242 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000242 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000242 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 18908 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 18908 # number of ReadReq MSHR misses
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+system.cpu.icache.demand_mshr_misses::total 18908 # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total 18908 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 155902 # number of replacements
system.cpu.dcache.tagsinuse 4076.934010 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 159998 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 292.891630 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 1079641000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4076.934010 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.995345 # Average percentage of cache occupancy
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-system.cpu.dcache.StoreCondReq_hits 15919 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 46830237 # number of demand (read+write) hits
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-system.cpu.dcache.ReadReq_miss_latency 1862630000 # number of ReadReq miss cycles
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-system.cpu.dcache.ReadReq_accesses 27140334 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.StoreCondReq_accesses 15919 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 46990235 # number of demand (read+write) accesses
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-system.cpu.dcache.ReadReq_miss_rate 0.001952 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.005392 # miss rate for WriteReq accesses
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-system.cpu.dcache.overall_miss_rate 0.003405 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529 # average WriteReq miss latency
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+system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529 # average WriteReq mshr miss latency
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-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 113660 # number of replacements
system.cpu.l2cache.tagsinuse 18191.621028 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 132489 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.466454 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 2165.921088 # Average occupied blocks per context
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-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.ReadReq_mshr_misses 31290 # number of ReadReq MSHR misses
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-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 1251600000 # number of ReadReq MSHR miss cycles
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-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:24:20
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:00:16
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 68148678500 # Number of ticks simulated
final_tick 68148678500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3420916 # Simulator instruction rate (inst/s)
-host_tick_rate 1712444497 # Simulator tick rate (ticks/s)
-host_mem_usage 214012 # Number of bytes of host memory used
-host_seconds 39.80 # Real time elapsed on the host
-sim_insts 136139203 # Number of instructions simulated
+host_inst_rate 3965699 # Simulator instruction rate (inst/s)
+host_op_rate 4017046 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2010855033 # Simulator tick rate (ticks/s)
+host_mem_usage 211680 # Number of bytes of host memory used
+host_seconds 33.89 # Real time elapsed on the host
+sim_insts 134398975 # Number of instructions simulated
+sim_ops 136139203 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 685773693 # Number of bytes read from this memory
system.physmem.bytes_inst_read 538214332 # Number of instructions bytes read from this memory
system.physmem.bytes_written 89882950 # Number of bytes written to this memory
system.cpu.numCycles 136297358 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 136139203 # Number of instructions executed
+system.cpu.committedInsts 134398975 # Number of instructions committed
+system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:24:48
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:01:00
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 202941992000 # Number of ticks simulated
final_tick 202941992000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1608666 # Simulator instruction rate (inst/s)
-host_tick_rate 2398029397 # Simulator tick rate (ticks/s)
-host_mem_usage 222724 # Number of bytes of host memory used
-host_seconds 84.63 # Real time elapsed on the host
-sim_insts 136139203 # Number of instructions simulated
+host_inst_rate 1927976 # Simulator instruction rate (inst/s)
+host_op_rate 1952939 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2911235123 # Simulator tick rate (ticks/s)
+host_mem_usage 220544 # Number of bytes of host memory used
+host_seconds 69.71 # Real time elapsed on the host
+sim_insts 134398975 # Number of instructions simulated
+sim_ops 136139203 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 8970304 # Number of bytes read from this memory
system.physmem.bytes_inst_read 835264 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5584960 # Number of bytes written to this memory
system.cpu.numCycles 405883984 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 136139203 # Number of instructions executed
+system.cpu.committedInsts 134398975 # Number of instructions committed
+system.cpu.committedOps 136139203 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 115187758 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2326977 # Number of float alu accesses
system.cpu.num_func_calls 1709332 # number of times a function call or return occured
system.cpu.icache.sampled_refs 187024 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 718.445547 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 144544557000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 2004.721102 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.978868 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 134366560 # number of ReadReq hits
-system.cpu.icache.demand_hits 134366560 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 134366560 # number of overall hits
-system.cpu.icache.ReadReq_misses 187024 # number of ReadReq misses
-system.cpu.icache.demand_misses 187024 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 187024 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 3166478000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 3166478000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 3166478000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 134553584 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 134553584 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 134553584 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.001390 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.001390 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.001390 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 16930.864488 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 16930.864488 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 16930.864488 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 2004.721102 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.978868 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.978868 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 134366560 # number of ReadReq hits
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+system.cpu.icache.ReadReq_misses::cpu.inst 187024 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 187024 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 187024 # number of demand (read+write) misses
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+system.cpu.icache.overall_misses::total 187024 # number of overall misses
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+system.cpu.icache.ReadReq_miss_latency::total 3166478000 # number of ReadReq miss cycles
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+system.cpu.icache.demand_miss_latency::total 3166478000 # number of demand (read+write) miss cycles
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+system.cpu.icache.overall_miss_latency::total 3166478000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 134553584 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total 134553584 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001390 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses 187024 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 187024 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 187024 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 2605406000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 2605406000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 146582 # number of replacements
system.cpu.dcache.tagsinuse 4087.617150 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 150678 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 776708000 # Cycle when the warmup percentage was hit.
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.069782 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.843587 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:42:50
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:25:39
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 1009857089500 # Number of ticks simulated
final_tick 1009857089500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 102085 # Simulator instruction rate (inst/s)
-host_tick_rate 56650413 # Simulator tick rate (ticks/s)
-host_mem_usage 208040 # Number of bytes of host memory used
-host_seconds 17826.12 # Real time elapsed on the host
+host_inst_rate 137029 # Simulator instruction rate (inst/s)
+host_op_rate 137029 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 76042102 # Simulator tick rate (ticks/s)
+host_mem_usage 209964 # Number of bytes of host memory used
+host_seconds 13280.24 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
+sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 172617984 # Number of bytes read from this memory
system.physmem.bytes_inst_read 54912 # Number of instructions bytes read from this memory
system.physmem.bytes_written 74938304 # Number of bytes written to this memory
system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
system.cpu.comInts 916086844 # Number of Integer instructions committed
system.cpu.comFloats 190 # Number of Floating Point instructions committed
-system.cpu.committedInsts 1819780127 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 1819780127 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.109867 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 1.109867 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 858 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 271654.623543 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 664.479191 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.324453 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 233079667 # number of ReadReq hits
-system.cpu.icache.demand_hits 233079667 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 233079667 # number of overall hits
-system.cpu.icache.ReadReq_misses 1062 # number of ReadReq misses
-system.cpu.icache.demand_misses 1062 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 1062 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 58337000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 58337000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 58337000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 233080729 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 233080729 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 233080729 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54931.261770 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54931.261770 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54931.261770 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 664.479191 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.324453 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.324453 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 233079667 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 233079667 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 233079667 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 233079667 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 233079667 # number of overall hits
+system.cpu.icache.overall_hits::total 233079667 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 1062 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 1062 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 1062 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 1062 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 1062 # number of overall misses
+system.cpu.icache.overall_misses::total 1062 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 58337000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 58337000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 58337000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 58337000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 58337000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 58337000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 233080729 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 233080729 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 233080729 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 233080729 # number of demand (read+write) accesses
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+system.cpu.icache.overall_accesses::total 233080729 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 83500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 204 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 204 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 204 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 858 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 858 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 858 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 45872500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 45872500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 45872500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000004 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000004 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000004 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 204 # number of ReadReq MSHR hits
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+system.cpu.icache.overall_mshr_misses::total 858 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 45872500 # number of ReadReq MSHR miss cycles
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+system.cpu.icache.demand_mshr_miss_latency::total 45872500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 45872500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 45872500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107352 # number of replacements
system.cpu.dcache.tagsinuse 4082.611665 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 9111448 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.310155 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 12612838000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4082.611665 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.996731 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 437271428 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 157798653 # number of WriteReq hits
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-system.cpu.dcache.overall_hits 595070081 # number of overall hits
-system.cpu.dcache.ReadReq_misses 7324235 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 2929849 # number of WriteReq misses
-system.cpu.dcache.demand_misses 10254084 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 10254084 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 180892053500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 110288339500 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 291180393000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 291180393000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 444595663 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 160728502 # number of WriteReq accesses(hits+misses)
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-system.cpu.dcache.ReadReq_miss_rate 0.016474 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.018229 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.016940 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.016940 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 28396.528934 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 28396.528934 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4082.611665 # Average occupied blocks per requestor
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466 # average WriteReq miss latency
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+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10999000 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 8091026500 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 2761 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 3058572 # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits 101953 # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits 1040683 # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 1142636 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 1142636 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 7222282 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 1889166 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 9111448 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 9111448 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 59191835500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 215279506500 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 215279506500 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011754 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate 0.015052 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686299 # number of replacements
system.cpu.l2cache.tagsinuse 26355.239368 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 2710943 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790384 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 223979031000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 15511.274798 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 10843.964569 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.473367 # Average percentage of cache occupancy
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-system.cpu.l2cache.ReadReq_misses 1807881 # number of ReadReq misses
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-system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764 # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency 52262.790510 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 10843.964569 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst 26.537327 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 15484.737472 # Average occupied blocks per requestor
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system.cpu.l2cache.blocked_cycles::no_mshrs 580500 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 70 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1807881 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 889275 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 2697156 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 2697156 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 72354298500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 35671113500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 108025412000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 108025412000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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-system.cpu.l2cache.overall_mshr_miss_rate 0.295990 # mshr miss rate for overall accesses
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-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470613 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:43:49
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:26:22
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 615292058500 # Number of ticks simulated
final_tick 615292058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 151558 # Simulator instruction rate (inst/s)
-host_tick_rate 53715526 # Simulator tick rate (ticks/s)
-host_mem_usage 208624 # Number of bytes of host memory used
-host_seconds 11454.64 # Real time elapsed on the host
+host_inst_rate 195644 # Simulator instruction rate (inst/s)
+host_op_rate 195644 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 69340417 # Simulator tick rate (ticks/s)
+host_mem_usage 211040 # Number of bytes of host memory used
+host_seconds 8873.50 # Real time elapsed on the host
sim_insts 1736043781 # Number of instructions simulated
+sim_ops 1736043781 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 173080384 # Number of bytes read from this memory
system.physmem.bytes_inst_read 60288 # Number of instructions bytes read from this memory
system.physmem.bytes_written 74996480 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.790955 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 1819780126 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 1819780126 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 736139047 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 29 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 19443221 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 1119336917 # Number of insts commited each cycle
-system.cpu.commit.count 1819780126 # Number of instructions committed
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 605324165 # Number of memory references committed
system.cpu.commit.loads 444595663 # Number of loads committed
system.cpu.timesIdled 398057 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 5523098 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 1736043781 # Number of Instructions Simulated
+system.cpu.committedOps 1736043781 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 1736043781 # Number of Instructions Simulated
system.cpu.cpi 0.708844 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.708844 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 942 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 409129.244161 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 746.155324 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.364334 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 385399748 # number of ReadReq hits
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-system.cpu.icache.ReadReq_misses 1348 # number of ReadReq misses
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-system.cpu.icache.overall_misses 1348 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 47398000 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency 47398000 # number of overall miss cycles
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-system.cpu.icache.ReadReq_miss_rate 0.000003 # miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_miss_latency 35161.721068 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency 35161.721068 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9159821 # number of replacements
system.cpu.dcache.tagsinuse 4086.961398 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 9163917 # Sample count of references to valid blocks.
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system.cpu.dcache.warmup_cycle 5157991000 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked::no_mshrs 37813 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.WriteReq_mshr_hits 3028693 # number of WriteReq MSHR hits
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-system.cpu.dcache.ReadReq_mshr_misses 7278880 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 1885036 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 1 # number of LoadLockedReq MSHR misses
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-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 81039107500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency 119679464036 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.013285 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.011728 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11133.458375 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20498.471401 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 35500 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13059.860439 # average overall mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13059.860439 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2693797 # number of replacements
system.cpu.l2cache.tagsinuse 26669.588705 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 2718439 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.807918 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 126954186500 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 15903.024773 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 10766.563932 # Average occupied blocks per context
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-system.cpu.l2cache.overall_avg_miss_latency 34379.376279 # average overall miss latency
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system.cpu.l2cache.blocked_cycles::no_mshrs 17570000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 1704 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.overall_mshr_misses 2704381 # number of overall MSHR misses
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31149.150743 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31197.539504 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:45:21
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:29:07
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 913189263000 # Number of ticks simulated
final_tick 913189263000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4221832 # Simulator instruction rate (inst/s)
-host_tick_rate 2118570165 # Simulator tick rate (ticks/s)
-host_mem_usage 198896 # Number of bytes of host memory used
-host_seconds 431.04 # Real time elapsed on the host
+host_inst_rate 5189226 # Simulator instruction rate (inst/s)
+host_op_rate 5189226 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2604020675 # Simulator tick rate (ticks/s)
+host_mem_usage 200656 # Number of bytes of host memory used
+host_seconds 350.68 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
+sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 9280309971 # Number of bytes read from this memory
system.physmem.bytes_inst_read 7305514036 # Number of instructions bytes read from this memory
system.physmem.bytes_written 827777307 # Number of bytes written to this memory
system.cpu.numCycles 1826378527 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.committedInsts 1819780127 # Number of instructions committed
+system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:52:43
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:35:09
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 2663443716000 # Number of ticks simulated
final_tick 2663443716000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1948044 # Simulator instruction rate (inst/s)
-host_tick_rate 2851171142 # Simulator tick rate (ticks/s)
-host_mem_usage 207608 # Number of bytes of host memory used
-host_seconds 934.16 # Real time elapsed on the host
+host_inst_rate 2433308 # Simulator instruction rate (inst/s)
+host_op_rate 2433308 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3561407770 # Simulator tick rate (ticks/s)
+host_mem_usage 209524 # Number of bytes of host memory used
+host_seconds 747.86 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
+sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 172614208 # Number of bytes read from this memory
system.physmem.bytes_inst_read 51328 # Number of instructions bytes read from this memory
system.physmem.bytes_written 74939072 # Number of bytes written to this memory
system.cpu.numCycles 5326887432 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1819780127 # Number of instructions executed
+system.cpu.committedInsts 1819780127 # Number of instructions committed
+system.cpu.committedOps 1819780127 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1725565901 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 805526 # Number of float alu accesses
system.cpu.num_func_calls 33534877 # number of times a function call or return occured
system.cpu.icache.sampled_refs 802 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2277278.937656 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 612.356766 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.299002 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1826377708 # number of ReadReq hits
-system.cpu.icache.demand_hits 1826377708 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1826377708 # number of overall hits
-system.cpu.icache.ReadReq_misses 802 # number of ReadReq misses
-system.cpu.icache.demand_misses 802 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 802 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 44912000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 44912000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 44912000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1826378510 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1826378510 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1826378510 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 612.356766 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.299002 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.299002 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1826377708 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1826377708 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 1826377708 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 1826377708 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 802 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 802 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 802 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 802 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 802 # number of overall misses
+system.cpu.icache.overall_misses::total 802 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 44912000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 44912000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 44912000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 44912000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 44912000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 44912000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1826378510 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.demand_accesses::total 1826378510 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1826378510 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1826378510 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses 802 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 802 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 802 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 42506000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 42506000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 42506000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9107638 # number of replacements
system.cpu.dcache.tagsinuse 4079.504248 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 9111734 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 65.433476 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 40989969000 # Cycle when the warmup percentage was hit.
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-system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513 # average ReadReq miss latency
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+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011755 # miss rate for WriteReq accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 7222414 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 1889320 # number of WriteReq MSHR misses
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-system.cpu.dcache.overall_mshr_misses 9111734 # number of overall MSHR misses
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-system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency 213473464000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.016245 # mshr miss rate for ReadReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate 0.015053 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000 # number of overall MSHR miss cycles
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+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513 # average ReadReq mshr miss latency
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+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2686269 # number of replacements
system.cpu.l2cache.tagsinuse 26040.087196 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 2710912 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.790701 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 582065656000 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 15312.508302 # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1 10727.578894 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.467301 # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1 0.327380 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 5415352 # number of ReadReq hits
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-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 10727.578894 # Average occupied blocks per requestor
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+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 1170923 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 1807864 # number of ReadReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses 2697097 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 72314560000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 35569320000 # number of ReadExReq MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.250285 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.470663 # mshr miss rate for ReadExReq accesses
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-system.cpu.l2cache.overall_mshr_miss_rate 0.295977 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.470663 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.295915 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
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+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:28:08
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 483300356500 # Number of ticks simulated
final_tick 483300356500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 96252 # Simulator instruction rate (inst/s)
-host_tick_rate 26997552 # Simulator tick rate (ticks/s)
-host_mem_usage 256412 # Number of bytes of host memory used
-host_seconds 17901.64 # Real time elapsed on the host
-sim_insts 1723073849 # Number of instructions simulated
+host_inst_rate 175200 # Simulator instruction rate (inst/s)
+host_op_rate 195449 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 54820940 # Simulator tick rate (ticks/s)
+host_mem_usage 223460 # Number of bytes of host memory used
+host_seconds 8815.98 # Real time elapsed on the host
+sim_insts 1544563036 # Number of instructions simulated
+sim_ops 1723073849 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 188191232 # Number of bytes read from this memory
system.physmem.bytes_inst_read 45952 # Number of instructions bytes read from this memory
system.physmem.bytes_written 77928320 # Number of bytes written to this memory
system.cpu.iew.wb_rate 2.025916 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.632400 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 1723073867 # The number of committed instructions
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system.cpu.commit.commitSquashedInsts 464107908 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 503 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 18315306 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 888130278 # Number of insts commited each cycle
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 660773817 # Number of memory references committed
system.cpu.commit.loads 485926771 # Number of loads committed
system.cpu.rob.rob_writes 4442782654 # The number of ROB writes
system.cpu.timesIdled 920078 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 10281556 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 1723073849 # Number of Instructions Simulated
-system.cpu.committedInsts_total 1723073849 # Number of Instructions Simulated
-system.cpu.cpi 0.560975 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.560975 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.782612 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.782612 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 1544563036 # Number of Instructions Simulated
+system.cpu.committedOps 1723073849 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 1544563036 # Number of Instructions Simulated
+system.cpu.cpi 0.625809 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.625809 # CPI: Total CPI of All Threads
+system.cpu.ipc 1.597933 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.597933 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 9941434858 # number of integer regfile reads
system.cpu.int_regfile_writes 1939754373 # number of integer regfile writes
system.cpu.fp_regfile_reads 96 # number of floating regfile reads
system.cpu.icache.sampled_refs 746 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 382141.180965 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 609.966952 # Average occupied blocks per context
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-system.cpu.icache.ReadReq_miss_latency 35270500 # number of ReadReq miss cycles
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-system.cpu.icache.ReadReq_avg_miss_latency 34646.856582 # average ReadReq miss latency
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-system.cpu.icache.overall_avg_miss_latency 34646.856582 # average overall miss latency
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu.dcache.tagsinuse 4087.729265 # Cycle average of tags in use
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system.cpu.dcache.blocked_cycles::no_mshrs 266779202 # number of cycles access was blocked
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system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.LoadLockedReq_mshr_hits 3 # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits 6061537 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 6061537 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 7682069 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 1892636 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 9574705 # number of demand (read+write) MSHR misses
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-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 92052400500 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.overall_mshr_miss_latency 137315641496 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.015065 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.010966 # mshr miss rate for WriteReq accesses
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-system.cpu.dcache.overall_mshr_miss_rate 0.014028 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11982.761480 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.449667 # average WriteReq mshr miss latency
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-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 2928111 # number of replacements
system.cpu.l2cache.tagsinuse 26779.513847 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 2955434 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 2.656349 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 102043879500 # Cycle when the warmup percentage was hit.
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-system.cpu.l2cache.overall_avg_miss_latency 34441.059154 # average overall miss latency
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+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951 # average ReadExReq miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 56425000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 6634 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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-system.cpu.l2cache.ReadReq_mshr_misses 2027959 # number of ReadReq MSHR misses
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-system.cpu.l2cache.overall_mshr_misses 2940488 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.671160 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31574.217367 # average ReadExReq mshr miss latency
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-system.cpu.l2cache.overall_avg_mshr_miss_latency 31306.249677 # average overall mshr miss latency
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+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:37:28
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:28:58
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 861538205000 # Number of ticks simulated
final_tick 861538205000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3027828 # Simulator instruction rate (inst/s)
-host_tick_rate 1513916118 # Simulator tick rate (ticks/s)
-host_mem_usage 210380 # Number of bytes of host memory used
-host_seconds 569.08 # Real time elapsed on the host
-sim_insts 1723073862 # Number of instructions simulated
+host_inst_rate 3097767 # Simulator instruction rate (inst/s)
+host_op_rate 3455787 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1727895925 # Simulator tick rate (ticks/s)
+host_mem_usage 212936 # Number of bytes of host memory used
+host_seconds 498.61 # Real time elapsed on the host
+sim_insts 1544563049 # Number of instructions simulated
+sim_ops 1723073862 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 7759650064 # Number of bytes read from this memory
system.physmem.bytes_inst_read 6178262392 # Number of instructions bytes read from this memory
system.physmem.bytes_written 624158392 # Number of bytes written to this memory
system.cpu.numCycles 1723076411 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1723073862 # Number of instructions executed
+system.cpu.committedInsts 1544563049 # Number of instructions committed
+system.cpu.committedOps 1723073862 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330134 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:45:39
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:33:49
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 2431419954000 # Number of ticks simulated
final_tick 2431419954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1410228 # Simulator instruction rate (inst/s)
-host_tick_rate 1996689457 # Simulator tick rate (ticks/s)
-host_mem_usage 219344 # Number of bytes of host memory used
-host_seconds 1217.73 # Real time elapsed on the host
-sim_insts 1717270343 # Number of instructions simulated
+host_inst_rate 1647360 # Simulator instruction rate (inst/s)
+host_op_rate 1838469 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2603021191 # Simulator tick rate (ticks/s)
+host_mem_usage 221840 # Number of bytes of host memory used
+host_seconds 934.08 # Real time elapsed on the host
+sim_insts 1538759609 # Number of instructions simulated
+sim_ops 1717270343 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 172766016 # Number of bytes read from this memory
system.physmem.bytes_inst_read 39424 # Number of instructions bytes read from this memory
system.physmem.bytes_written 75006720 # Number of bytes written to this memory
system.cpu.numCycles 4862839908 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 1717270343 # Number of instructions executed
+system.cpu.committedInsts 1538759609 # Number of instructions committed
+system.cpu.committedOps 1717270343 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 1536941850 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 36 # Number of float alu accesses
system.cpu.num_func_calls 27330134 # number of times a function call or return occured
system.cpu.icache.sampled_refs 638 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2420948.214734 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 514.872896 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.251403 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1544564961 # number of ReadReq hits
-system.cpu.icache.demand_hits 1544564961 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1544564961 # number of overall hits
-system.cpu.icache.ReadReq_misses 638 # number of ReadReq misses
-system.cpu.icache.demand_misses 638 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 638 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 34804000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 34804000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 34804000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1544565599 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1544565599 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1544565599 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54551.724138 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54551.724138 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54551.724138 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 514.872896 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.251403 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.251403 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1544564961 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1544564961 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1544564961 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1544564961 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1544564961 # number of overall hits
+system.cpu.icache.overall_hits::total 1544564961 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 638 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 638 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 638 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 638 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 638 # number of overall misses
+system.cpu.icache.overall_misses::total 638 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 34804000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 34804000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 34804000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 34804000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 34804000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 34804000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1544565599 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1544565599 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1544565599 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1544565599 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1544565599 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1544565599 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 638 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 638 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 638 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 32890000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 32890000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 32890000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 638 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 638 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 638 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 638 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 638 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 638 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 32890000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 32890000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 32890000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 32890000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 32890000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 32890000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 9111140 # number of replacements
system.cpu.dcache.tagsinuse 4083.719979 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 9115236 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 70.854453 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 25923025000 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 4083.719979 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.997002 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 475158040 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 170696898 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 61 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 61 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 645854938 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 645854938 # number of overall hits
-system.cpu.dcache.ReadReq_misses 7226087 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 1889149 # number of WriteReq misses
-system.cpu.dcache.demand_misses 9115236 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 9115236 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 177140908000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 63824222000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 240965130000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 240965130000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 482384127 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 172586047 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 61 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 61 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 654970174 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 654970174 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.014980 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.010946 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.013917 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.013917 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 26435.424162 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 26435.424162 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 4083.719979 # Average occupied blocks per requestor
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35596320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35596320000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24640000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.250335 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471063 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.965517 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.296082 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:13:31
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:34:58
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 2846007259500 # Number of ticks simulated
final_tick 2846007259500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2006575 # Simulator instruction rate (inst/s)
-host_tick_rate 1218454030 # Simulator tick rate (ticks/s)
-host_mem_usage 204704 # Number of bytes of host memory used
-host_seconds 2335.75 # Real time elapsed on the host
-sim_insts 4686862651 # Number of instructions simulated
+host_inst_rate 1815306 # Simulator instruction rate (inst/s)
+host_op_rate 2828411 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1717498350 # Simulator tick rate (ticks/s)
+host_mem_usage 210188 # Number of bytes of host memory used
+host_seconds 1657.07 # Real time elapsed on the host
+sim_insts 3008081057 # Number of instructions simulated
+sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 37129731755 # Number of bytes read from this memory
system.physmem.bytes_inst_read 32105863408 # Number of instructions bytes read from this memory
system.physmem.bytes_written 1544656790 # Number of bytes written to this memory
system.cpu.numCycles 5692014520 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 4686862651 # Number of instructions executed
+system.cpu.committedInsts 3008081057 # Number of instructions committed
+system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:30:19
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:48:34
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
spec_init
sim_ticks 5923548078000 # Number of ticks simulated
final_tick 5923548078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1176749 # Simulator instruction rate (inst/s)
-host_tick_rate 1487248019 # Simulator tick rate (ticks/s)
-host_mem_usage 213688 # Number of bytes of host memory used
-host_seconds 3982.89 # Real time elapsed on the host
-sim_insts 4686862651 # Number of instructions simulated
+host_inst_rate 1064786 # Simulator instruction rate (inst/s)
+host_op_rate 1659033 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2096788716 # Simulator tick rate (ticks/s)
+host_mem_usage 219100 # Number of bytes of host memory used
+host_seconds 2825.06 # Real time elapsed on the host
+sim_insts 3008081057 # Number of instructions simulated
+sim_ops 4686862651 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 173910080 # Number of bytes read from this memory
system.physmem.bytes_inst_read 43200 # Number of instructions bytes read from this memory
system.physmem.bytes_written 75176384 # Number of bytes written to this memory
system.cpu.numCycles 11847096156 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 4686862651 # Number of instructions executed
+system.cpu.committedInsts 3008081057 # Number of instructions committed
+system.cpu.committedOps 4686862651 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4686862580 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.icache.sampled_refs 675 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5945529.262222 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 555.713137 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.271344 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 4013232252 # number of ReadReq hits
-system.cpu.icache.demand_hits 4013232252 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 4013232252 # number of overall hits
-system.cpu.icache.ReadReq_misses 675 # number of ReadReq misses
-system.cpu.icache.demand_misses 675 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 675 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 37800000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 37800000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 37800000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 4013232927 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 4013232927 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 4013232927 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000000 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000000 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000000 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 555.713137 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.271344 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.271344 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 4013232252 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4013232252 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 4013232252 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 4013232252 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 4013232252 # number of overall hits
+system.cpu.icache.overall_hits::total 4013232252 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 675 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 675 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 675 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 675 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 675 # number of overall misses
+system.cpu.icache.overall_misses::total 675 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 37800000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 37800000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 37800000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 37800000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 37800000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 37800000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 4013232927 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 4013232927 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 4013232927 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 4013232927 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 4013232927 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 4013232927 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000000 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000000 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000000 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 675 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 675 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 675 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 35775000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 35775000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 35775000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000000 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000000 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000000 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 675 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 675 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 675 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 35775000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 35775000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 35775000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 35775000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 35775000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 35775000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000000 # mshr miss rate for overall accesses
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-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks 1174631 # number of writebacks
+system.cpu.l2cache.writebacks::total 1174631 # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 675 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1825920 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 1826595 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 890750 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 890750 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 675 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 2716670 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 2717345 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 675 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 2716670 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 2717345 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 27000000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 73036800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 73063800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 35630000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 35630000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 27000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 27000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.252798 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471339 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.298120 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:57:18
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:36:18
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 41833966000 # Number of ticks simulated
final_tick 41833966000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 111295 # Simulator instruction rate (inst/s)
-host_tick_rate 50660994 # Simulator tick rate (ticks/s)
-host_mem_usage 211656 # Number of bytes of host memory used
-host_seconds 825.76 # Real time elapsed on the host
+host_inst_rate 151560 # Simulator instruction rate (inst/s)
+host_op_rate 151560 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68989742 # Simulator tick rate (ticks/s)
+host_mem_usage 213560 # Number of bytes of host memory used
+host_seconds 606.38 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
+sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 316032 # Number of bytes read from this memory
system.physmem.bytes_inst_read 178816 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
-system.cpu.committedInsts 91903056 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 91903056 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.910393 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 0.910393 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 9436 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1057.621132 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1491.782957 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.728410 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 9979713 # number of ReadReq hits
-system.cpu.icache.demand_hits 9979713 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 9979713 # number of overall hits
-system.cpu.icache.ReadReq_misses 11486 # number of ReadReq misses
-system.cpu.icache.demand_misses 11486 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 11486 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 291407500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 291407500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 291407500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 9991199 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 9991199 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 9991199 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.001150 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.001150 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.001150 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 25370.668640 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 25370.668640 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 25370.668640 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1491.782957 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.728410 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.728410 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 9979713 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 9979713 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 9979713 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 9979713 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 9979713 # number of overall hits
+system.cpu.icache.overall_hits::total 9979713 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 11486 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 11486 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 11486 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 11486 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 11486 # number of overall misses
+system.cpu.icache.overall_misses::total 11486 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 291407500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 291407500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 291407500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 291407500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 291407500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 291407500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 9991199 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 9991199 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 9991199 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 9991199 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 9991199 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 9991199 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001150 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.001150 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.001150 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 69500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 17375 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 2050 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 2050 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 2050 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 9436 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 9436 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 9436 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 222700000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 222700000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 222700000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000944 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000944 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000944 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 2050 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 2050 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 2050 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 2050 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 2050 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 2050 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9436 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 9436 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 9436 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 9436 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 9436 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 9436 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 222700000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 222700000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 222700000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 222700000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 222700000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 222700000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000944 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1441.532122 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11916.871795 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 1441.532122 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.351937 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 19995645 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 6495561 # number of WriteReq hits
-system.cpu.dcache.demand_hits 26491206 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 26491206 # number of overall hits
-system.cpu.dcache.ReadReq_misses 553 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 5542 # number of WriteReq misses
-system.cpu.dcache.demand_misses 6095 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 6095 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 28393500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 303801000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 332194500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 332194500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000028 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.000852 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.000230 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.000230 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54502.789171 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54502.789171 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 1441.532122 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.351937 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.351937 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 19995645 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 19995645 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 6495561 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 6495561 # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data 26491206 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 26491206 # number of demand (read+write) hits
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.296100 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 06:08:28
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:45:24
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 29167093500 # Number of ticks simulated
final_tick 29167093500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 155660 # Simulator instruction rate (inst/s)
-host_tick_rate 53933893 # Simulator tick rate (ticks/s)
-host_mem_usage 212576 # Number of bytes of host memory used
-host_seconds 540.79 # Real time elapsed on the host
+host_inst_rate 198361 # Simulator instruction rate (inst/s)
+host_op_rate 198361 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68729352 # Simulator tick rate (ticks/s)
+host_mem_usage 214912 # Number of bytes of host memory used
+host_seconds 424.38 # Real time elapsed on the host
sim_insts 84179709 # Number of instructions simulated
+sim_ops 84179709 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 332416 # Number of bytes read from this memory
system.physmem.bytes_inst_read 193856 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.725137 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 91903055 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 91903055 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 40723267 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 389 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 1895854 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 52161479 # Number of insts commited each cycle
-system.cpu.commit.count 91903055 # Number of instructions committed
+system.cpu.commit.committedInsts 91903055 # Number of instructions committed
+system.cpu.commit.committedOps 91903055 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 26497301 # Number of memory references committed
system.cpu.commit.loads 19996198 # Number of loads committed
system.cpu.timesIdled 2277 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 93138 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 84179709 # Number of Instructions Simulated
+system.cpu.committedOps 84179709 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 84179709 # Number of Instructions Simulated
system.cpu.cpi 0.692972 # CPI: Cycles Per Instruction
system.cpu.cpi_total 0.692972 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 10628 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1749.359616 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1593.002324 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.777833 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 18592194 # number of ReadReq hits
-system.cpu.icache.demand_hits 18592194 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 18592194 # number of overall hits
-system.cpu.icache.ReadReq_misses 11853 # number of ReadReq misses
-system.cpu.icache.demand_misses 11853 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 11853 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 188036500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 188036500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 188036500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 18604047 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 18604047 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 18604047 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000637 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000637 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000637 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 15864.042858 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 15864.042858 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 15864.042858 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1593.002324 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.777833 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.777833 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 18592194 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 18592194 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 18592194 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 18592194 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 18592194 # number of overall hits
+system.cpu.icache.overall_hits::total 18592194 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 11853 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 11853 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 11853 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 11853 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 11853 # number of overall misses
+system.cpu.icache.overall_misses::total 11853 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 188036500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 188036500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 188036500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 188036500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 188036500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 188036500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 18604047 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 18604047 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 18604047 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 18604047 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 18604047 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 18604047 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000637 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000637 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000637 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 1225 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 1225 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 1225 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 10628 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 10628 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 10628 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 124769000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 124769000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 124769000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000571 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000571 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000571 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1225 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1225 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1225 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1225 # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total 1225 # number of overall MSHR hits
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+system.cpu.icache.ReadReq_mshr_misses::total 10628 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 10628 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 10628 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 10628 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 10628 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 124769000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 124769000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 124769000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 124769000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 124769000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 124769000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000571 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 159 # number of replacements
system.cpu.dcache.tagsinuse 1462.507461 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 2246 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13534.798753 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 1462.507461 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.357057 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 23906051 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 6493055 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 52 # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits 30399106 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 30399106 # number of overall hits
-system.cpu.dcache.ReadReq_misses 938 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 8048 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 1 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 8986 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 8986 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 28163500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 289889000 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 38000 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 318052500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 318052500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 23906989 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 53 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 30408092 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 30408092 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000039 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.001238 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.018868 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.000296 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.000296 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 38000 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35394.224349 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35394.224349 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 1462.507461 # Average occupied blocks per requestor
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+system.cpu.dcache.overall_hits::total 30399106 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 938 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 938 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 8048 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 8048 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 1 # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data 8986 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 8986 # number of demand (read+write) misses
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+system.cpu.dcache.overall_misses::total 8986 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 28163500 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 28163500 # number of ReadReq miss cycles
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-system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849 # average overall mshr miss latency
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system.cpu.l2cache.tagsinuse 2400.275766 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 3556 # Sample count of references to valid blocks.
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68173500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 162318000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 94144500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68173500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 162318000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.891262 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985557 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.285002 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963936 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 06:10:21
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:46:35
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 45951567500 # Number of ticks simulated
final_tick 45951567500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 4191883 # Simulator instruction rate (inst/s)
-host_tick_rate 2095941744 # Simulator tick rate (ticks/s)
-host_mem_usage 202544 # Number of bytes of host memory used
-host_seconds 21.92 # Real time elapsed on the host
+host_inst_rate 5286635 # Simulator instruction rate (inst/s)
+host_op_rate 5286630 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2643314521 # Simulator tick rate (ticks/s)
+host_mem_usage 204308 # Number of bytes of host memory used
+host_seconds 17.38 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
+sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 475949877 # Number of bytes read from this memory
system.physmem.bytes_inst_read 367612356 # Number of instructions bytes read from this memory
system.physmem.bytes_written 30920974 # Number of bytes written to this memory
system.cpu.numCycles 91903136 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 91903056 # Number of instructions executed
+system.cpu.committedInsts 91903056 # Number of instructions committed
+system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 06:10:54
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:47:03
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 118740049000 # Number of ticks simulated
final_tick 118740049000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2095418 # Simulator instruction rate (inst/s)
-host_tick_rate 2707308980 # Simulator tick rate (ticks/s)
-host_mem_usage 211256 # Number of bytes of host memory used
-host_seconds 43.86 # Real time elapsed on the host
+host_inst_rate 2598987 # Simulator instruction rate (inst/s)
+host_op_rate 2598985 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3357924345 # Simulator tick rate (ticks/s)
+host_mem_usage 213168 # Number of bytes of host memory used
+host_seconds 35.36 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
+sim_ops 91903056 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 304960 # Number of bytes read from this memory
system.physmem.bytes_inst_read 167744 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 237480098 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 91903056 # Number of instructions executed
+system.cpu.committedInsts 91903056 # Number of instructions committed
+system.cpu.committedOps 91903056 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 79581109 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6862064 # Number of float alu accesses
system.cpu.num_func_calls 2059216 # number of times a function call or return occured
system.cpu.icache.sampled_refs 8510 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10798.423032 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1418.037996 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.692401 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 91894580 # number of ReadReq hits
-system.cpu.icache.demand_hits 91894580 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 91894580 # number of overall hits
-system.cpu.icache.ReadReq_misses 8510 # number of ReadReq misses
-system.cpu.icache.demand_misses 8510 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 8510 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 229222000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 229222000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 229222000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 91903090 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 91903090 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 91903090 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000093 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000093 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000093 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 26935.605170 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 26935.605170 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 26935.605170 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1418.037996 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.692401 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.692401 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 91894580 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 91894580 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 91894580 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 91894580 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 91894580 # number of overall hits
+system.cpu.icache.overall_hits::total 91894580 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 8510 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 8510 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 8510 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 8510 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 8510 # number of overall misses
+system.cpu.icache.overall_misses::total 8510 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 229222000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 229222000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 229222000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 229222000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 229222000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 229222000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 91903090 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 91903090 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 91903090 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 91903090 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 91903090 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 91903090 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 8510 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 8510 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 8510 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 203692000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 203692000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 203692000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000093 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000093 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000093 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 8510 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 8510 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 8510 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 8510 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 8510 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 8510 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 203692000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 203692000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 203692000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 203692000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 203692000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 203692000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000093 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 157 # number of replacements
system.cpu.dcache.tagsinuse 1442.028823 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 11918.613585 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 1442.028823 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.352058 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 19995723 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 6499355 # number of WriteReq hits
-system.cpu.dcache.demand_hits 26495078 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 26495078 # number of overall hits
-system.cpu.dcache.ReadReq_misses 475 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 1748 # number of WriteReq misses
-system.cpu.dcache.demand_misses 2223 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 2223 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 24374000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 96796000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 121170000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 121170000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 19996198 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 6501103 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 26497301 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 26497301 # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.985126 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.307991 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:37:09
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 105850842000 # Number of ticks simulated
final_tick 105850842000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46914 # Simulator instruction rate (inst/s)
-host_tick_rate 26320721 # Simulator tick rate (ticks/s)
-host_mem_usage 259812 # Number of bytes of host memory used
-host_seconds 4021.58 # Real time elapsed on the host
-sim_insts 188667627 # Number of instructions simulated
+host_inst_rate 122767 # Simulator instruction rate (inst/s)
+host_op_rate 134419 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 75414821 # Simulator tick rate (ticks/s)
+host_mem_usage 227032 # Number of bytes of host memory used
+host_seconds 1403.58 # Real time elapsed on the host
+sim_insts 172314144 # Number of instructions simulated
+sim_ops 188667627 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 239936 # Number of bytes read from this memory
system.physmem.bytes_inst_read 128320 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.155893 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.599323 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 188682015 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 172328532 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 188682015 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 146244510 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1636018 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 9791900 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 188552607 # Number of insts commited each cycle
-system.cpu.commit.count 188682015 # Number of instructions committed
+system.cpu.commit.committedInsts 172328532 # Number of instructions committed
+system.cpu.commit.committedOps 188682015 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 42498565 # Number of memory references committed
system.cpu.commit.loads 29851708 # Number of loads committed
system.cpu.rob.rob_writes 693007050 # The number of ROB writes
system.cpu.timesIdled 1719 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 58483 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 188667627 # Number of Instructions Simulated
-system.cpu.committedInsts_total 188667627 # Number of Instructions Simulated
-system.cpu.cpi 1.122088 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.122088 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.891196 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.891196 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 172314144 # Number of Instructions Simulated
+system.cpu.committedOps 188667627 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 172314144 # Number of Instructions Simulated
+system.cpu.cpi 1.228580 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.228580 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.813948 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.813948 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 1111988877 # number of integer regfile reads
system.cpu.int_regfile_writes 407368356 # number of integer regfile writes
system.cpu.fp_regfile_reads 2928539 # number of floating regfile reads
system.cpu.icache.sampled_refs 3640 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 11158.088187 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1329.301324 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.649073 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 40615441 # number of ReadReq hits
-system.cpu.icache.demand_hits 40615441 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 40615441 # number of overall hits
-system.cpu.icache.ReadReq_misses 4234 # number of ReadReq misses
-system.cpu.icache.demand_misses 4234 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 4234 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 101275500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 101275500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 101275500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 40619675 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 40619675 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 40619675 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000104 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000104 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000104 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23919.579594 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23919.579594 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23919.579594 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1329.301324 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.649073 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.649073 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 40615441 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 40615441 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 40615441 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 40615441 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 40615441 # number of overall hits
+system.cpu.icache.overall_hits::total 40615441 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4234 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4234 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4234 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4234 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 4234 # number of overall misses
+system.cpu.icache.overall_misses::total 4234 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 101275500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 101275500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 101275500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 101275500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 101275500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 101275500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 40619675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 40619675 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 40619675 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 40619675 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 40619675 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 40619675 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000104 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000104 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000104 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 594 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 594 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 594 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 3640 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 3640 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 3640 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 74572500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 74572500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 74572500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000090 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000090 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000090 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 594 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 594 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 594 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 594 # number of demand (read+write) MSHR hits
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+system.cpu.icache.overall_mshr_hits::total 594 # number of overall MSHR hits
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+system.cpu.icache.demand_mshr_misses::total 3640 # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total 3640 # number of overall MSHR misses
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+system.cpu.icache.ReadReq_mshr_miss_latency::total 74572500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 74572500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 74572500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 74572500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 74572500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000090 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 53 # number of replacements
system.cpu.dcache.tagsinuse 1403.723956 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1846 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 26350.862947 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 1403.723956 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.342706 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 36234545 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 12356727 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits 27791 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits 24630 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 48591272 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 48591272 # number of overall hits
-system.cpu.dcache.ReadReq_misses 1808 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 7560 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses 2 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses 9368 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 9368 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 59529000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 237156500 # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency 63500 # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency 296685500 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 296685500 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 36236353 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 12364287 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses 27793 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses 24630 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 48600640 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 48600640 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.000050 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.000611 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate 0.000072 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate 0.000193 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.000193 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407 # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 31750 # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 31670.100342 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 31670.100342 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 1403.723956 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.342706 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.342706 # Average percentage of cache occupancy
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+system.cpu.dcache.LoadLockedReq_hits::total 27791 # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 24630 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total 24630 # number of StoreCondReq hits
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+system.cpu.dcache.ReadReq_misses::cpu.data 1808 # number of ReadReq misses
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+system.cpu.dcache.WriteReq_misses::total 7560 # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses
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+system.cpu.dcache.overall_misses::total 9368 # number of overall misses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 20643500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 82895000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33590000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33590000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 62251500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 54233500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 116485000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 62251500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 54233500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 116485000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.876821 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991751 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.550824 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.944745 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:50:48
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:37:27
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 103106771000 # Number of ticks simulated
final_tick 103106771000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3006793 # Simulator instruction rate (inst/s)
-host_tick_rate 1643182108 # Simulator tick rate (ticks/s)
-host_mem_usage 213456 # Number of bytes of host memory used
-host_seconds 62.75 # Real time elapsed on the host
-sim_insts 188670900 # Number of instructions simulated
+host_inst_rate 3118510 # Simulator instruction rate (inst/s)
+host_op_rate 3414466 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1865971013 # Simulator tick rate (ticks/s)
+host_mem_usage 216012 # Number of bytes of host memory used
+host_seconds 55.26 # Real time elapsed on the host
+sim_insts 172317417 # Number of instructions simulated
+sim_ops 188670900 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 869973902 # Number of bytes read from this memory
system.physmem.bytes_inst_read 759440240 # Number of instructions bytes read from this memory
system.physmem.bytes_written 45252940 # Number of bytes written to this memory
system.cpu.numCycles 206213543 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 188670900 # Number of instructions executed
+system.cpu.committedInsts 172317417 # Number of instructions committed
+system.cpu.committedOps 188670900 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:52:01
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:38:33
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 232077154000 # Number of ticks simulated
final_tick 232077154000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1497030 # Simulator instruction rate (inst/s)
-host_tick_rate 1846187485 # Simulator tick rate (ticks/s)
-host_mem_usage 222460 # Number of bytes of host memory used
-host_seconds 125.71 # Real time elapsed on the host
-sim_insts 188185929 # Number of instructions simulated
+host_inst_rate 1867609 # Simulator instruction rate (inst/s)
+host_op_rate 2045232 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2522247357 # Simulator tick rate (ticks/s)
+host_mem_usage 224952 # Number of bytes of host memory used
+host_seconds 92.01 # Real time elapsed on the host
+sim_insts 171842491 # Number of instructions simulated
+sim_ops 188185929 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 220992 # Number of bytes read from this memory
system.physmem.bytes_inst_read 110656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 464154308 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 188185929 # Number of instructions executed
+system.cpu.committedInsts 171842491 # Number of instructions committed
+system.cpu.committedOps 188185929 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 150106226 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses
system.cpu.num_func_calls 3504894 # number of times a function call or return occured
system.cpu.icache.sampled_refs 3051 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 62227.797443 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1147.981155 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.560538 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 189857010 # number of ReadReq hits
-system.cpu.icache.demand_hits 189857010 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 189857010 # number of overall hits
-system.cpu.icache.ReadReq_misses 3051 # number of ReadReq misses
-system.cpu.icache.demand_misses 3051 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 3051 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 115332000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 115332000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 115332000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 189860061 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 189860061 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 189860061 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000016 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000016 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000016 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 37801.376598 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 37801.376598 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 37801.376598 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1147.981155 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.560538 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.560538 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 189857010 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 189857010 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 189857010 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 189857010 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 189857010 # number of overall hits
+system.cpu.icache.overall_hits::total 189857010 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 3051 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 3051 # number of overall misses
+system.cpu.icache.overall_misses::total 3051 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 115332000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 115332000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 115332000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 115332000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 115332000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 115332000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 189860061 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 189860061 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 189860061 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 189860061 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 189860061 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 189860061 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000016 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 3051 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 3051 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 3051 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 106179000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 106179000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 106179000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000016 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000016 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000016 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3051 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 3051 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 3051 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 3051 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 3051 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 3051 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 106179000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 106179000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 106179000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 106179000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 106179000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 106179000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000016 # mshr miss rate for demand accesses
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-system.cpu.l2cache.demand_mshr_miss_latency 138120000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 138120000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.631283 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.992727 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.713430 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.713430 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 1729 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 632 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 2361 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1092 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1092 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 1729 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1724 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 3453 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 1729 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1724 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 3453 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 69160000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 94440000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43680000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 69160000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 68960000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 138120000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 69160000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 68960000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 138120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.917271 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.992727 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.566699 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.963667 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:25:10
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:01:49
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
-Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav
-Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 96722951500 # Number of ticks simulated
final_tick 96722951500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3381365 # Simulator instruction rate (inst/s)
-host_tick_rate 1690691780 # Simulator tick rate (ticks/s)
-host_mem_usage 210080 # Number of bytes of host memory used
-host_seconds 57.21 # Real time elapsed on the host
-sim_insts 193444769 # Number of instructions simulated
+host_inst_rate 4190258 # Simulator instruction rate (inst/s)
+host_op_rate 4190262 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2095142285 # Simulator tick rate (ticks/s)
+host_mem_usage 207744 # Number of bytes of host memory used
+host_seconds 46.17 # Real time elapsed on the host
+sim_insts 193444531 # Number of instructions simulated
+sim_ops 193444769 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 997245606 # Number of bytes read from this memory
system.physmem.bytes_inst_read 773782192 # Number of instructions bytes read from this memory
system.physmem.bytes_written 72065412 # Number of bytes written to this memory
system.cpu.numCycles 193445904 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 193444769 # Number of instructions executed
+system.cpu.committedInsts 193444531 # Number of instructions committed
+system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
egid=100
env=
errout=cerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:26:18
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:02:21
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 270576960000 # Number of ticks simulated
final_tick 270576960000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1675606 # Simulator instruction rate (inst/s)
-host_tick_rate 2343719954 # Simulator tick rate (ticks/s)
-host_mem_usage 218792 # Number of bytes of host memory used
-host_seconds 115.45 # Real time elapsed on the host
-sim_insts 193444769 # Number of instructions simulated
+host_inst_rate 2083715 # Simulator instruction rate (inst/s)
+host_op_rate 2083717 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2914556895 # Simulator tick rate (ticks/s)
+host_mem_usage 216616 # Number of bytes of host memory used
+host_seconds 92.84 # Real time elapsed on the host
+sim_insts 193444531 # Number of instructions simulated
+sim_ops 193444769 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 331072 # Number of bytes read from this memory
system.physmem.bytes_inst_read 230208 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 541153920 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 193444769 # Number of instructions executed
+system.cpu.committedInsts 193444531 # Number of instructions committed
+system.cpu.committedOps 193444769 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 167974818 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 1970372 # Number of float alu accesses
system.cpu.num_func_calls 1957920 # number of times a function call or return occured
system.cpu.icache.sampled_refs 12288 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 15741.639079 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1591.571713 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.777135 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 193433261 # number of ReadReq hits
-system.cpu.icache.demand_hits 193433261 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 193433261 # number of overall hits
-system.cpu.icache.ReadReq_misses 12288 # number of ReadReq misses
-system.cpu.icache.demand_misses 12288 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 12288 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 323106000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 323106000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 323106000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 193445549 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 193445549 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 193445549 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000064 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000064 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000064 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 26294.433594 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 26294.433594 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1591.571713 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.777135 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.777135 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 193433261 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 193433261 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 193433261 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 193433261 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 193433261 # number of overall hits
+system.cpu.icache.overall_hits::total 193433261 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 12288 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 12288 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 12288 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 12288 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 12288 # number of overall misses
+system.cpu.icache.overall_misses::total 12288 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 323106000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 323106000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 323106000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 323106000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 323106000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 323106000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 193445549 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 193445549 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 193445549 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 193445549 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 193445549 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 193445549 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000064 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000064 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000064 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 12288 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 12288 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 12288 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 286242000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 286242000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 286242000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000064 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000064 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000064 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 12288 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 12288 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 12288 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 12288 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 12288 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 12288 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 286242000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 286242000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 286242000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 286242000 # number of demand (read+write) MSHR miss cycles
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-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 4095 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 1078 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 5173 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 5173 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 163800000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 206920000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 206920000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.320272 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.373125 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.373125 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3597 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 498 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 4095 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1078 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1078 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3597 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1576 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5173 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3597 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1576 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5173 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 143880000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 19920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 163800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 43120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 43120000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 143880000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 63040000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 206920000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 143880000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 63040000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 206920000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.292725 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
egid=100
env=
errout=cerr
euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 9 2012 12:45:55
-gem5 started Feb 9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:02:46
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 96266258000 # Number of ticks simulated
final_tick 96266258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 60515 # Simulator instruction rate (inst/s)
-host_tick_rate 26316743 # Simulator tick rate (ticks/s)
-host_mem_usage 262352 # Number of bytes of host memory used
-host_seconds 3657.99 # Real time elapsed on the host
-sim_insts 221363017 # Number of instructions simulated
+host_inst_rate 89516 # Simulator instruction rate (inst/s)
+host_op_rate 150037 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 65247901 # Simulator tick rate (ticks/s)
+host_mem_usage 229524 # Number of bytes of host memory used
+host_seconds 1475.39 # Real time elapsed on the host
+sim_insts 132071227 # Number of instructions simulated
+sim_ops 221363017 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 339712 # Number of bytes read from this memory
system.physmem.bytes_inst_read 214912 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_rate 1.457634 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.601730 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 221363017 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 132071227 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 221363017 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 174222633 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 1246 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 2892920 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 168869292 # Number of insts commited each cycle
-system.cpu.commit.count 221363017 # Number of instructions committed
+system.cpu.commit.committedInsts 132071227 # Number of instructions committed
+system.cpu.commit.committedOps 221363017 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 77165306 # Number of memory references committed
system.cpu.commit.loads 56649590 # Number of loads committed
system.cpu.rob.rob_writes 814800236 # The number of ROB writes
system.cpu.timesIdled 1747 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 80351 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 221363017 # Number of Instructions Simulated
-system.cpu.committedInsts_total 221363017 # Number of Instructions Simulated
-system.cpu.cpi 0.869759 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 0.869759 # CPI: Total CPI of All Threads
-system.cpu.ipc 1.149744 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 1.149744 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 132071227 # Number of Instructions Simulated
+system.cpu.committedOps 221363017 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 132071227 # Number of Instructions Simulated
+system.cpu.cpi 1.457793 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.457793 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.685968 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.685968 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 530367480 # number of integer regfile reads
system.cpu.int_regfile_writes 288604591 # number of integer regfile writes
system.cpu.fp_regfile_reads 3608788 # number of floating regfile reads
system.cpu.icache.sampled_refs 6167 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4662.101832 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1597.649860 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.780102 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 28751182 # number of ReadReq hits
-system.cpu.icache.demand_hits 28751182 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 28751182 # number of overall hits
-system.cpu.icache.ReadReq_misses 7479 # number of ReadReq misses
-system.cpu.icache.demand_misses 7479 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 7479 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 173725000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 173725000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 173725000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 28758661 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 28758661 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 28758661 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000260 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000260 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000260 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23228.372777 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23228.372777 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23228.372777 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1597.649860 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.780102 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.780102 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 28751182 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 28751182 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 28751182 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 28751182 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 28751182 # number of overall hits
+system.cpu.icache.overall_hits::total 28751182 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 7479 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 7479 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 7479 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 7479 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 7479 # number of overall misses
+system.cpu.icache.overall_misses::total 7479 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 173725000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 173725000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 173725000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 173725000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 173725000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 173725000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 28758661 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 28758661 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 28758661 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 28758661 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 28758661 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 28758661 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000260 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000260 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000260 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 1119 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 1119 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 1119 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 6360 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 6360 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 6360 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 125233500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 125233500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 125233500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.000221 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.000221 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.000221 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1119 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 1119 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 1119 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 1119 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 1119 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 1119 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 6360 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 6360 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 6360 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 6360 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 6360 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 6360 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 125233500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 125233500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 125233500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 125233500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 125233500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 125233500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000221 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 56 # number of replacements
system.cpu.dcache.tagsinuse 1415.486536 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1987 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 36707.686462 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 1415.486536 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.345578 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 52423955 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 20513973 # number of WriteReq hits
-system.cpu.dcache.demand_hits 72937928 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 72937928 # number of overall hits
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-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.994882 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.650809 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.650809 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.784972 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31000 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.462698 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 3358 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 395 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3753 # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 193 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total 193 # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1555 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1555 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 3358 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1950 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 5308 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 3358 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1950 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 5308 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 104175500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12238000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 116413500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 5983000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 5983000 # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 48232500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 48232500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 104175500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 60470500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 164646000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 104175500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 60470500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 164646000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.927230 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.994882 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.544511 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980392 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31000 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 08:24:02
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:27:33
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 131393100000 # Number of ticks simulated
final_tick 131393100000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1953897 # Simulator instruction rate (inst/s)
-host_tick_rate 1159762651 # Simulator tick rate (ticks/s)
-host_mem_usage 211876 # Number of bytes of host memory used
-host_seconds 113.29 # Real time elapsed on the host
-sim_insts 221363018 # Number of instructions simulated
+host_inst_rate 1741959 # Simulator instruction rate (inst/s)
+host_op_rate 2919677 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1733014386 # Simulator tick rate (ticks/s)
+host_mem_usage 217356 # Number of bytes of host memory used
+host_seconds 75.82 # Real time elapsed on the host
+sim_insts 132071228 # Number of instructions simulated
+sim_ops 221363018 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 1698379042 # Number of bytes read from this memory
system.physmem.bytes_inst_read 1387955288 # Number of instructions bytes read from this memory
system.physmem.bytes_written 99822189 # Number of bytes written to this memory
system.cpu.numCycles 262786201 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 221363018 # Number of instructions executed
+system.cpu.committedInsts 132071228 # Number of instructions committed
+system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
egid=100
env=
errout=cerr
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 08:26:06
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:28:59
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 250960631000 # Number of ticks simulated
final_tick 250960631000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1263573 # Simulator instruction rate (inst/s)
-host_tick_rate 1432520595 # Simulator tick rate (ticks/s)
-host_mem_usage 220856 # Number of bytes of host memory used
-host_seconds 175.19 # Real time elapsed on the host
-sim_insts 221363018 # Number of instructions simulated
+host_inst_rate 1043901 # Simulator instruction rate (inst/s)
+host_op_rate 1749670 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1983612036 # Simulator tick rate (ticks/s)
+host_mem_usage 226268 # Number of bytes of host memory used
+host_seconds 126.52 # Real time elapsed on the host
+sim_insts 132071228 # Number of instructions simulated
+sim_ops 221363018 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 303040 # Number of bytes read from this memory
system.physmem.bytes_inst_read 181760 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 501921262 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 221363018 # Number of instructions executed
+system.cpu.committedInsts 132071228 # Number of instructions committed
+system.cpu.committedOps 221363018 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 220339607 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2162459 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.icache.sampled_refs 4694 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 36959.888794 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 1455.289108 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.710590 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 173489718 # number of ReadReq hits
-system.cpu.icache.demand_hits 173489718 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 173489718 # number of overall hits
-system.cpu.icache.ReadReq_misses 4694 # number of ReadReq misses
-system.cpu.icache.demand_misses 4694 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 4694 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 185041500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 185041500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 185041500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 173494412 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 173494412 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 173494412 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.000027 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.000027 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.000027 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 39420.856412 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 39420.856412 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 39420.856412 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 1455.289108 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.710590 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.710590 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 173489718 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 173489718 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 173489718 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 173489718 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 173489718 # number of overall hits
+system.cpu.icache.overall_hits::total 173489718 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 4694 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 4694 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 4694 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 4694 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 4694 # number of overall misses
+system.cpu.icache.overall_misses::total 4694 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 185041500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 185041500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 185041500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 185041500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 185041500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 185041500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 173494412 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 173494412 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 173494412 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 173494412 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 173494412 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 173494412 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000027 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.000027 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.000027 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412 # average overall miss latency
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+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.998099 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.605028 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.994751 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.605028 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.994751 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 3160 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 1575 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 4735 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 4735 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 126400000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 63000000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 189400000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 189400000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.629357 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 0.998099 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.717533 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.717533 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2840 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 320 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 3160 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1575 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 1575 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 2840 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 1895 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 4735 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 2840 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 1895 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 4735 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 113600000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 12800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 126400000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 63000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 63000000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 113600000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 75800000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 189400000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 113600000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 75800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 189400000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.978593 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.998099 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.605028 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.994751 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
system=system
tracer=system.cpu0.tracer
width=1
+workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
system=system
tracer=system.cpu1.tracer
width=1
+workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[1]
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848432
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848304
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848569
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848451
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848515
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848579
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848643
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848707
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848771
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848835
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848899
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615850617
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848891
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848816
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848696
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848936
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848680
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848944
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
-platform=system.tsunami
system=system
pio=system.iobus.port[22]
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
-platform=system.tsunami
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[2]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:39
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 97861500
sim_ticks 1870335522500 # Number of ticks simulated
final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3272042 # Simulator instruction rate (inst/s)
-host_tick_rate 96902915749 # Simulator tick rate (ticks/s)
-host_mem_usage 296264 # Number of bytes of host memory used
-host_seconds 19.30 # Real time elapsed on the host
+host_inst_rate 4204751 # Simulator instruction rate (inst/s)
+host_op_rate 4204746 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 124525337361 # Simulator tick rate (ticks/s)
+host_mem_usage 293604 # Number of bytes of host memory used
+host_seconds 15.02 # Real time elapsed on the host
sim_insts 63154034 # Number of instructions simulated
+sim_ops 63154034 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 72297472 # Number of bytes read from this memory
system.physmem.bytes_inst_read 995008 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10452352 # Number of bytes written to this memory
system.l2c.sampled_refs 1087985 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.151871 # Average number of references to valid blocks.
system.l2c.warmup_cycle 990121000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10019.673951 # Average occupied blocks per context
-system.l2c.occ_blocks::1 266.115685 # Average occupied blocks per context
-system.l2c.occ_blocks::2 23831.931773 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.152888 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.004061 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.363646 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1620505 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 137130 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 23831.931773 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 3683.485712 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 6336.188239 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 152.381317 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 113.734368 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.363646 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.056206 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.096683 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.002325 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.001735 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.520595 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 871618 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 748887 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 101445 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 35685 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1757635 # number of ReadReq hits
-system.l2c.Writeback_hits::0 811846 # number of Writeback hits
+system.l2c.Writeback_hits::writebacks 811846 # number of Writeback hits
system.l2c.Writeback_hits::total 811846 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 134 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 39 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data 134 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 39 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 173 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 15 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 9 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 15 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 24 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 164417 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 14126 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data 164417 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data 14126 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 178543 # number of ReadExReq hits
-system.l2c.demand_hits::0 1784922 # number of demand (read+write) hits
-system.l2c.demand_hits::1 151256 # number of demand (read+write) hits
-system.l2c.demand_hits::2 0 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst 871618 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data 913304 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst 101445 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data 49811 # number of demand (read+write) hits
system.l2c.demand_hits::total 1936178 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1784922 # number of overall hits
-system.l2c.overall_hits::1 151256 # number of overall hits
-system.l2c.overall_hits::2 0 # number of overall hits
+system.l2c.overall_hits::cpu0.inst 871618 # number of overall hits
+system.l2c.overall_hits::cpu0.data 913304 # number of overall hits
+system.l2c.overall_hits::cpu1.inst 101445 # number of overall hits
+system.l2c.overall_hits::cpu1.data 49811 # number of overall hits
system.l2c.overall_hits::total 1936178 # number of overall hits
-system.l2c.ReadReq_misses::0 956917 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 4511 # number of ReadReq misses
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system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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-system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks 15 # number of writebacks
+system.cpu1.icache.writebacks::total 15 # number of writebacks
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 62338 # number of replacements
system.cpu1.dcache.tagsinuse 391.951263 # Cycle average of tags in use
system.cpu1.dcache.sampled_refs 62657 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 29.279155 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1851267520500 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 391.951263 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.765530 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 1109315 # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data 391.951263 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.765530 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.765530 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 1109315 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1109315 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 707444 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 707444 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 707444 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 15129 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 15129 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 15129 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 15613 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 15613 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 15613 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 1816759 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data 1816759 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 1816759 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 1816759 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data 1816759 # number of overall hits
system.cpu1.dcache.overall_hits::total 1816759 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 41650 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data 41650 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 41650 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 25861 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 25861 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 25861 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 1289 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 1289 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 1289 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 732 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 732 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 732 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 67511 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data 67511 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 67511 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 67511 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data 67511 # number of overall misses
system.cpu1.dcache.overall_misses::total 67511 # number of overall misses
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 1150965 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1150965 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1150965 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 733305 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 733305 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 733305 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 16418 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 16418 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 16418 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 16345 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 16345 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 16345 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 1884270 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1884270 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 1884270 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1884270 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.036187 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.035266 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.078511 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.044784 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.035829 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.035829 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.036187 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.035266 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.078511 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.044784 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.035829 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.035829 # miss rate for overall accesses
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 39996 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 39996 # number of writebacks
+system.cpu1.dcache.writebacks::total 39996 # number of writebacks
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
system=system
tracer=system.cpu.tracer
width=1
+workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[1]
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848432
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848304
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848569
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848451
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848515
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848579
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848643
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848707
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848771
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848835
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848899
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615850617
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848891
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848816
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848696
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848936
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848680
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848944
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
-platform=system.tsunami
system=system
pio=system.iobus.port[22]
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
-platform=system.tsunami
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[2]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:39
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1829332258000 because m5_exit instruction encountered
sim_ticks 1829332258000 # Number of ticks simulated
final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 3300922 # Simulator instruction rate (inst/s)
-host_tick_rate 100577077281 # Simulator tick rate (ticks/s)
-host_mem_usage 294216 # Number of bytes of host memory used
-host_seconds 18.19 # Real time elapsed on the host
+host_inst_rate 4111639 # Simulator instruction rate (inst/s)
+host_op_rate 4111633 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 125278906724 # Simulator tick rate (ticks/s)
+host_mem_usage 291412 # Number of bytes of host memory used
+host_seconds 14.60 # Real time elapsed on the host
sim_insts 60038305 # Number of instructions simulated
+sim_ops 60038305 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 71650816 # Number of bytes read from this memory
system.physmem.bytes_inst_read 955904 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10156864 # Number of bytes written to this memory
system.l2c.sampled_refs 1077848 # Sample count of references to valid blocks.
system.l2c.avg_refs 2.126306 # Average number of references to valid blocks.
system.l2c.warmup_cycle 765422500 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10193.605493 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23613.410409 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.155542 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.360312 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1699395 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 23613.410409 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 3680.391656 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 6513.213838 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.360312 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.056158 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.099384 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.515854 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst 905267 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 794128 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1699395 # number of ReadReq hits
-system.l2c.Writeback_hits::0 825291 # number of Writeback hits
+system.l2c.Writeback_hits::writebacks 825291 # number of Writeback hits
system.l2c.Writeback_hits::total 825291 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 1 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 185383 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data 185383 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 185383 # number of ReadExReq hits
-system.l2c.demand_hits::0 1884778 # number of demand (read+write) hits
-system.l2c.demand_hits::1 0 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst 905267 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 979511 # number of demand (read+write) hits
system.l2c.demand_hits::total 1884778 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1884778 # number of overall hits
-system.l2c.overall_hits::1 0 # number of overall hits
+system.l2c.overall_hits::cpu.inst 905267 # number of overall hits
+system.l2c.overall_hits::cpu.data 979511 # number of overall hits
system.l2c.overall_hits::total 1884778 # number of overall hits
-system.l2c.ReadReq_misses::0 959629 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 14936 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 944693 # number of ReadReq misses
system.l2c.ReadReq_misses::total 959629 # number of ReadReq misses
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system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
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-system.cpu.dcache.occ_percent::0 0.999996 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 7807782 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 511.997802 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999996 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 7807782 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 7807782 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 5848212 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 5848212 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 5848212 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 183141 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 183141 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 183141 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 199282 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 199282 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 199282 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 13655994 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 13655994 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 13655994 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 13655994 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 13655994 # number of overall hits
system.cpu.dcache.overall_hits::total 13655994 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 1721705 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 1721705 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1721705 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 304362 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 304362 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 304362 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 17162 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 17162 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 17162 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0 2026067 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data 2026067 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 2026067 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 2026067 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data 2026067 # number of overall misses
system.cpu.dcache.overall_misses::total 2026067 # number of overall misses
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 9529487 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 9529487 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 9529487 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 6152574 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 6152574 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 6152574 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 200303 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 200303 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 200303 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 199282 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 199282 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 199282 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 15682061 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 15682061 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 15682061 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 15682061 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 15682061 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 15682061 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.180671 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.049469 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.085680 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.129196 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.129196 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.180671 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049469 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.085680 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.129196 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.129196 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 825183 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 825183 # number of writebacks
+system.cpu.dcache.writebacks::total 825183 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
progress_interval=0
system=system
tracer=system.cpu0.tracer
+workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
progress_interval=0
system=system
tracer=system.cpu1.tracer
+workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[1]
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848432
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848304
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848569
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848451
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848515
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848579
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848643
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848707
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848771
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848835
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848899
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615850617
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848891
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848816
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848696
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848936
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848680
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848944
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
-platform=system.tsunami
system=system
pio=system.iobus.port[22]
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
-platform=system.tsunami
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[2]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:23:09
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:02
gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 562628000
sim_ticks 1958647095000 # Number of ticks simulated
final_tick 1958647095000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1643366 # Simulator instruction rate (inst/s)
-host_tick_rate 54228566310 # Simulator tick rate (ticks/s)
-host_mem_usage 293036 # Number of bytes of host memory used
-host_seconds 36.12 # Real time elapsed on the host
+host_inst_rate 1989502 # Simulator instruction rate (inst/s)
+host_op_rate 1989500 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 65650485361 # Simulator tick rate (ticks/s)
+host_mem_usage 290388 # Number of bytes of host memory used
+host_seconds 29.83 # Real time elapsed on the host
sim_insts 59355643 # Number of instructions simulated
+sim_ops 59355643 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30050624 # Number of bytes read from this memory
system.physmem.bytes_inst_read 971200 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10333120 # Number of bytes written to this memory
system.l2c.sampled_refs 427769 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.543761 # Average number of references to valid blocks.
system.l2c.warmup_cycle 10882116000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 10867.929163 # Average occupied blocks per context
-system.l2c.occ_blocks::1 199.983935 # Average occupied blocks per context
-system.l2c.occ_blocks::2 23419.887612 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.165831 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.003052 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.357359 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1659395 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 119191 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 23419.887612 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst 3728.336055 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data 7139.593108 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst 100.838318 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data 99.145617 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.357359 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst 0.056890 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data 0.108942 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst 0.001539 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data 0.001513 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.526242 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst 901389 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data 758006 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst 86187 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data 33004 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1778586 # number of ReadReq hits
-system.l2c.Writeback_hits::0 816294 # number of Writeback hits
+system.l2c.Writeback_hits::writebacks 816294 # number of Writeback hits
system.l2c.Writeback_hits::total 816294 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 172 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 53 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data 172 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data 53 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 225 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 18 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 19 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data 18 # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data 19 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 37 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 170288 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 12569 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data 170288 # number of ReadExReq hits
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.numCycles 3916023774 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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-system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.122512 # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.049821 # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.085698 # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.002134 # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.092785 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.092785 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 7251.219512 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 786441 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 1036101 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 291536 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 16544 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses 410 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses 1327637 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 1327637 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 23461938500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency 8235346000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 185317000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 1743000 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency 31697284500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 31697284500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 884470000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1242107000 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 2126577000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.122512 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.049821 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.085698 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.002134 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0 0.092785 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0 0.092785 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 4251.219512 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks 786441 # number of writebacks
+system.cpu0.dcache.writebacks::total 786441 # number of writebacks
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+system.cpu0.dcache.WriteReq_mshr_misses::total 291536 # number of WriteReq MSHR misses
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+system.cpu0.dcache.demand_mshr_miss_latency::total 31697284500 # number of demand (read+write) MSHR miss cycles
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+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168 # average ReadReq mshr miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4251.219512 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
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+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.numCycles 3917294190 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 5282991 # Number of instructions executed
+system.cpu1.committedInsts 5282991 # Number of instructions committed
+system.cpu1.committedOps 5282991 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 4948310 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 34031 # Number of float alu accesses
system.cpu1.num_func_calls 158031 # number of times a function call or return occured
system.cpu1.icache.sampled_refs 86969 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 59.783935 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 1942711132000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 419.807616 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.819937 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0 5199349 # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst 419.807616 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.819937 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.819937 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 5199349 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 5199349 # number of ReadReq hits
-system.cpu1.icache.demand_hits::0 5199349 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
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system.cpu1.icache.demand_hits::total 5199349 # number of demand (read+write) hits
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system.cpu1.icache.overall_hits::total 5199349 # number of overall hits
-system.cpu1.icache.ReadReq_misses::0 87005 # number of ReadReq misses
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system.cpu1.icache.ReadReq_misses::total 87005 # number of ReadReq misses
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-system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst 87005 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 87005 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0 87005 # number of overall misses
-system.cpu1.icache.overall_misses::1 0 # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst 87005 # number of overall misses
system.cpu1.icache.overall_misses::total 87005 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency 1260607500 # number of ReadReq miss cycles
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-system.cpu1.icache.overall_miss_latency 1260607500 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0 5286354 # number of ReadReq accesses(hits+misses)
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+system.cpu1.icache.overall_miss_latency::total 1260607500 # number of overall miss cycles
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system.cpu1.icache.ReadReq_accesses::total 5286354 # number of ReadReq accesses(hits+misses)
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system.cpu1.icache.demand_accesses::total 5286354 # number of demand (read+write) accesses
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+system.cpu1.icache.overall_accesses::cpu1.inst 5286354 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 5286354 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.016458 # miss rate for ReadReq accesses
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-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14488.908683 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14488.908683 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.016458 # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst 0.016458 # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst 0.016458 # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 14 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses 87005 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses 87005 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 87005 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 999558500 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency 999558500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 999558500 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.016458 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0 0.016458 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0.016458 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks 14 # number of writebacks
+system.cpu1.icache.writebacks::total 14 # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 87005 # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total 87005 # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst 87005 # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total 87005 # number of demand (read+write) MSHR misses
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+system.cpu1.icache.overall_mshr_misses::total 87005 # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 999558500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total 999558500 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 999558500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 999558500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 999558500 # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total 999558500 # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.016458 # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 52960 # number of replacements
system.cpu1.dcache.tagsinuse 389.521271 # Cycle average of tags in use
system.cpu1.dcache.sampled_refs 53472 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 30.762530 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 1942411783000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 389.521271 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.760784 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 1003161 # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data 389.521271 # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data 0.760784 # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total 0.760784 # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data 1003161 # number of ReadReq hits
system.cpu1.dcache.ReadReq_hits::total 1003161 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 616899 # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data 616899 # number of WriteReq hits
system.cpu1.dcache.WriteReq_hits::total 616899 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 11784 # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 11784 # number of LoadLockedReq hits
system.cpu1.dcache.LoadLockedReq_hits::total 11784 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 11526 # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 11526 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 11526 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 1620060 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data 1620060 # number of demand (read+write) hits
system.cpu1.dcache.demand_hits::total 1620060 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 1620060 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data 1620060 # number of overall hits
system.cpu1.dcache.overall_hits::total 1620060 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 37113 # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data 37113 # number of ReadReq misses
system.cpu1.dcache.ReadReq_misses::total 37113 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 20421 # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data 20421 # number of WriteReq misses
system.cpu1.dcache.WriteReq_misses::total 20421 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 982 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 982 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 982 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 505 # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data 505 # number of StoreCondReq misses
system.cpu1.dcache.StoreCondReq_misses::total 505 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 57534 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data 57534 # number of demand (read+write) misses
system.cpu1.dcache.demand_misses::total 57534 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 57534 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data 57534 # number of overall misses
system.cpu1.dcache.overall_misses::total 57534 # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency 533263000 # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency 556796000 # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency 13079000 # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency 6416000 # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency 1090059000 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 1090059000 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 1040274 # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 533263000 # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total 533263000 # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 556796000 # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total 556796000 # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 13079000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total 13079000 # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 6416000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total 6416000 # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data 1090059000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total 1090059000 # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data 1090059000 # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total 1090059000 # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data 1040274 # number of ReadReq accesses(hits+misses)
system.cpu1.dcache.ReadReq_accesses::total 1040274 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 637320 # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data 637320 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 637320 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 12766 # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 12766 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 12766 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 12031 # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 12031 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 12031 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 1677594 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data 1677594 # number of demand (read+write) accesses
system.cpu1.dcache.demand_accesses::total 1677594 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 1677594 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data 1677594 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 1677594 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.035676 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.032042 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.076923 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.041975 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.034296 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.034296 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.035676 # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.032042 # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.076923 # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.041975 # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data 0.034296 # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.034296 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 29784 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses 37113 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 20421 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 982 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses 505 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 57534 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 57534 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 421922000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency 495533000 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 10133000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 4901000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency 917455000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 917455000 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 11413500 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 298050500 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 309464000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.035676 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.032042 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.076923 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.041975 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.034296 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.034296 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 9704.950495 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 29784 # number of writebacks
+system.cpu1.dcache.writebacks::total 29784 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 37113 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 37113 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 20421 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 20421 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 982 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 982 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 505 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 505 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 57534 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 57534 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 57534 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 57534 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 421922000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 421922000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 495533000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 495533000 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 10133000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 10133000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 4901000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 4901000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 917455000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 917455000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 917455000 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 917455000 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 11413500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 11413500 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 298050500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 298050500 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 309464000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 309464000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035676 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.076923 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.041975 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.034296 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 9704.950495 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
progress_interval=0
system=system
tracer=system.cpu.tracer
+workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[1]
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848432
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848304
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848569
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848451
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848515
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848579
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848643
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848707
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848771
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848835
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848899
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615850617
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848891
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848816
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848696
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848936
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848680
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848944
pio_latency=1000
pio_size=8
-platform=system.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
-platform=system.tsunami
system=system
pio=system.iobus.port[22]
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
-platform=system.tsunami
system=system
time=Thu Jan 1 00:00:00 2009
tsunami=system.tsunami
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
-platform=system.tsunami
system=system
tsunami=system.tsunami
pio=system.iobus.port[2]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:43
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:47
gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
Global frequency set at 1000000000000 ticks per second
- 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 1915548867000 because m5_exit instruction encountered
sim_ticks 1915548867000 # Number of ticks simulated
final_tick 1915548867000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1659827 # Simulator instruction rate (inst/s)
-host_tick_rate 56637748152 # Simulator tick rate (ticks/s)
-host_mem_usage 290988 # Number of bytes of host memory used
-host_seconds 33.82 # Real time elapsed on the host
+host_inst_rate 1998214 # Simulator instruction rate (inst/s)
+host_op_rate 1998212 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 68184353129 # Simulator tick rate (ticks/s)
+host_mem_usage 288188 # Number of bytes of host memory used
+host_seconds 28.09 # Real time elapsed on the host
sim_insts 56137087 # Number of instructions simulated
+sim_ops 56137087 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 29663360 # Number of bytes read from this memory
system.physmem.bytes_inst_read 943040 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10122368 # Number of bytes written to this memory
system.l2c.sampled_refs 421794 # Sample count of references to valid blocks.
system.l2c.avg_refs 5.479364 # Average number of references to valid blocks.
system.l2c.warmup_cycle 6937912000 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 11241.373247 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23110.665097 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.171530 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.352641 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 1710461 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 23110.665097 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 3746.363547 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 7495.009700 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.352641 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.057165 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.114365 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.524171 # Average percentage of cache occupancy
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system.l2c.ReadReq_hits::total 1710461 # number of ReadReq hits
-system.l2c.Writeback_hits::0 826671 # number of Writeback hits
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system.l2c.Writeback_hits::total 826671 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 6 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 185878 # number of ReadExReq hits
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system.l2c.ReadExReq_hits::total 185878 # number of ReadExReq hits
-system.l2c.demand_hits::0 1896339 # number of demand (read+write) hits
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system.l2c.demand_hits::total 1896339 # number of demand (read+write) hits
-system.l2c.overall_hits::0 1896339 # number of overall hits
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system.l2c.overall_hits::total 1896339 # number of overall hits
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system.l2c.ReadReq_misses::total 304138 # number of ReadReq misses
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system.l2c.UpgradeReq_misses::total 7 # number of UpgradeReq misses
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system.l2c.ReadExReq_misses::total 118294 # number of ReadExReq misses
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system.l2c.demand_misses::total 422432 # number of demand (read+write) misses
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system.l2c.overall_misses::total 422432 # number of overall misses
-system.l2c.ReadReq_miss_latency 15820206500 # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency 248000 # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency 6151753000 # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency 21971959500 # number of demand (read+write) miss cycles
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+system.l2c.overall_miss_latency::cpu.data 21205698000 # number of overall miss cycles
+system.l2c.overall_miss_latency::total 21971959500 # number of overall miss cycles
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system.l2c.ReadReq_accesses::total 2014599 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 826671 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 826671 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 13 # number of UpgradeReq accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 304172 # number of ReadExReq accesses(hits+misses)
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system.l2c.ReadExReq_accesses::total 304172 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2318771 # number of demand (read+write) accesses
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system.l2c.demand_accesses::total 2318771 # number of demand (read+write) accesses
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system.l2c.overall_accesses::total 2318771 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.150967 # miss rate for ReadReq accesses
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-system.l2c.demand_miss_rate::0 0.182179 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.l2c.demand_miss_rate::total no_value # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.182179 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.l2c.overall_miss_rate::total no_value # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0 52016.540189 # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429 # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 inf # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total inf # average UpgradeReq miss latency
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-system.l2c.demand_avg_miss_latency::total inf # average overall miss latency
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-system.l2c.overall_avg_miss_latency::total inf # average overall miss latency
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 116650 # number of writebacks
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-system.l2c.ReadReq_mshr_misses 304138 # number of ReadReq MSHR misses
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-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 12170545000 # number of ReadReq MSHR miss cycles
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-system.l2c.ReadReq_mshr_uncacheable_latency 772673000 # number of ReadReq MSHR uncacheable cycles
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system.cpu.icache.overall_accesses::total 56148907 # number of overall (read+write) accesses
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-system.cpu.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
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+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1390115 # number of replacements
system.cpu.dcache.tagsinuse 511.984023 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1390627 # Sample count of references to valid blocks.
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-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
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-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
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+system.cpu.dcache.demand_mshr_miss_latency::total 32230024000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 32230024000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 32230024000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862763000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862763000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1199607500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1199607500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2062370500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 2062370500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120441 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049462 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.085908 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091383 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn: instruction 'mcr bpiallis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr dccimvac' unimplemented
-warn: instruction 'mcr dccmvau' unimplemented
-warn: instruction 'mcr icimvau' unimplemented
-warn: instruction 'mcr bpiallis' unimplemented
-warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn: instruction 'mcr icialluis' unimplemented
-warn: instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+ File "<string>", line 1, in <module>
+ File "/tmp/gem5.ali/src/python/m5/main.py", line 357, in main
+ exec filecode in scope
+ File "tests/run.py", line 70, in <module>
+ execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+ File "tests/configs/realview-simple-atomic-dual.py", line 86, in <module>
+ system.l2c.num_cpus = 2
+ File "/tmp/gem5.ali/src/python/m5/SimObject.py", line 725, in __setattr__
+ % (self.__class__.__name__, attr)
+AttributeError: Class L2 has no parameter num_cpus
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:37:03
gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 2411694099500 because m5_exit instruction encountered
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
-
----------- Begin Simulation Statistics ----------
-sim_seconds 2.411694 # Number of seconds simulated
-sim_ticks 2411694099500 # Number of ticks simulated
-final_tick 2411694099500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2039542 # Simulator instruction rate (inst/s)
-host_tick_rate 61821688958 # Simulator tick rate (ticks/s)
-host_mem_usage 378872 # Number of bytes of host memory used
-host_seconds 39.01 # Real time elapsed on the host
-sim_insts 79563488 # Number of instructions simulated
-system.nvmem.bytes_read 68 # Number of bytes read from this memory
-system.nvmem.bytes_inst_read 68 # Number of instructions bytes read from this memory
-system.nvmem.bytes_written 0 # Number of bytes written to this memory
-system.nvmem.num_reads 17 # Number of read requests responded to by this memory
-system.nvmem.num_writes 0 # Number of write requests responded to by this memory
-system.nvmem.num_other 0 # Number of other requests responded to by this memory
-system.nvmem.bw_read 28 # Total read bandwidth from this memory (bytes/s)
-system.nvmem.bw_inst_read 28 # Instruction read bandwidth from this memory (bytes/s)
-system.nvmem.bw_total 28 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read 123270308 # Number of bytes read from this memory
-system.physmem.bytes_inst_read 1011392 # Number of instructions bytes read from this memory
-system.physmem.bytes_written 10185232 # Number of bytes written to this memory
-system.physmem.num_reads 14146769 # Number of read requests responded to by this memory
-system.physmem.num_writes 869038 # Number of write requests responded to by this memory
-system.physmem.num_other 0 # Number of other requests responded to by this memory
-system.physmem.bw_read 51113575 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read 419370 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write 4223269 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total 55336844 # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements 127720 # number of replacements
-system.l2c.tagsinuse 25547.920863 # Cycle average of tags in use
-system.l2c.total_refs 1498989 # Total number of references to valid blocks.
-system.l2c.sampled_refs 156132 # Sample count of references to valid blocks.
-system.l2c.avg_refs 9.600780 # Average number of references to valid blocks.
-system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 4404.089299 # Average occupied blocks per context
-system.l2c.occ_blocks::1 6217.918720 # Average occupied blocks per context
-system.l2c.occ_blocks::2 14925.912843 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.067201 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.094878 # Average percentage of cache occupancy
-system.l2c.occ_percent::2 0.227751 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 706190 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 499815 # number of ReadReq hits
-system.l2c.ReadReq_hits::2 12920 # number of ReadReq hits
-system.l2c.ReadReq_hits::total 1218925 # number of ReadReq hits
-system.l2c.Writeback_hits::0 580461 # number of Writeback hits
-system.l2c.Writeback_hits::total 580461 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 776 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1 523 # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total 1299 # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0 147 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1 202 # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total 349 # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0 64831 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1 37797 # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total 102628 # number of ReadExReq hits
-system.l2c.demand_hits::0 771021 # number of demand (read+write) hits
-system.l2c.demand_hits::1 537612 # number of demand (read+write) hits
-system.l2c.demand_hits::2 12920 # number of demand (read+write) hits
-system.l2c.demand_hits::total 1321553 # number of demand (read+write) hits
-system.l2c.overall_hits::0 771021 # number of overall hits
-system.l2c.overall_hits::1 537612 # number of overall hits
-system.l2c.overall_hits::2 12920 # number of overall hits
-system.l2c.overall_hits::total 1321553 # number of overall hits
-system.l2c.ReadReq_misses::0 19675 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 15224 # number of ReadReq misses
-system.l2c.ReadReq_misses::2 52 # number of ReadReq misses
-system.l2c.ReadReq_misses::total 34951 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 6349 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1 3492 # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total 9841 # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0 791 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1 531 # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total 1322 # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0 99048 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1 48785 # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total 147833 # number of ReadExReq misses
-system.l2c.demand_misses::0 118723 # number of demand (read+write) misses
-system.l2c.demand_misses::1 64009 # number of demand (read+write) misses
-system.l2c.demand_misses::2 52 # number of demand (read+write) misses
-system.l2c.demand_misses::total 182784 # number of demand (read+write) misses
-system.l2c.overall_misses::0 118723 # number of overall misses
-system.l2c.overall_misses::1 64009 # number of overall misses
-system.l2c.overall_misses::2 52 # number of overall misses
-system.l2c.overall_misses::total 182784 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 725865 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 515039 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2 12972 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total 1253876 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 580461 # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total 580461 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 7125 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1 4015 # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total 11140 # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0 938 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1 733 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total 1671 # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 163879 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1 86582 # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total 250461 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 889744 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 601621 # number of demand (read+write) accesses
-system.l2c.demand_accesses::2 12972 # number of demand (read+write) accesses
-system.l2c.demand_accesses::total 1504337 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 889744 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 601621 # number of overall (read+write) accesses
-system.l2c.overall_accesses::2 12972 # number of overall (read+write) accesses
-system.l2c.overall_accesses::total 1504337 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.027106 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.029559 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2 0.004009 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.060673 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.891088 # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1 0.869738 # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0 0.843284 # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1 0.724420 # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.604397 # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1 0.563454 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.133435 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.106394 # miss rate for demand accesses
-system.l2c.demand_miss_rate::2 0.004009 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.243838 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.133435 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.106394 # miss rate for overall accesses
-system.l2c.overall_miss_rate::2 0.004009 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.243838 # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::2 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
-system.l2c.blocked::no_targets 0 # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.l2c.fast_writes 0 # number of fast writes performed
-system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 111818 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
-system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu0.dtb.inst_hits 0 # ITB inst hits
-system.cpu0.dtb.inst_misses 0 # ITB inst misses
-system.cpu0.dtb.read_hits 9339288 # DTB read hits
-system.cpu0.dtb.read_misses 5153 # DTB read misses
-system.cpu0.dtb.write_hits 6907876 # DTB write hits
-system.cpu0.dtb.write_misses 1048 # DTB write misses
-system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries 2247 # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults 150 # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses 9344441 # DTB read accesses
-system.cpu0.dtb.write_accesses 6908924 # DTB write accesses
-system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu0.dtb.hits 16247164 # DTB hits
-system.cpu0.dtb.misses 6201 # DTB misses
-system.cpu0.dtb.accesses 16253365 # DTB accesses
-system.cpu0.itb.inst_hits 34822552 # ITB inst hits
-system.cpu0.itb.inst_misses 2978 # ITB inst misses
-system.cpu0.itb.read_hits 0 # DTB read hits
-system.cpu0.itb.read_misses 0 # DTB read misses
-system.cpu0.itb.write_hits 0 # DTB write hits
-system.cpu0.itb.write_misses 0 # DTB write misses
-system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries 1462 # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses 0 # DTB read accesses
-system.cpu0.itb.write_accesses 0 # DTB write accesses
-system.cpu0.itb.inst_accesses 34825530 # ITB inst accesses
-system.cpu0.itb.hits 34822552 # DTB hits
-system.cpu0.itb.misses 2978 # DTB misses
-system.cpu0.itb.accesses 34825530 # DTB accesses
-system.cpu0.numCycles 4823340800 # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 44975797 # Number of instructions executed
-system.cpu0.num_int_alu_accesses 39858123 # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses 4945 # Number of float alu accesses
-system.cpu0.num_func_calls 1311755 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 4494669 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 39858123 # number of integer instructions
-system.cpu0.num_fp_insts 4945 # number of float instructions
-system.cpu0.num_int_register_reads 202125744 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 42204131 # number of times the integer registers were written
-system.cpu0.num_fp_register_reads 3641 # number of times the floating registers were read
-system.cpu0.num_fp_register_writes 1308 # number of times the floating registers were written
-system.cpu0.num_mem_refs 17030946 # number of memory refs
-system.cpu0.num_load_insts 9786549 # Number of load instructions
-system.cpu0.num_store_insts 7244397 # Number of store instructions
-system.cpu0.num_idle_cycles 4777543068.852608 # Number of idle cycles
-system.cpu0.num_busy_cycles 45797731.147393 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.009495 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.990505 # Percentage of idle cycles
-system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 59311 # number of quiesce instructions executed
-system.cpu0.icache.replacements 504460 # number of replacements
-system.cpu0.icache.tagsinuse 511.627588 # Cycle average of tags in use
-system.cpu0.icache.total_refs 34319155 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 504972 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 67.962491 # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle 64519524000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 511.627588 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.999273 # Average percentage of cache occupancy
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-system.cpu0.icache.demand_hits::total 34319155 # number of demand (read+write) hits
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-system.cpu0.icache.overall_hits::total 34319155 # number of overall hits
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-system.cpu0.icache.ReadReq_misses::total 504973 # number of ReadReq misses
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-system.cpu0.icache.ReadReq_accesses::total 34824128 # number of ReadReq accesses(hits+misses)
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-system.cpu0.icache.demand_accesses::total 34824128 # number of demand (read+write) accesses
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-system.cpu0.dcache.avg_refs 38.643068 # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit.
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-system.cpu0.dcache.ReadReq_hits::total 7803296 # number of ReadReq hits
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-system.cpu0.dcache.WriteReq_hits::total 6534059 # number of WriteReq hits
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-system.cpu0.dcache.LoadLockedReq_hits::total 172314 # number of LoadLockedReq hits
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-system.cpu0.dcache.StoreCondReq_misses::total 7293 # number of StoreCondReq misses
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-system.cpu0.dcache.LoadLockedReq_accesses::total 182192 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu0.dcache.StoreCondReq_accesses::total 182159 # number of StoreCondReq accesses(hits+misses)
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-system.cpu0.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
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-system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
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-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 247434 # number of replacements
-system.cpu1.dcache.tagsinuse 444.903488 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 9876826 # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs 247805 # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs 39.857251 # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle 69253206000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 444.903488 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.868952 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 5955973 # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total 5955973 # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0 3777038 # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total 3777038 # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0 59593 # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total 59593 # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0 60090 # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total 60090 # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0 9733011 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1 0 # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total 9733011 # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0 9733011 # number of overall hits
-system.cpu1.dcache.overall_hits::1 0 # number of overall hits
-system.cpu1.dcache.overall_hits::total 9733011 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 165799 # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total 165799 # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0 111467 # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total 111467 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 10725 # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total 10725 # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0 10198 # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total 10198 # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0 277266 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1 0 # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total 277266 # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0 277266 # number of overall misses
-system.cpu1.dcache.overall_misses::1 0 # number of overall misses
-system.cpu1.dcache.overall_misses::total 277266 # number of overall misses
-system.cpu1.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0 6121772 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total 6121772 # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0 3888505 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total 3888505 # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0 70318 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total 70318 # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0 70288 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total 70288 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 10010277 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total 10010277 # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0 10010277 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total 10010277 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.027083 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.028666 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.152521 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.145089 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.027698 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.027698 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes 0 # number of fast writes performed
-system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 202201 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.iocache.replacements 0 # number of replacements
-system.iocache.tagsinuse 0 # Cycle average of tags in use
-system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
-system.iocache.avg_refs no_value # Average number of references to valid blocks.
-system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
-system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
-system.iocache.fast_writes 0 # number of fast writes performed
-system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
-
----------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
system=system
tracer=system.cpu.tracer
width=1
+workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.realview
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=A9SCU
pio_addr=520093696
pio_latency=1000
-platform=system.realview
system=system
pio=system.membus.port[5]
ignore_access=false
pio_addr=268451840
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[24]
min_backoff_delay=4000
pio_addr=268566528
pio_latency=10000
-platform=system.realview
system=system
vnc=system.vncserver
dma=system.iobus.port[6]
ignore_access=false
pio_addr=268632064
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[12]
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
-platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ignore_access=false
pio_addr=268513280
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[19]
ignore_access=false
pio_addr=268517376
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[20]
ignore_access=false
pio_addr=268521472
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[21]
is_mouse=false
pio_addr=268460032
pio_latency=1000
-platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[7]
is_mouse=true
pio_addr=268464128
pio_latency=1000
-platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[8]
pio_addr=520101888
pio_latency=1000
pio_size=4095
-platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
int_num_watchdog=30
pio_addr=520095232
pio_latency=1000
-platform=system.realview
system=system
pio=system.membus.port[6]
ignore_access=false
pio_addr=268455936
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[25]
idreg=0
pio_addr=268435456
pio_latency=1000
-platform=system.realview
proc_id0=201326592
proc_id1=201327138
system=system
ignore_access=false
pio_addr=268529664
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[26]
ignore_access=false
pio_addr=268492800
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[23]
ignore_access=false
pio_addr=269357056
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[16]
ignore_access=true
pio_addr=268439552
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[17]
ignore_access=false
pio_addr=268488704
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[22]
int_num1=36
pio_addr=268505088
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[3]
int_num1=37
pio_addr=268509184
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[4]
ignore_access=false
pio_addr=268476416
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[13]
ignore_access=false
pio_addr=268480512
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[14]
ignore_access=false
pio_addr=268484608
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[15]
ignore_access=false
pio_addr=268500992
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[18]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:24:55
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:36:22
gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
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+system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 13150366 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13150366 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 9943631 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 9943631 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9943631 # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::0 235999 # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data 235999 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 235999 # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0 247136 # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data 247136 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247136 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0 23093997 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 23093997 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23093997 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 23093997 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 23093997 # number of overall hits
system.cpu.dcache.overall_hits::total 23093997 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 364548 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 364548 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 364548 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 249897 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 249897 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 249897 # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0 11138 # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data 11138 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11138 # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0 614445 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data 614445 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 614445 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 614445 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data 614445 # number of overall misses
system.cpu.dcache.overall_misses::total 614445 # number of overall misses
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 13514914 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 13514914 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13514914 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 10193528 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10193528 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10193528 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 247137 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247137 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247137 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 247136 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247136 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247136 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 23708442 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 23708442 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23708442 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 23708442 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23708442 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23708442 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.026974 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.024515 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.045068 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.025917 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.025917 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026974 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024515 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045068 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.025917 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.025917 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 559892 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 559892 # number of writebacks
+system.cpu.dcache.writebacks::total 559892 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
load_addr_mask=268435455
machine_type=RealView_PBX
mem_mode=timing
-memories=system.physmem system.nvmem
+memories=system.nvmem system.physmem
midr_regval=890224640
num_work_ids=16
physmem=system.physmem
progress_interval=0
system=system
tracer=system.cpu0.tracer
+workload=
dcache_port=system.cpu0.dcache.cpu_side
icache_port=system.cpu0.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
progress_interval=0
system=system
tracer=system.cpu1.tracer
+workload=
dcache_port=system.cpu1.dcache.cpu_side
icache_port=system.cpu1.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.realview
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=A9SCU
pio_addr=520093696
pio_latency=1000
-platform=system.realview
system=system
pio=system.membus.port[5]
ignore_access=false
pio_addr=268451840
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[24]
min_backoff_delay=4000
pio_addr=268566528
pio_latency=10000
-platform=system.realview
system=system
vnc=system.vncserver
dma=system.iobus.port[6]
ignore_access=false
pio_addr=268632064
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[12]
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
-platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ignore_access=false
pio_addr=268513280
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[19]
ignore_access=false
pio_addr=268517376
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[20]
ignore_access=false
pio_addr=268521472
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[21]
is_mouse=false
pio_addr=268460032
pio_latency=1000
-platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[7]
is_mouse=true
pio_addr=268464128
pio_latency=1000
-platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[8]
pio_addr=520101888
pio_latency=1000
pio_size=4095
-platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
int_num_watchdog=30
pio_addr=520095232
pio_latency=1000
-platform=system.realview
system=system
pio=system.membus.port[6]
ignore_access=false
pio_addr=268455936
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[25]
idreg=0
pio_addr=268435456
pio_latency=1000
-platform=system.realview
proc_id0=201326592
proc_id1=201327138
system=system
ignore_access=false
pio_addr=268529664
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[26]
ignore_access=false
pio_addr=268492800
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[23]
ignore_access=false
pio_addr=269357056
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[16]
ignore_access=true
pio_addr=268439552
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[17]
ignore_access=false
pio_addr=268488704
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[22]
int_num1=36
pio_addr=268505088
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[3]
int_num1=37
pio_addr=268509184
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[4]
ignore_access=false
pio_addr=268476416
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[13]
ignore_access=false
pio_addr=268480512
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[14]
ignore_access=false
pio_addr=268484608
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[15]
ignore_access=false
pio_addr=268500992
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[18]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:38:22
gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
sim_ticks 2669611225000 # Number of ticks simulated
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sim_freq 1000000000000 # Frequency of simulated ticks
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for ReadReq accesses
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+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.053873 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.051351 # mshr miss rate for ReadReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.883009 # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764706 # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.767500 # mshr miss rate for SCUpgradeReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.005632 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.009235 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.020397 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.316029 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.001908 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.002130 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.014869 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.217778 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40034.893305 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40375.955770 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40076.671408 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40153.934520 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40086.080586 # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.479142 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964 # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
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+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cpu0.numCycles 5337805216 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 43969024 # Number of instructions executed
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system.cpu0.num_int_alu_accesses 39881498 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4107 # Number of float alu accesses
system.cpu0.num_func_calls 977479 # number of times a function call or return occured
system.cpu0.icache.sampled_refs 380581 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 92.929786 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 74921716000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 510.849663 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.997753 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0 35367311 # number of ReadReq hits
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+system.cpu0.icache.occ_percent::total 0.997753 # Average percentage of cache occupancy
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system.cpu0.icache.ReadReq_hits::total 35367311 # number of ReadReq hits
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system.cpu0.icache.demand_hits::total 35367311 # number of demand (read+write) hits
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system.cpu0.icache.ReadReq_misses::total 380583 # number of ReadReq misses
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system.cpu0.icache.demand_misses::total 380583 # number of demand (read+write) misses
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system.cpu0.icache.overall_misses::total 380583 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 5651439000 # number of ReadReq miss cycles
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+system.cpu0.icache.overall_miss_latency::total 5651439000 # number of overall miss cycles
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system.cpu0.icache.ReadReq_accesses::total 35747894 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.demand_accesses::cpu0.inst 35747894 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 35747894 # number of demand (read+write) accesses
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system.cpu0.icache.overall_accesses::total 35747894 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0 0.010646 # miss rate for ReadReq accesses
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-system.cpu0.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total no_value # miss rate for demand accesses
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-system.cpu0.icache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total no_value # miss rate for overall accesses
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-system.cpu0.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14849.425749 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14849.425749 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total inf # average overall miss latency
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+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749 # average ReadReq miss latency
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+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 12960 # number of writebacks
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-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 380583 # number of ReadReq MSHR misses
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-system.cpu0.icache.overall_mshr_misses 380583 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 4509188500 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 4509188500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 4509188500 # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency 351814000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 351814000 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0 0.010646 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu0.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0 0.010646 # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034 # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.writebacks::writebacks 12960 # number of writebacks
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+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 351814000 # number of overall MSHR uncacheable cycles
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+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average ReadReq mshr miss latency
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+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034 # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 334596 # number of replacements
system.cpu0.dcache.tagsinuse 450.118381 # Cycle average of tags in use
system.cpu0.dcache.sampled_refs 335004 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 38.434389 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 663204000 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 450.118381 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.879137 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0 7428609 # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data 450.118381 # Average occupied blocks per requestor
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+system.cpu0.dcache.occ_percent::total 0.879137 # Average percentage of cache occupancy
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system.cpu0.dcache.ReadReq_hits::total 7428609 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0 5172633 # number of WriteReq hits
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system.cpu0.dcache.WriteReq_hits::total 5172633 # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0 126778 # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 126778 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 126778 # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0 127996 # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data 127996 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 127996 # number of StoreCondReq hits
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system.cpu0.dcache.demand_hits::total 12601242 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0 12601242 # number of overall hits
-system.cpu0.dcache.overall_hits::1 0 # number of overall hits
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system.cpu0.dcache.overall_hits::total 12601242 # number of overall hits
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system.cpu0.dcache.ReadReq_misses::total 217330 # number of ReadReq misses
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system.cpu0.dcache.WriteReq_misses::total 155538 # number of WriteReq misses
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system.cpu0.dcache.LoadLockedReq_misses::total 9456 # number of LoadLockedReq misses
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system.cpu0.dcache.StoreCondReq_misses::total 8189 # number of StoreCondReq misses
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system.cpu0.dcache.demand_misses::total 372868 # number of demand (read+write) misses
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system.cpu0.dcache.overall_misses::total 372868 # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency 3330686000 # number of ReadReq miss cycles
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-system.cpu0.dcache.LoadLockedReq_miss_latency 100249000 # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency 70240000 # number of StoreCondReq miss cycles
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system.cpu0.dcache.ReadReq_accesses::total 7645939 # number of ReadReq accesses(hits+misses)
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system.cpu0.dcache.WriteReq_accesses::total 5328171 # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0 136234 # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 136234 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 136234 # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0 136185 # number of StoreCondReq accesses(hits+misses)
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system.cpu0.dcache.StoreCondReq_accesses::total 136185 # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0 12974110 # number of demand (read+write) accesses
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system.cpu0.dcache.demand_accesses::total 12974110 # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0 12974110 # number of overall (read+write) accesses
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system.cpu0.dcache.overall_accesses::total 12974110 # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0 0.028424 # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0 0.029192 # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0 0.069410 # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0 0.060131 # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0 0.028739 # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0 0.028739 # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385 # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901 # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596 # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 8577.359873 # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728 # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028424 # miss rate for ReadReq accesses
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+system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028739 # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028739 # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385 # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901 # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596 # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8577.359873 # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
-system.cpu0.dcache.writebacks 294891 # number of writebacks
-system.cpu0.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses 217330 # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses 155538 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 9456 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses 8184 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses 372868 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses 372868 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency 2678673500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency 5851029000 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 71881000 # number of LoadLockedReq MSHR miss cycles
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-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency 1000 # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency 8529702500 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency 8529702500 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 9171180500 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 40129379500 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 49300560000 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0 0.028424 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0 0.029192 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0 0.069410 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0 0.060095 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0 0.028739 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0 0.028739 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 7601.628596 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 5582.966764 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency inf # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624 # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks 294891 # number of writebacks
+system.cpu0.dcache.writebacks::total 294891 # number of writebacks
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+system.cpu0.dcache.ReadReq_mshr_misses::total 217330 # number of ReadReq MSHR misses
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+system.cpu0.dcache.StoreCondReq_mshr_misses::total 8184 # number of StoreCondReq MSHR misses
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+system.cpu0.dcache.demand_mshr_misses::total 372868 # number of demand (read+write) MSHR misses
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+system.cpu0.dcache.overall_mshr_misses::total 372868 # number of overall MSHR misses
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+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5851029000 # number of WriteReq MSHR miss cycles
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 71881000 # number of LoadLockedReq MSHR miss cycles
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+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles
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+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 9171180500 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 40129379500 # number of WriteReq MSHR uncacheable cycles
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+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028424 # mshr miss rate for ReadReq accesses
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+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.069410 # mshr miss rate for LoadLockedReq accesses
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+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028739 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7601.628596 # average LoadLockedReq mshr miss latency
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+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624 # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.numCycles 5339222450 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.num_insts 34444935 # Number of instructions executed
+system.cpu1.committedInsts 25921760 # Number of instructions committed
+system.cpu1.committedOps 34444935 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 31033253 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 5714 # Number of float alu accesses
system.cpu1.num_func_calls 1093852 # number of times a function call or return occured
system.cpu1.icache.sampled_refs 508733 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 51.774788 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 191336880000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0 497.375159 # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0 0.971436 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0 26339543 # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst 497.375159 # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst 0.971436 # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total 0.971436 # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst 26339543 # number of ReadReq hits
system.cpu1.icache.ReadReq_hits::total 26339543 # number of ReadReq hits
-system.cpu1.icache.demand_hits::0 26339543 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::cpu1.inst 26339543 # number of demand (read+write) hits
system.cpu1.icache.demand_hits::total 26339543 # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0 26339543 # number of overall hits
-system.cpu1.icache.overall_hits::1 0 # number of overall hits
+system.cpu1.icache.overall_hits::cpu1.inst 26339543 # number of overall hits
system.cpu1.icache.overall_hits::total 26339543 # number of overall hits
-system.cpu1.icache.ReadReq_misses::0 508733 # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::cpu1.inst 508733 # number of ReadReq misses
system.cpu1.icache.ReadReq_misses::total 508733 # number of ReadReq misses
-system.cpu1.icache.demand_misses::0 508733 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst 508733 # number of demand (read+write) misses
system.cpu1.icache.demand_misses::total 508733 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0 508733 # number of overall misses
-system.cpu1.icache.overall_misses::1 0 # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst 508733 # number of overall misses
system.cpu1.icache.overall_misses::total 508733 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency 7436442000 # number of ReadReq miss cycles
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-system.cpu1.icache.ReadReq_accesses::0 26848276 # number of ReadReq accesses(hits+misses)
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+system.cpu1.icache.overall_miss_latency::cpu1.inst 7436442000 # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total 7436442000 # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst 26848276 # number of ReadReq accesses(hits+misses)
system.cpu1.icache.ReadReq_accesses::total 26848276 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::cpu1.inst 26848276 # number of demand (read+write) accesses
system.cpu1.icache.demand_accesses::total 26848276 # number of demand (read+write) accesses
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+system.cpu1.icache.overall_accesses::cpu1.inst 26848276 # number of overall (read+write) accesses
system.cpu1.icache.overall_accesses::total 26848276 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0 0.018948 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0 0.018948 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1 no_value # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::0 0.018948 # miss rate for overall accesses
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-system.cpu1.icache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14617.573462 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14617.573462 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total inf # average overall miss latency
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+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462 # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.writebacks 27998 # number of writebacks
-system.cpu1.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu1.icache.ReadReq_mshr_misses 508733 # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses 508733 # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses 508733 # number of overall MSHR misses
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-system.cpu1.icache.ReadReq_mshr_miss_latency 5908060000 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency 5908060000 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency 5908060000 # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency 5250000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency 5250000 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0 0.018948 # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0 0.018948 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409 # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks 27998 # number of writebacks
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+system.cpu1.icache.demand_mshr_miss_latency::total 5908060000 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 295754 # number of replacements
system.cpu1.dcache.tagsinuse 467.166427 # Cycle average of tags in use
system.cpu1.dcache.sampled_refs 296266 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 39.616787 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 75924171000 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 467.166427 # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0 0.912434 # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0 6345290 # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data 467.166427 # Average occupied blocks per requestor
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+system.cpu1.dcache.occ_percent::total 0.912434 # Average percentage of cache occupancy
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system.cpu1.dcache.ReadReq_hits::total 6345290 # number of ReadReq hits
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system.cpu1.dcache.WriteReq_hits::total 5152610 # number of WriteReq hits
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system.cpu1.dcache.LoadLockedReq_hits::total 104795 # number of LoadLockedReq hits
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+system.cpu1.dcache.StoreCondReq_hits::cpu1.data 106403 # number of StoreCondReq hits
system.cpu1.dcache.StoreCondReq_hits::total 106403 # number of StoreCondReq hits
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system.cpu1.dcache.demand_hits::total 11497900 # number of demand (read+write) hits
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system.cpu1.dcache.overall_hits::total 11497900 # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0 188245 # number of ReadReq misses
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system.cpu1.dcache.ReadReq_misses::total 188245 # number of ReadReq misses
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system.cpu1.dcache.WriteReq_misses::total 137493 # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0 11557 # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11557 # number of LoadLockedReq misses
system.cpu1.dcache.LoadLockedReq_misses::total 11557 # number of LoadLockedReq misses
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system.cpu1.dcache.StoreCondReq_misses::total 9906 # number of StoreCondReq misses
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system.cpu1.dcache.demand_misses::total 325738 # number of demand (read+write) misses
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system.cpu1.dcache.overall_misses::total 325738 # number of overall misses
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system.cpu1.dcache.ReadReq_accesses::total 6533535 # number of ReadReq accesses(hits+misses)
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+system.cpu1.dcache.WriteReq_accesses::cpu1.data 5290103 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 5290103 # number of WriteReq accesses(hits+misses)
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+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116352 # number of LoadLockedReq accesses(hits+misses)
system.cpu1.dcache.LoadLockedReq_accesses::total 116352 # number of LoadLockedReq accesses(hits+misses)
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+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 116309 # number of StoreCondReq accesses(hits+misses)
system.cpu1.dcache.StoreCondReq_accesses::total 116309 # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0 11823638 # number of demand (read+write) accesses
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system.cpu1.dcache.demand_accesses::total 11823638 # number of demand (read+write) accesses
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+system.cpu1.dcache.overall_accesses::cpu1.data 11823638 # number of overall (read+write) accesses
system.cpu1.dcache.overall_accesses::total 11823638 # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0 0.028812 # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0 0.025991 # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0 0.099328 # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0 0.085170 # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0 0.027550 # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0 0.027550 # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832 # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156 # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004 # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 8327.579245 # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1 inf # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total inf # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634 # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.028812 # miss rate for ReadReq accesses
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+system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027550 # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832 # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156 # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004 # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8327.579245 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634 # average overall miss latency
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
-system.cpu1.dcache.writebacks 253551 # number of writebacks
-system.cpu1.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses 188245 # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses 137493 # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses 11557 # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses 9900 # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses 325738 # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses 325738 # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency 2164153000 # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency 3711466500 # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency 97050000 # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency 52793000 # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency 5875619500 # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency 5875619500 # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency 470526000 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000 # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0 0.028812 # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0 0.025991 # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0 0.099328 # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0 0.085118 # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1 inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total inf # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0 0.027550 # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0 0.027550 # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026 # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 8397.508004 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency 5332.626263 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392 # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks 253551 # number of writebacks
+system.cpu1.dcache.writebacks::total 253551 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 188245 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 188245 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 137493 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 137493 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11557 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11557 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 9900 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 9900 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 325738 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 325738 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 325738 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 325738 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2164153000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2164153000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 3711466500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 3711466500 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 97050000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 97050000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 52793000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 52793000 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 5875619500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 5875619500 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5875619500 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 5875619500 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 470526000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 470526000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.028812 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025991 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.099328 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.085118 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027550 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8397.508004 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5332.626263 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392 # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1342252853622 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1342252853622 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxArmSystem
children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
boot_loader=/dist/m5/system/binaries/boot.arm
boot_loader_mem=system.nvmem
boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
progress_interval=0
system=system
tracer=system.cpu.tracer
+workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.realview
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=A9SCU
pio_addr=520093696
pio_latency=1000
-platform=system.realview
system=system
pio=system.membus.port[5]
ignore_access=false
pio_addr=268451840
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[24]
min_backoff_delay=4000
pio_addr=268566528
pio_latency=10000
-platform=system.realview
system=system
vnc=system.vncserver
dma=system.iobus.port[6]
ignore_access=false
pio_addr=268632064
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[12]
pio_addr=1073741824
pio_latency=1000
pio_size=536870912
-platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
ignore_access=false
pio_addr=268513280
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[19]
ignore_access=false
pio_addr=268517376
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[20]
ignore_access=false
pio_addr=268521472
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[21]
is_mouse=false
pio_addr=268460032
pio_latency=1000
-platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[7]
is_mouse=true
pio_addr=268464128
pio_latency=1000
-platform=system.realview
system=system
vnc=system.vncserver
pio=system.iobus.port[8]
pio_addr=520101888
pio_latency=1000
pio_size=4095
-platform=system.realview
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
int_num_watchdog=30
pio_addr=520095232
pio_latency=1000
-platform=system.realview
system=system
pio=system.membus.port[6]
ignore_access=false
pio_addr=268455936
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[25]
idreg=0
pio_addr=268435456
pio_latency=1000
-platform=system.realview
proc_id0=201326592
proc_id1=201327138
system=system
ignore_access=false
pio_addr=268529664
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[26]
ignore_access=false
pio_addr=268492800
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[23]
ignore_access=false
pio_addr=269357056
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[16]
ignore_access=true
pio_addr=268439552
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[17]
ignore_access=false
pio_addr=268488704
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[22]
int_num1=36
pio_addr=268505088
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[3]
int_num1=37
pio_addr=268509184
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[4]
ignore_access=false
pio_addr=268476416
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[13]
ignore_access=false
pio_addr=268480512
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[14]
ignore_access=false
pio_addr=268484608
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[15]
ignore_access=false
pio_addr=268500992
pio_latency=1000
-platform=system.realview
system=system
pio=system.iobus.port[18]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:37:03
gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
info: Using bootloader at address 0x80000000
sim_ticks 2591441692000 # Number of ticks simulated
final_tick 2591441692000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 852555 # Simulator instruction rate (inst/s)
-host_tick_rate 29271571690 # Simulator tick rate (ticks/s)
-host_mem_usage 379496 # Number of bytes of host memory used
-host_seconds 88.53 # Real time elapsed on the host
-sim_insts 75477515 # Number of instructions simulated
+host_inst_rate 874833 # Simulator instruction rate (inst/s)
+host_op_rate 1117723 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 38375829651 # Simulator tick rate (ticks/s)
+host_mem_usage 376612 # Number of bytes of host memory used
+host_seconds 67.53 # Real time elapsed on the host
+sim_insts 59075683 # Number of instructions simulated
+sim_ops 75477515 # Number of ops (including micro ops) simulated
system.nvmem.bytes_read 20 # Number of bytes read from this memory
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system.cpu.dcache.ReadReq_accesses::total 13538930 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 10208396 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 10208396 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10208396 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0 247593 # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247593 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247593 # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0 247592 # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data 247592 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247592 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 23747326 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 23747326 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23747326 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 23747326 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 23747326 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23747326 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.027222 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.024519 # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0 0.046249 # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.026060 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.026060 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813 # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1 inf # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total inf # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428 # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1 inf # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total inf # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511 # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1 inf # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total inf # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 24881.141283 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 24881.141283 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 inf # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total inf # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027222 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024519 # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046249 # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.026060 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.026060 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15864.036813 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428 # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511 # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 564388 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 368563 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 250302 # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses 11451 # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 618865 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 618865 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4741074500 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 8800219500 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency 151723500 # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 13541294000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 13541294000 # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000 # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 40367455500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.027222 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.024519 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0 0.046249 # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1 inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total inf # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.026060 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.026060 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645 # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511 # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 564388 # number of writebacks
+system.cpu.dcache.writebacks::total 564388 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368563 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 368563 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250302 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 250302 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11451 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 11451 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 618865 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 618865 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 618865 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 618865 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4741074500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4741074500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8800219500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8800219500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 151723500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 151723500 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13541294000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 13541294000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13541294000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 13541294000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40367455500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40367455500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027222 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024519 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046249 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026060 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs no_value # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.demand_misses::0 0 # number of demand (read+write) misses
-system.iocache.demand_misses::1 0 # number of demand (read+write) misses
-system.iocache.demand_misses::total 0 # number of demand (read+write) misses
-system.iocache.overall_misses::0 0 # number of overall misses
-system.iocache.overall_misses::1 0 # number of overall misses
-system.iocache.overall_misses::total 0 # number of overall misses
-system.iocache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency 0 # number of overall miss cycles
-system.iocache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::1 0 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 0 # number of demand (read+write) accesses
-system.iocache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::1 0 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 0 # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.iocache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.iocache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.iocache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.iocache.overall_avg_miss_latency::total no_value # average overall miss latency
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.writebacks 0 # number of writebacks
-system.iocache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits 0 # number of overall MSHR hits
-system.iocache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses 0 # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1341941439938 # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1341941439938 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
e820_table=system.e820_table
init_param=0
oem_revision=0
oem_table_id=
+[system.apicbridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
[system.bridge]
type=Bridge
delay=50000
system=system
tracer=system.cpu.tracer
width=1
+workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
-platform=system.pc
system=system
int_port=system.membus.port[7]
pio=system.membus.port[6]
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
type=IntrControl
sys=system
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
[system.iobus]
type=Bus
block_size=64
use_default_range=true
width=64
default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
[system.iocache]
type=BaseCache
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.membus.badaddr_responder]
type=IsaFake
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854779128
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776568
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776808
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776552
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776818
pio_latency=1000
pio_size=2
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854775936
pio_latency=1000
pio_size=1
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=1000
-platform=system.pc
system=system
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.port[2]
type=I8237
pio_addr=9223372036854775808
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[3]
int_latency=1000
pio_addr=4273995776
pio_latency=1000
-platform=system.pc
system=system
int_port=system.iobus.port[13]
pio=system.iobus.port[12]
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[7]
output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=1000
-platform=system.pc
slave=system.pc.south_bridge.pic2
system=system
pio=system.iobus.port[8]
output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=1000
-platform=system.pc
slave=Null
system=system
pio=system.iobus.port[9]
int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[10]
i8254=system.pc.south_bridge.pit
pio_addr=9223372036854775905
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[11]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:46
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:48
gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5112043255000 because m5_exit instruction encountered
sim_ticks 5112043255000 # Number of ticks simulated
final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 2850135 # Simulator instruction rate (inst/s)
-host_tick_rate 35611898535 # Simulator tick rate (ticks/s)
-host_mem_usage 353172 # Number of bytes of host memory used
-host_seconds 143.55 # Real time elapsed on the host
-sim_insts 409133277 # Number of instructions simulated
+host_inst_rate 1772716 # Simulator instruction rate (inst/s)
+host_op_rate 3629762 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 45353186641 # Simulator tick rate (ticks/s)
+host_mem_usage 350348 # Number of bytes of host memory used
+host_seconds 112.72 # Real time elapsed on the host
+sim_insts 199813913 # Number of instructions simulated
+sim_ops 409133277 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 15568704 # Number of bytes read from this memory
system.physmem.bytes_inst_read 972736 # Number of instructions bytes read from this memory
system.physmem.bytes_written 12232896 # Number of bytes written to this memory
system.l2c.sampled_refs 196390 # Sample count of references to valid blocks.
system.l2c.avg_refs 16.968573 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 9701.563280 # Average occupied blocks per context
-system.l2c.occ_blocks::1 27141.380805 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.148034 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.414145 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2042917 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 9538 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 27139.322665 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 2.054559 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 0.003581 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 1828.819855 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 7872.743425 # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks 0.414113 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker 0.000031 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst 0.027906 # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data 0.120129 # Average percentage of cache occupancy
+system.l2c.occ_percent::total 0.562179 # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker 6729 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker 2809 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst 776101 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data 1266816 # number of ReadReq hits
system.l2c.ReadReq_hits::total 2052455 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1529403 # number of Writeback hits
+system.l2c.Writeback_hits::writebacks 1529403 # number of Writeback hits
system.l2c.Writeback_hits::total 1529403 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 31 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data 31 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0 168948 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data 168948 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 168948 # number of ReadExReq hits
-system.l2c.demand_hits::0 2211865 # number of demand (read+write) hits
-system.l2c.demand_hits::1 9538 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker 6729 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker 2809 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst 776101 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data 1435764 # number of demand (read+write) hits
system.l2c.demand_hits::total 2221403 # number of demand (read+write) hits
-system.l2c.overall_hits::0 2211865 # number of overall hits
-system.l2c.overall_hits::1 9538 # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker 6729 # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker 2809 # number of overall hits
+system.l2c.overall_hits::cpu.inst 776101 # number of overall hits
+system.l2c.overall_hits::cpu.data 1435764 # number of overall hits
system.l2c.overall_hits::total 2221403 # number of overall hits
-system.l2c.ReadReq_misses::0 55972 # number of ReadReq misses
-system.l2c.ReadReq_misses::1 27 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker 16 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker 11 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst 15200 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data 40772 # number of ReadReq misses
system.l2c.ReadReq_misses::total 55999 # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0 1792 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data 1792 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 1792 # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0 144639 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data 144639 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 144639 # number of ReadExReq misses
-system.l2c.demand_misses::0 200611 # number of demand (read+write) misses
-system.l2c.demand_misses::1 27 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker 16 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker 11 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst 15200 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data 185411 # number of demand (read+write) misses
system.l2c.demand_misses::total 200638 # number of demand (read+write) misses
-system.l2c.overall_misses::0 200611 # number of overall misses
-system.l2c.overall_misses::1 27 # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker 16 # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker 11 # number of overall misses
+system.l2c.overall_misses::cpu.inst 15200 # number of overall misses
+system.l2c.overall_misses::cpu.data 185411 # number of overall misses
system.l2c.overall_misses::total 200638 # number of overall misses
-system.l2c.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency 0 # number of overall miss cycles
-system.l2c.ReadReq_accesses::0 2098889 # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1 9565 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.dtb.walker 6745 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker 2820 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst 791301 # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data 1307588 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 2108454 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1529403 # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks 1529403 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 1529403 # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0 1823 # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data 1823 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 1823 # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0 313587 # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data 313587 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 313587 # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0 2412476 # number of demand (read+write) accesses
-system.l2c.demand_accesses::1 9565 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker 6745 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker 2820 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst 791301 # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data 1621175 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 2422041 # number of demand (read+write) accesses
-system.l2c.overall_accesses::0 2412476 # number of overall (read+write) accesses
-system.l2c.overall_accesses::1 9565 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker 6745 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker 2820 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst 791301 # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data 1621175 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 2422041 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.026667 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1 0.002823 # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total 0.029490 # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0 0.982995 # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0 0.461240 # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0 0.083156 # miss rate for demand accesses
-system.l2c.demand_miss_rate::1 0.002823 # miss rate for demand accesses
-system.l2c.demand_miss_rate::total 0.085978 # miss rate for demand accesses
-system.l2c.overall_miss_rate::0 0.083156 # miss rate for overall accesses
-system.l2c.overall_miss_rate::1 0.002823 # miss rate for overall accesses
-system.l2c.overall_miss_rate::total 0.085978 # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::0 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::1 0 # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 0 # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.002372 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.003901 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst 0.019209 # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data 0.031181 # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data 0.982995 # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data 0.461240 # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker 0.002372 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker 0.003901 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst 0.019209 # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data 0.114368 # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker 0.002372 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker 0.003901 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst 0.019209 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data 0.114368 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 144472 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks 144472 # number of writebacks
+system.l2c.writebacks::total 144472 # number of writebacks
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 47570 # number of replacements
system.iocache.tagsinuse 0.042409 # Cycle average of tags in use
system.iocache.sampled_refs 47586 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 4994776740009 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1 0.042409 # Average occupied blocks per context
-system.iocache.occ_percent::1 0.002651 # Average percentage of cache occupancy
-system.iocache.demand_hits::0 0 # number of demand (read+write) hits
-system.iocache.demand_hits::1 0 # number of demand (read+write) hits
-system.iocache.demand_hits::total 0 # number of demand (read+write) hits
-system.iocache.overall_hits::0 0 # number of overall hits
-system.iocache.overall_hits::1 0 # number of overall hits
-system.iocache.overall_hits::total 0 # number of overall hits
-system.iocache.ReadReq_misses::1 905 # number of ReadReq misses
+system.iocache.occ_blocks::pc.south_bridge.ide 0.042409 # Average occupied blocks per requestor
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system.cpu.dtb_walker_cache.sampled_refs 7767 # Sample count of references to valid blocks.
system.cpu.dtb_walker_cache.avg_refs 1.654950 # Average number of references to valid blocks.
system.cpu.dtb_walker_cache.warmup_cycle 5101232849000 # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1 5.010998 # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1 0.313187 # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1 12875 # number of ReadReq hits
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker 5.010998 # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker 0.313187 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total 0.313187 # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 12875 # number of ReadReq hits
system.cpu.dtb_walker_cache.ReadReq_hits::total 12875 # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0 0 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1 12875 # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 12875 # number of demand (read+write) hits
system.cpu.dtb_walker_cache.demand_hits::total 12875 # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0 0 # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1 12875 # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 12875 # number of overall hits
system.cpu.dtb_walker_cache.overall_hits::total 12875 # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1 8933 # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8933 # number of ReadReq misses
system.cpu.dtb_walker_cache.ReadReq_misses::total 8933 # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0 0 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1 8933 # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8933 # number of demand (read+write) misses
system.cpu.dtb_walker_cache.demand_misses::total 8933 # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0 0 # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1 8933 # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8933 # number of overall misses
system.cpu.dtb_walker_cache.overall_misses::total 8933 # number of overall misses
-system.cpu.dtb_walker_cache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1 21808 # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21808 # number of ReadReq accesses(hits+misses)
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21808 # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0 0 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1 21808 # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21808 # number of demand (read+write) accesses
system.cpu.dtb_walker_cache.demand_accesses::total 21808 # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0 0 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1 21808 # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21808 # number of overall (read+write) accesses
system.cpu.dtb_walker_cache.overall_accesses::total 21808 # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1 0.409620 # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0 no_value # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1 0.409620 # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0 no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1 0.409620 # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0 no_value # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0 no_value # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.409620 # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.409620 # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.409620 # miss rate for overall accesses
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks 2517 # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dtb_walker_cache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0 no_value # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0 no_value # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dtb_walker_cache.writebacks::writebacks 2517 # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total 2517 # number of writebacks
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 1621277 # number of replacements
system.cpu.dcache.tagsinuse 511.999417 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 1621789 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 12.419754 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 7549500 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 511.999417 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.999999 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0 12057024 # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data 511.999417 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.999999 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 12057024 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 12057024 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0 8082938 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 8082938 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 8082938 # number of WriteReq hits
-system.cpu.dcache.demand_hits::0 20139962 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1 0 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data 20139962 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 20139962 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0 20139962 # number of overall hits
-system.cpu.dcache.overall_hits::1 0 # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data 20139962 # number of overall hits
system.cpu.dcache.overall_hits::total 20139962 # number of overall hits
-system.cpu.dcache.ReadReq_misses::0 1308207 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data 1308207 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 1308207 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0 315850 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 315850 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 315850 # number of WriteReq misses
-system.cpu.dcache.demand_misses::0 1624057 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1 0 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data 1624057 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1624057 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0 1624057 # number of overall misses
-system.cpu.dcache.overall_misses::1 0 # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data 1624057 # number of overall misses
system.cpu.dcache.overall_misses::total 1624057 # number of overall misses
-system.cpu.dcache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0 13365231 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data 13365231 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13365231 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0 8398788 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 8398788 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 8398788 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0 21764019 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1 0 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data 21764019 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 21764019 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0 21764019 # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1 0 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 21764019 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 21764019 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0 0.097881 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0 0.037607 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0 0.074621 # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1 no_value # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total no_value # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0 0.074621 # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1 no_value # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total no_value # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 0 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1 no_value # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total no_value # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097881 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037607 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.074621 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.074621 # miss rate for overall accesses
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 1525559 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 no_value # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total no_value # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 no_value # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total no_value # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 1525559 # number of writebacks
+system.cpu.dcache.writebacks::total 1525559 # number of writebacks
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
e820_table=system.e820_table
init_param=0
oem_revision=0
oem_table_id=
+[system.apicbridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
[system.bridge]
type=Bridge
delay=50000
progress_interval=0
system=system
tracer=system.cpu.tracer
+workload=
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
int_latency=1000
pio_addr=2305843009213693952
pio_latency=1000
-platform=system.pc
system=system
int_port=system.membus.port[7]
pio=system.membus.port[6]
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
type=IntrControl
sys=system
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
[system.iobus]
type=Bus
block_size=64
use_default_range=true
width=64
default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
[system.iocache]
type=BaseCache
latency=50000
max_miss_count=0
mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=1024
subblock_size=0
+system=system
tgts_per_mshr=12
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
use_default_range=false
width=64
default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.membus.badaddr_responder]
type=IsaFake
pio_addr=0
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854779128
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776568
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776808
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776552
pio_latency=1000
pio_size=8
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854776818
pio_latency=1000
pio_size=2
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=9223372036854775936
pio_latency=1000
pio_size=1
-platform=system.pc
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
int_pin=system.pc.south_bridge.cmos.int_pin
pio_addr=9223372036854775920
pio_latency=1000
-platform=system.pc
system=system
time=Sun Jan 1 00:00:00 2012
pio=system.iobus.port[2]
type=I8237
pio_addr=9223372036854775808
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[3]
int_latency=1000
pio_addr=4273995776
pio_latency=1000
-platform=system.pc
system=system
int_port=system.iobus.port[13]
pio=system.iobus.port[12]
mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
pio_addr=0
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[7]
output=system.pc.south_bridge.pic1.output
pio_addr=9223372036854775840
pio_latency=1000
-platform=system.pc
slave=system.pc.south_bridge.pic2
system=system
pio=system.iobus.port[8]
output=system.pc.south_bridge.pic2.output
pio_addr=9223372036854775968
pio_latency=1000
-platform=system.pc
slave=Null
system=system
pio=system.iobus.port[9]
int_pin=system.pc.south_bridge.pit.int_pin
pio_addr=9223372036854775872
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[10]
i8254=system.pc.south_bridge.pit
pio_addr=9223372036854775905
pio_latency=1000
-platform=system.pc
system=system
pio=system.iobus.port[11]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:49
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:06:52
gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
- 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 5195470393000 because m5_exit instruction encountered
sim_ticks 5195470393000 # Number of ticks simulated
final_tick 5195470393000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1681123 # Simulator instruction rate (inst/s)
-host_tick_rate 32940960656 # Simulator tick rate (ticks/s)
-host_mem_usage 349824 # Number of bytes of host memory used
-host_seconds 157.72 # Real time elapsed on the host
-sim_insts 265147881 # Number of instructions simulated
+host_inst_rate 1225094 # Simulator instruction rate (inst/s)
+host_op_rate 2351489 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46076516791 # Simulator tick rate (ticks/s)
+host_mem_usage 346880 # Number of bytes of host memory used
+host_seconds 112.76 # Real time elapsed on the host
+sim_insts 138138472 # Number of instructions simulated
+sim_ops 265147881 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13764096 # Number of bytes read from this memory
system.physmem.bytes_inst_read 974400 # Number of instructions bytes read from this memory
system.physmem.bytes_written 10427072 # Number of bytes written to this memory
system.l2c.sampled_refs 168244 # Sample count of references to valid blocks.
system.l2c.avg_refs 19.991025 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 7910.895776 # Average occupied blocks per context
-system.l2c.occ_blocks::1 23478.999694 # Average occupied blocks per context
-system.l2c.occ_percent::0 0.120711 # Average percentage of cache occupancy
-system.l2c.occ_percent::1 0.358261 # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0 2047882 # number of ReadReq hits
-system.l2c.ReadReq_hits::1 9561 # number of ReadReq hits
+system.l2c.occ_blocks::writebacks 23478.740830 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker 0.248367 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker 0.010497 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst 1900.597036 # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data 6010.298740 # Average occupied blocks per requestor
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system.l2c.ReadReq_hits::total 2057443 # number of ReadReq hits
-system.l2c.Writeback_hits::0 1534567 # number of Writeback hits
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system.l2c.Writeback_hits::total 1534567 # number of Writeback hits
-system.l2c.UpgradeReq_hits::0 320 # number of UpgradeReq hits
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system.l2c.UpgradeReq_hits::total 320 # number of UpgradeReq hits
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system.l2c.ReadExReq_hits::total 192958 # number of ReadExReq hits
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system.l2c.demand_hits::total 2250401 # number of demand (read+write) hits
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system.l2c.overall_hits::total 2250401 # number of overall hits
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system.l2c.ReadReq_accesses::total 2108273 # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0 1534567 # number of Writeback accesses(hits+misses)
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system.l2c.Writeback_accesses::total 1534567 # number of Writeback accesses(hits+misses)
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system.l2c.UpgradeReq_accesses::total 1689 # number of UpgradeReq accesses(hits+misses)
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system.l2c.demand_accesses::total 2421399 # number of demand (read+write) accesses
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system.l2c.overall_accesses::total 2421399 # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0 0.024209 # miss rate for ReadReq accesses
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system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
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-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.l2c.ReadReq_mshr_miss_rate::0 0.024220 # mshr miss rate for ReadReq accesses
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system.iocache.blocked_cycles::no_mshrs 69564644 # number of cycles access was blocked
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system.iocache.blocked::no_mshrs 11299 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
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system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.dcache.WriteReq_mshr_uncacheable_latency 1379728500 # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 77305053000 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0 0.098647 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1 inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total inf # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0 0.037778 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1 inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total inf # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0 0.075163 # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1 inf # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total inf # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0 0.075163 # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1 inf # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total inf # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451 # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks 1529951 # number of writebacks
+system.cpu.dcache.writebacks::total 1529951 # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1310824 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 1310824 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315344 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 315344 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 1626168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 1626168 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 1626168 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 1626168 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 15919294500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 15919294500 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8568794500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8568794500 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 24488089000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 24488089000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 24488089000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 24488089000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 75925324500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 75925324500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1379728500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1379728500 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 77305053000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 77305053000 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098647 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037778 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075163 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451 # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
system=drivesys
tracer=drivesys.cpu.tracer
width=1
+workload=
dcache_port=drivesys.membus.port[4]
icache_port=drivesys.membus.port[3]
pio_addr=0
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
-platform=drivesys.tsunami
system=drivesys
tsunami=drivesys.tsunami
pio=drivesys.iobus.port[1]
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848432
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848304
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848569
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848451
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848515
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848579
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848643
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848707
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848771
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848835
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848899
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615850617
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848891
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848816
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848696
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848936
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848680
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848944
pio_latency=1000
pio_size=8
-platform=drivesys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
-platform=drivesys.tsunami
system=drivesys
pio=drivesys.iobus.port[22]
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
-platform=drivesys.tsunami
system=drivesys
time=Thu Jan 1 00:00:00 2009
tsunami=drivesys.tsunami
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
-platform=drivesys.tsunami
system=drivesys
tsunami=drivesys.tsunami
pio=drivesys.iobus.port[2]
[root]
type=Root
children=drivesys etherdump etherlink testsys
+full_system=true
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
system=testsys
tracer=testsys.cpu.tracer
width=1
+workload=
dcache_port=testsys.membus.port[4]
icache_port=testsys.membus.port[3]
pio_addr=0
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=true
ret_data16=65535
ret_data32=4294967295
type=TsunamiCChip
pio_addr=8803072344064
pio_latency=1000
-platform=testsys.tsunami
system=testsys
tsunami=testsys.tsunami
pio=testsys.iobus.port[1]
pio_addr=8796093677568
pio_latency=1000
pio_size=393216
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848432
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848304
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848569
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848451
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848515
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848579
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848643
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848707
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848771
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848835
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848899
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615850617
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848891
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848816
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848696
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848936
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848680
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
pio_addr=8804615848944
pio_latency=1000
pio_size=8
-platform=testsys.tsunami
ret_bad_addr=false
ret_data16=65535
ret_data32=4294967295
devicename=FrameBuffer
pio_addr=8804615848912
pio_latency=1000
-platform=testsys.tsunami
system=testsys
pio=testsys.iobus.port[22]
frequency=976562500
pio_addr=8804615847936
pio_latency=1000
-platform=testsys.tsunami
system=testsys
time=Thu Jan 1 00:00:00 2009
tsunami=testsys.tsunami
type=TsunamiPChip
pio_addr=8802535473152
pio_latency=1000
-platform=testsys.tsunami
system=testsys
tsunami=testsys.tsunami
pio=testsys.iobus.port[2]
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:23:10
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:02
gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
Global frequency set at 1000000000000 ticks per second
- 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
- 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: kernel located at: /dist/m5/system/binaries/vmlinux
info: Entering event queue @ 0. Starting simulation...
sim_ticks 200000789468 # Number of ticks simulated
final_tick 4300236018046 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 201516796 # Simulator instruction rate (inst/s)
-host_tick_rate 147427543497 # Simulator tick rate (ticks/s)
-host_mem_usage 479620 # Number of bytes of host memory used
-host_seconds 1.36 # Real time elapsed on the host
+host_inst_rate 238054601 # Simulator instruction rate (inst/s)
+host_op_rate 238047910 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 174152914765 # Simulator tick rate (ticks/s)
+host_mem_usage 476544 # Number of bytes of host memory used
+host_seconds 1.15 # Real time elapsed on the host
sim_insts 273374833 # Number of instructions simulated
+sim_ops 273374833 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read 19104208 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read 14257548 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written 3887982 # Number of bytes written to this memory
testsys.cpu.numCycles 199569460393 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.num_insts 3560411 # Number of instructions executed
+testsys.cpu.committedInsts 3560411 # Number of instructions committed
+testsys.cpu.committedOps 3560411 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 3348322 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses
testsys.cpu.num_func_calls 107994 # number of times a function call or return occured
drivesys.cpu.numCycles 199571362884 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-drivesys.cpu.num_insts 1958129 # Number of instructions executed
+drivesys.cpu.committedInsts 1958129 # Number of instructions committed
+drivesys.cpu.committedOps 1958129 # Number of ops (including micro ops) committed
drivesys.cpu.num_int_alu_accesses 1889973 # Number of integer alu accesses
drivesys.cpu.num_fp_alu_accesses 1278 # Number of float alu accesses
drivesys.cpu.num_func_calls 121650 # number of times a function call or return occured
sim_ticks 785978 # Number of ticks simulated
final_tick 4300236804024 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 864513825905 # Simulator instruction rate (inst/s)
-host_tick_rate 2363296319 # Simulator tick rate (ticks/s)
-host_mem_usage 479620 # Number of bytes of host memory used
+host_inst_rate 826237832724 # Simulator instruction rate (inst/s)
+host_op_rate 785322914063 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2155916043 # Simulator tick rate (ticks/s)
+host_mem_usage 476544 # Number of bytes of host memory used
host_seconds 0.00 # Real time elapsed on the host
sim_insts 273374833 # Number of instructions simulated
+sim_ops 273374833 # Number of ops (including micro ops) simulated
testsys.physmem.bytes_read 0 # Number of bytes read from this memory
testsys.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
testsys.physmem.bytes_written 0 # Number of bytes written to this memory
testsys.cpu.numCycles 0 # number of cpu cycles simulated
testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-testsys.cpu.num_insts 0 # Number of instructions executed
+testsys.cpu.committedInsts 0 # Number of instructions committed
+testsys.cpu.committedOps 0 # Number of ops (including micro ops) committed
testsys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses
testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
testsys.cpu.num_func_calls 0 # number of times a function call or return occured
drivesys.cpu.numCycles 0 # number of cpu cycles simulated
drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started
drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-drivesys.cpu.num_insts 0 # Number of instructions executed
+drivesys.cpu.committedInsts 0 # Number of instructions committed
+drivesys.cpu.committedOps 0 # Number of ops (including micro ops) committed
drivesys.cpu.num_int_alu_accesses 0 # Number of integer alu accesses
drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
drivesys.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 21216000 # Number of ticks simulated
final_tick 21216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 36015 # Simulator instruction rate (inst/s)
-host_tick_rate 119302866 # Simulator tick rate (ticks/s)
-host_mem_usage 207132 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 38129 # Simulator instruction rate (inst/s)
+host_op_rate 38124 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 126288909 # Simulator tick rate (ticks/s)
+host_mem_usage 209388 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30016 # Number of bytes read from this memory
system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 3265 # Number of Integer instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
-system.cpu.committedInsts 6404 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 6404 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 6404 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 6404 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 6404 # Number of Instructions committed (Total)
system.cpu.cpi 6.626015 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.626015 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 1.930233 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 138.882502 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.067814 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 581 # number of ReadReq hits
-system.cpu.icache.demand_hits 581 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 581 # number of overall hits
-system.cpu.icache.ReadReq_misses 348 # number of ReadReq misses
-system.cpu.icache.demand_misses 348 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 348 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 19241000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 19241000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 19241000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 929 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses 929 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.374596 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.374596 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.374596 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55290.229885 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55290.229885 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55290.229885 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.671807 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 10.136905 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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+system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5114000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 5114000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3910000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 3910000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9024000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 9024000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9024000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 9024000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080169 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081951 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 195.209568 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 195.209568 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.005957 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 1 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 1 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 1 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 396 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 73 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 469 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 469 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 20702000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 3822000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 24524000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 24524000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 397 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 73 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 470 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 470 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.997481 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.997872 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.997872 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52289.978678 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52289.978678 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 138.958412 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 56.251157 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004241 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001717 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005957 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
+system.cpu.l2cache.overall_misses::total 469 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15707000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4995000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 20702000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3822000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 3822000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 15707000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 8817000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 24524000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 15707000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 8817000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 24524000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 396 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 469 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 469 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15877000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2942500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 18819500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 18819500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997481 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.997872 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.997872 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12038500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3838500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15877000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2942500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2942500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12038500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18819500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12038500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18819500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 12004500 # Number of ticks simulated
final_tick 12004500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 38695 # Simulator instruction rate (inst/s)
-host_tick_rate 72731813 # Simulator tick rate (ticks/s)
-host_mem_usage 208040 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 42281 # Simulator instruction rate (inst/s)
+host_op_rate 42276 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 79460110 # Simulator tick rate (ticks/s)
+host_mem_usage 210060 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 6386 # Number of instructions simulated
+sim_ops 6386 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 31040 # Number of bytes read from this memory
system.physmem.bytes_inst_read 19904 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.736883 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 6403 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 6403 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 5259 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 381 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11614 # Number of insts commited each cycle
-system.cpu.commit.count 6403 # Number of instructions committed
+system.cpu.commit.committedInsts 6403 # Number of instructions committed
+system.cpu.commit.committedOps 6403 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2050 # Number of memory references committed
system.cpu.commit.loads 1185 # Number of loads committed
system.cpu.timesIdled 230 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11418 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 6386 # Number of Instructions Simulated
+system.cpu.committedOps 6386 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 6386 # Number of Instructions Simulated
system.cpu.cpi 3.759787 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.759787 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 312 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.147436 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 160.112304 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.078180 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1606 # number of ReadReq hits
-system.cpu.icache.demand_hits 1606 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1606 # number of overall hits
-system.cpu.icache.ReadReq_misses 433 # number of ReadReq misses
-system.cpu.icache.demand_misses 433 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 433 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15431000 # number of ReadReq miss cycles
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+system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
+system.cpu.l2cache.overall_hits::total 1 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 311 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 412 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 485 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses
+system.cpu.l2cache.overall_misses::total 485 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10665000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3498000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 14163000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2513500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2513500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 10665000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6011500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 16676500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 10665000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6011500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 16676500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 312 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 413 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 412 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 485 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 485 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12850000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2286000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 15136000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 15136000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997579 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.997942 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.997942 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 311 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 412 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 485 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 485 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9672000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3178000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12850000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2286000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2286000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9672000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5464000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15136000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9672000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5464000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15136000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 3215000 # Number of ticks simulated
final_tick 3215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 76916 # Simulator instruction rate (inst/s)
-host_tick_rate 38606134 # Simulator tick rate (ticks/s)
-host_mem_usage 198176 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 35037 # Simulator instruction rate (inst/s)
+host_op_rate 35032 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 17585099 # Simulator tick rate (ticks/s)
+host_mem_usage 199940 # Number of bytes of host memory used
+host_seconds 0.18 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 6696 # Number of bytes written to this memory
system.cpu.numCycles 6431 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
to_l2_latency=1
transitions_per_cycle=32
================ End RubySystem Configuration Print ================
-Real time: Jan/23/2012 04:21:55
+Real time: Feb/12/2012 15:33:22
Profiler Stats
--------------
-Elapsed_time_in_seconds: 2
-Elapsed_time_in_minutes: 0.0333333
-Elapsed_time_in_hours: 0.000555556
-Elapsed_time_in_days: 2.31481e-05
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.38
-Virtual_time_in_minutes: 0.00633333
-Virtual_time_in_hours: 0.000105556
-Virtual_time_in_days: 4.39815e-06
+Virtual_time_in_seconds: 1.01
+Virtual_time_in_minutes: 0.0168333
+Virtual_time_in_hours: 0.000280556
+Virtual_time_in_days: 1.16898e-05
Ruby_current_time: 279353
Ruby_start_time: 0
Ruby_cycles: 279353
-mbytes_resident: 45.5547
-mbytes_total: 214.371
-resident_ratio: 0.212504
+mbytes_resident: 0
+mbytes_total: 0
ruby_cycles_executed: [ 279354 ]
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 20 count: 9645 average: 0.064282 | standard deviation: 0.540462 | 9495 0 1 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ]
+Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 2725 average: 0.226789 | standard deviation: 0.997795 | 2576 0 0 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average: 0 | standard deviation: 0 | 1041 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11862
-page_faults: 127
+page_reclaims: 13214
+page_faults: 148
swaps: 0
-block_inputs: 22816
-block_outputs: 96
+block_inputs: 2
+block_outputs: 4
Network Stats
-------------
M_I Fwd_GET_INSTR [0 ] 0
M_I WB_Ack [436 ] 436
-E_I Load [0 ] 0
-E_I Ifetch [0 ] 0
-E_I Store [0 ] 0
-E_I L1_Replacement [0 ] 0
-
SINK_WB_ACK Load [0 ] 0
SINK_WB_ACK Ifetch [0 ] 0
SINK_WB_ACK Store [0 ] 0
--- L2Cache ---
- Event Counts -
L1_GET_INSTR [691 ] 691
-L1_GETS [586 ] 586
+L1_GETS [585 ] 585
L1_GETX [216 ] 216
L1_UPGRADE [0 ] 0
L1_PUTX [436 ] 436
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
-M_I L1_GETS [3 ] 3
+M_I L1_GETS [2 ] 2
M_I L1_GETX [0 ] 0
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:44:57
-gem5 started Jan 23 2012 04:21:53
-gem5 executing on zizzer
-command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 279353 # Number of ticks simulated
final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 2836 # Simulator instruction rate (inst/s)
-host_tick_rate 123728 # Simulator tick rate (ticks/s)
-host_mem_usage 219520 # Number of bytes of host memory used
-host_seconds 2.26 # Real time elapsed on the host
+host_inst_rate 12170 # Simulator instruction rate (inst/s)
+host_op_rate 12169 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 530781 # Simulator tick rate (ticks/s)
+host_mem_usage 270088 # Number of bytes of host memory used
+host_seconds 0.53 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 6696 # Number of bytes written to this memory
system.cpu.numCycles 279353 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
recycle_latency=10
request_latency=2
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:47:36
-gem5 started Jan 23 2012 04:22:12
+gem5 compiled Feb 11 2012 13:06:37
+gem5 started Feb 11 2012 13:53:23
gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 223694 # Number of ticks simulated
final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 19611 # Simulator instruction rate (inst/s)
-host_tick_rate 684980 # Simulator tick rate (ticks/s)
-host_mem_usage 219636 # Number of bytes of host memory used
-host_seconds 0.33 # Real time elapsed on the host
+host_inst_rate 37589 # Simulator instruction rate (inst/s)
+host_op_rate 37585 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1312743 # Simulator tick rate (ticks/s)
+host_mem_usage 221408 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 6696 # Number of bytes written to this memory
system.cpu.numCycles 223694 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
recycle_latency=10
retry_threshold=1
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:50:16
-gem5 started Jan 23 2012 04:22:25
+gem5 compiled Feb 11 2012 13:07:02
+gem5 started Feb 11 2012 13:54:08
gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 231701 # Number of ticks simulated
final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 23819 # Simulator instruction rate (inst/s)
-host_tick_rate 861729 # Simulator tick rate (ticks/s)
-host_mem_usage 217800 # Number of bytes of host memory used
-host_seconds 0.27 # Real time elapsed on the host
+host_inst_rate 59077 # Simulator instruction rate (inst/s)
+host_op_rate 59067 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2136733 # Simulator tick rate (ticks/s)
+host_mem_usage 219660 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 6696 # Number of bytes written to this memory
system.cpu.numCycles 231701 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:42:19
-gem5 started Jan 23 2012 04:21:43
+gem5 compiled Feb 11 2012 13:05:44
+gem5 started Feb 11 2012 13:52:39
gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 208400 # Number of ticks simulated
final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 24253 # Simulator instruction rate (inst/s)
-host_tick_rate 789193 # Simulator tick rate (ticks/s)
-host_mem_usage 217184 # Number of bytes of host memory used
-host_seconds 0.26 # Real time elapsed on the host
+host_inst_rate 64619 # Simulator instruction rate (inst/s)
+host_op_rate 64607 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2102096 # Simulator tick rate (ticks/s)
+host_mem_usage 218760 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 6696 # Number of bytes written to this memory
system.cpu.numCycles 208400 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 342698 # Number of ticks simulated
final_tick 342698 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 32385 # Simulator instruction rate (inst/s)
-host_tick_rate 1732860 # Simulator tick rate (ticks/s)
-host_mem_usage 218476 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
+host_inst_rate 61504 # Simulator instruction rate (inst/s)
+host_op_rate 61493 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3290073 # Simulator tick rate (ticks/s)
+host_mem_usage 220236 # Number of bytes of host memory used
+host_seconds 0.10 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 34460 # Number of bytes read from this memory
system.physmem.bytes_inst_read 25656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 6696 # Number of bytes written to this memory
system.cpu.numCycles 342698 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 33007000 # Number of ticks simulated
final_tick 33007000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 110064 # Simulator instruction rate (inst/s)
-host_tick_rate 566999999 # Simulator tick rate (ticks/s)
-host_mem_usage 206896 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 37663 # Simulator instruction rate (inst/s)
+host_op_rate 37658 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 194071847 # Simulator tick rate (ticks/s)
+host_mem_usage 209060 # Number of bytes of host memory used
+host_seconds 0.17 # Real time elapsed on the host
sim_insts 6404 # Number of instructions simulated
+sim_ops 6404 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 28544 # Number of bytes read from this memory
system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 66014 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 6404 # Number of instructions executed
+system.cpu.committedInsts 6404 # Number of instructions committed
+system.cpu.committedOps 6404 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 6331 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses
system.cpu.num_func_calls 251 # number of times a function call or return occured
system.cpu.icache.sampled_refs 279 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 21.992832 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 127.883393 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.062443 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 6136 # number of ReadReq hits
-system.cpu.icache.demand_hits 6136 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 6136 # number of overall hits
-system.cpu.icache.ReadReq_misses 279 # number of ReadReq misses
-system.cpu.icache.demand_misses 279 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 279 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15582000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 15582000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 15582000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 6415 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 6415 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 6415 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.043492 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.043492 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.043492 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55849.462366 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55849.462366 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55849.462366 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 127.883393 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.062443 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.062443 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 6136 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 6136 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 6136 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 6136 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 6136 # number of overall hits
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+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996416 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996416 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 373 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 73 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 446 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 446 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 14920000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2920000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 17840000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 17840000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.997326 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.997763 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.997763 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 373 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3800000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14920000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2920000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6720000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17840000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6720000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17840000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996416 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:23
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 6833000 # Number of ticks simulated
final_tick 6833000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 46364 # Simulator instruction rate (inst/s)
-host_tick_rate 132671945 # Simulator tick rate (ticks/s)
-host_mem_usage 207164 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 16400 # Simulator instruction rate (inst/s)
+host_op_rate 16398 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 46934615 # Simulator tick rate (ticks/s)
+host_mem_usage 209144 # Number of bytes of host memory used
+host_seconds 0.15 # Real time elapsed on the host
sim_insts 2387 # Number of instructions simulated
+sim_ops 2387 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 17280 # Number of bytes read from this memory
system.physmem.bytes_inst_read 11840 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.786143 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 2576 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 2416 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 149 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 5960 # Number of insts commited each cycle
-system.cpu.commit.count 2576 # Number of instructions committed
+system.cpu.commit.committedInsts 2576 # Number of instructions committed
+system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 709 # Number of memory references committed
system.cpu.commit.loads 415 # Number of loads committed
system.cpu.timesIdled 139 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7284 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 2387 # Number of Instructions Simulated
+system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 2387 # Number of Instructions Simulated
system.cpu.cpi 5.725597 # CPI: Cycles Per Instruction
system.cpu.cpi_total 5.725597 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 185 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3.783784 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 91.574139 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.044714 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 700 # number of ReadReq hits
-system.cpu.icache.demand_hits 700 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 700 # number of overall hits
-system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
-system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 241 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 8777500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 8777500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 8777500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 941 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 941 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 941 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.256111 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.256111 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.256111 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36421.161826 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36421.161826 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36421.161826 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 91.574139 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.044714 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.044714 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 700 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 700 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 700 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 700 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 700 # number of overall hits
+system.cpu.icache.overall_hits::total 700 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses
+system.cpu.icache.overall_misses::total 241 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 8777500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 8777500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 8777500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 8777500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 8777500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 8777500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 941 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 941 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 941 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 941 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 941 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 941 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.256111 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.256111 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.256111 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 185 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 185 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 185 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 6554500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 6554500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 6554500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.196599 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.196599 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.196599 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 185 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 185 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 185 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 185 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 185 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 185 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 6554500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 6554500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 6554500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 6554500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 6554500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 6554500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.196599 # mshr miss rate for overall accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7661500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 756000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 756000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5756000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 2661500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 8417500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5756000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 2661500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 8417500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31500 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 1297500 # Number of ticks simulated
final_tick 1297500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 182014 # Simulator instruction rate (inst/s)
-host_tick_rate 91451888 # Simulator tick rate (ticks/s)
-host_mem_usage 197324 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 24554 # Simulator instruction rate (inst/s)
+host_op_rate 24550 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 12358328 # Simulator tick rate (ticks/s)
+host_mem_usage 199092 # Number of bytes of host memory used
+host_seconds 0.11 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2058 # Number of bytes written to this memory
system.cpu.numCycles 2596 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
env=
errout=cerr
euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
gid=100
input=cin
max_stack_size=67108864
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
to_l2_latency=1
transitions_per_cycle=32
================ End RubySystem Configuration Print ================
-Real time: Jan/23/2012 04:21:58
+Real time: Feb/12/2012 15:33:21
Profiler Stats
--------------
-Elapsed_time_in_seconds: 2
-Elapsed_time_in_minutes: 0.0333333
-Elapsed_time_in_hours: 0.000555556
-Elapsed_time_in_days: 2.31481e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours: 7.22222e-05
-Virtual_time_in_days: 3.00926e-06
+Virtual_time_in_seconds: 0.71
+Virtual_time_in_minutes: 0.0118333
+Virtual_time_in_hours: 0.000197222
+Virtual_time_in_days: 8.21759e-06
Ruby_current_time: 104867
Ruby_start_time: 0
Ruby_cycles: 104867
-mbytes_resident: 43.0078
-mbytes_total: 212.113
-resident_ratio: 0.202759
+mbytes_resident: 0
+mbytes_total: 0
ruby_cycles_executed: [ 104868 ]
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0636766 | standard deviation: 0.653474 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.235537 | standard deviation: 1.24505 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average: 0 | standard deviation: 0 | 431 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11317
-page_faults: 0
+page_reclaims: 12663
+page_faults: 71
swaps: 0
block_inputs: 0
-block_outputs: 88
+block_outputs: 0
Network Stats
-------------
M_I Fwd_GET_INSTR [0 ] 0
M_I WB_Ack [124 ] 124
-E_I Load [0 ] 0
-E_I Ifetch [0 ] 0
-E_I Store [0 ] 0
-E_I L1_Replacement [0 ] 0
-
SINK_WB_ACK Load [0 ] 0
SINK_WB_ACK Ifetch [0 ] 0
SINK_WB_ACK Store [0 ] 0
--- L2Cache ---
- Event Counts -
L1_GET_INSTR [300 ] 300
-L1_GETS [206 ] 206
-L1_GETX [70 ] 70
+L1_GETS [205 ] 205
+L1_GETX [69 ] 69
L1_UPGRADE [0 ] 0
L1_PUTX [124 ] 124
L1_PUTX_old [0 ] 0
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
-M_I L1_GETS [2 ] 2
-M_I L1_GETX [2 ] 2
+M_I L1_GETS [1 ] 1
+M_I L1_GETX [1 ] 1
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
M_I L1_PUTX_old [0 ] 0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:44:57
-gem5 started Jan 23 2012 04:21:56
-gem5 executing on zizzer
-command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 104867 # Number of ticks simulated
final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 1196 # Simulator instruction rate (inst/s)
-host_tick_rate 48657 # Simulator tick rate (ticks/s)
-host_mem_usage 217208 # Number of bytes of host memory used
-host_seconds 2.16 # Real time elapsed on the host
+host_inst_rate 10837 # Simulator instruction rate (inst/s)
+host_op_rate 10836 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 440871 # Simulator tick rate (ticks/s)
+host_mem_usage 267756 # Number of bytes of host memory used
+host_seconds 0.24 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2058 # Number of bytes written to this memory
system.cpu.numCycles 104867 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
recycle_latency=10
request_latency=2
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:47:36
-gem5 started Jan 23 2012 04:22:12
+gem5 compiled Feb 11 2012 13:06:37
+gem5 started Feb 11 2012 13:53:34
gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 85418 # Number of ticks simulated
final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 13096 # Simulator instruction rate (inst/s)
-host_tick_rate 434048 # Simulator tick rate (ticks/s)
-host_mem_usage 217400 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
+host_inst_rate 37008 # Simulator instruction rate (inst/s)
+host_op_rate 36998 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1226055 # Simulator tick rate (ticks/s)
+host_mem_usage 219168 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2058 # Number of bytes written to this memory
system.cpu.numCycles 85418 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
recycle_latency=10
retry_threshold=1
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:50:16
-gem5 started Jan 23 2012 04:22:25
+gem5 compiled Feb 11 2012 13:07:02
+gem5 started Feb 11 2012 13:54:19
gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 87899 # Number of ticks simulated
final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 12702 # Simulator instruction rate (inst/s)
-host_tick_rate 433208 # Simulator tick rate (ticks/s)
-host_mem_usage 216416 # Number of bytes of host memory used
-host_seconds 0.20 # Real time elapsed on the host
+host_inst_rate 58227 # Simulator instruction rate (inst/s)
+host_op_rate 58203 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1984496 # Simulator tick rate (ticks/s)
+host_mem_usage 218264 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2058 # Number of bytes written to this memory
system.cpu.numCycles 87899 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:42:19
-gem5 started Jan 23 2012 04:21:49
+gem5 compiled Feb 11 2012 13:05:44
+gem5 started Feb 11 2012 13:52:40
gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 78448 # Number of ticks simulated
final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 29294 # Simulator instruction rate (inst/s)
-host_tick_rate 891567 # Simulator tick rate (ticks/s)
-host_mem_usage 215964 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 53931 # Simulator instruction rate (inst/s)
+host_op_rate 53912 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1640583 # Simulator tick rate (ticks/s)
+host_mem_usage 217556 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2058 # Number of bytes written to this memory
system.cpu.numCycles 78448 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=AlphaTLB
size=64
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 123378 # Number of ticks simulated
final_tick 123378 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 44691 # Simulator instruction rate (inst/s)
-host_tick_rate 2138947 # Simulator tick rate (ticks/s)
-host_mem_usage 216404 # Number of bytes of host memory used
-host_seconds 0.06 # Real time elapsed on the host
+host_inst_rate 35379 # Simulator instruction rate (inst/s)
+host_op_rate 35370 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1692995 # Simulator tick rate (ticks/s)
+host_mem_usage 218176 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 13356 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10340 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2058 # Number of bytes written to this memory
system.cpu.numCycles 123378 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 16769000 # Number of ticks simulated
final_tick 16769000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 297044 # Simulator instruction rate (inst/s)
-host_tick_rate 1928782837 # Simulator tick rate (ticks/s)
-host_mem_usage 206044 # Number of bytes of host memory used
-host_seconds 0.01 # Real time elapsed on the host
+host_inst_rate 142484 # Simulator instruction rate (inst/s)
+host_op_rate 142326 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 925222654 # Simulator tick rate (ticks/s)
+host_mem_usage 208204 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
sim_insts 2577 # Number of instructions simulated
+sim_ops 2577 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 15680 # Number of bytes read from this memory
system.physmem.bytes_inst_read 10432 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 33538 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 2577 # Number of instructions executed
+system.cpu.committedInsts 2577 # Number of instructions committed
+system.cpu.committedOps 2577 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 2375 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 6 # Number of float alu accesses
system.cpu.num_func_calls 140 # number of times a function call or return occured
system.cpu.icache.sampled_refs 163 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 14.865031 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 80.003762 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.039064 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 2423 # number of ReadReq hits
-system.cpu.icache.demand_hits 2423 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 2423 # number of overall hits
-system.cpu.icache.ReadReq_misses 163 # number of ReadReq misses
-system.cpu.icache.demand_misses 163 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 163 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 9128000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 9128000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 9128000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 2586 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 2586 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 2586 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.063032 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.063032 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.063032 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 80.003762 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.039064 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.039064 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 2423 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 2423 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 2423 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 2423 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 2423 # number of overall hits
+system.cpu.icache.overall_hits::total 2423 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 163 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 163 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 163 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 163 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 163 # number of overall misses
+system.cpu.icache.overall_misses::total 163 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 9128000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 9128000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 9128000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 9128000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 9128000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 9128000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 2586 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 2586 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 2586 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 2586 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 2586 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 2586 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.063032 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.063032 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.063032 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 56000 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 56000 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 56000 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 163 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 163 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 163 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 8639000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 8639000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 8639000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.063032 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.063032 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.063032 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 163 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 163 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 163 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 163 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 163 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 8639000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 8639000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 8639000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 8639000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 8639000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 8639000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063032 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53000 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53000 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 47.418751 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 82 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 7.646341 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 47.418751 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.011577 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 360 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 267 # number of WriteReq hits
-system.cpu.dcache.demand_hits 627 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 627 # number of overall hits
-system.cpu.dcache.ReadReq_misses 55 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 27 # number of WriteReq misses
-system.cpu.dcache.demand_misses 82 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 82 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 3080000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 1512000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 4592000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 4592000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 415 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 294 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 709 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 709 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.132530 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.091837 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.115656 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.115656 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
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system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu.dcache.ReadReq_mshr_miss_latency 2915000 # number of ReadReq MSHR miss cycles
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-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 107.101205 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 218 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 107.101205 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.003268 # Average percentage of cache occupancy
-system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits
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-system.cpu.l2cache.ReadReq_miss_latency 11336000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 1404000 # number of ReadExReq miss cycles
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-system.cpu.l2cache.ReadReq_accesses 218 # number of ReadReq accesses(hits+misses)
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-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
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-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
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+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 218 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 27 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 245 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 245 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 8720000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1080000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 9800000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 9800000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
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+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1080000 # number of ReadExReq MSHR miss cycles
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+system.cpu.l2cache.overall_mshr_miss_latency::total 9800000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
gid=100
input=cin
max_stack_size=67108864
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 07:27:01
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:35:50
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 10000500 # Number of ticks simulated
final_tick 10000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
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-host_tick_rate 85336508 # Simulator tick rate (ticks/s)
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-sim_insts 5739 # Number of instructions simulated
+host_inst_rate 72927 # Simulator instruction rate (inst/s)
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+host_tick_rate 158457261 # Simulator tick rate (ticks/s)
+host_mem_usage 221260 # Number of bytes of host memory used
+host_seconds 0.06 # Real time elapsed on the host
+sim_insts 4600 # Number of instructions simulated
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system.physmem.bytes_read 25856 # Number of bytes read from this memory
system.physmem.bytes_inst_read 17856 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_rate 0.391961 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.506103 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 5739 # The number of committed instructions
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system.cpu.commit.commitSquashedInsts 5094 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted
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system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
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system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2139 # Number of memory references committed
system.cpu.commit.loads 1201 # Number of loads committed
system.cpu.rob.rob_writes 22566 # The number of ROB writes
system.cpu.timesIdled 180 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8494 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 5739 # Number of Instructions Simulated
-system.cpu.committedInsts_total 5739 # Number of Instructions Simulated
-system.cpu.cpi 3.485276 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.485276 # CPI: Total CPI of All Threads
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-system.cpu.ipc_total 0.286921 # IPC: Total IPC of All Threads
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-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 3230000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 1505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 4735000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 4735000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.059861 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.046002 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.055316 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.055316 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data 262 # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total 262 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 319 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 319 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 319 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 319 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 112 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 112 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 154 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 154 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 154 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 154 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3230000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 3230000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 1505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4735000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 4735000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4735000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 4735000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059861 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055316 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 188.110462 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 362 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.116022 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 188.110462 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.005741 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 42 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 42 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 42 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 367 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 42 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 409 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 409 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 12613500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 1452000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 14065500 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 14065500 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 409 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 42 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 451 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 451 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.897311 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.906874 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.906874 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34389.975550 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34389.975550 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 140.315748 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 47.794714 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004282 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001459 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005741 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 24 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 42 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 18 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 24 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 42 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 18 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 24 # number of overall hits
+system.cpu.l2cache.overall_hits::total 42 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 279 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 88 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 367 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 279 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 130 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 409 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 279 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 130 # number of overall misses
+system.cpu.l2cache.overall_misses::total 409 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 9586000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3027500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 12613500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1452000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 1452000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 9586000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 4479500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 14065500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 9586000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 4479500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 14065500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 297 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 112 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 409 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 154 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 451 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 154 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 451 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.939394 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.785714 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.939394 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.844156 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.939394 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.844156 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits 5 # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits 5 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 5 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 362 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 42 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 404 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 404 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 11304000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1319000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 12623000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 12623000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.885086 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.895787 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.895787 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 279 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 83 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 362 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 279 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 404 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 279 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 404 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8692000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2612000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11304000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1319000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1319000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8692000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3931000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 12623000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8692000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3931000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 12623000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.741071 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.939394 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.811688 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31448 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:36:01
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 2875500 # Number of ticks simulated
final_tick 2875500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 25921 # Simulator instruction rate (inst/s)
-host_tick_rate 12986430 # Simulator tick rate (ticks/s)
-host_mem_usage 208728 # Number of bytes of host memory used
-host_seconds 0.22 # Real time elapsed on the host
-sim_insts 5739 # Number of instructions simulated
+host_inst_rate 866385 # Simulator instruction rate (inst/s)
+host_op_rate 1077395 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 538148768 # Simulator tick rate (ticks/s)
+host_mem_usage 211284 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 4600 # Number of instructions simulated
+sim_ops 5739 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 22944 # Number of bytes read from this memory
system.physmem.bytes_inst_read 18452 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3648 # Number of bytes written to this memory
system.cpu.numCycles 5752 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5739 # Number of instructions executed
+system.cpu.committedInsts 4600 # Number of instructions committed
+system.cpu.committedOps 5739 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=ArmInterrupts
+
[system.cpu.itb]
type=ArmTLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:36:11
gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 26361000 # Number of ticks simulated
final_tick 26361000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 20483 # Simulator instruction rate (inst/s)
-host_tick_rate 95024596 # Simulator tick rate (ticks/s)
-host_mem_usage 217432 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
-sim_insts 5682 # Number of instructions simulated
+host_inst_rate 456104 # Simulator instruction rate (inst/s)
+host_op_rate 565540 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2619225899 # Simulator tick rate (ticks/s)
+host_mem_usage 220184 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
+sim_insts 4574 # Number of instructions simulated
+sim_ops 5682 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 22400 # Number of bytes read from this memory
system.physmem.bytes_inst_read 14400 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 52722 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5682 # Number of instructions executed
+system.cpu.committedInsts 4574 # Number of instructions committed
+system.cpu.committedOps 5682 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4985 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses
system.cpu.num_func_calls 185 # number of times a function call or return occured
system.cpu.icache.sampled_refs 241 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 18.145228 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 114.525744 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.055921 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 4373 # number of ReadReq hits
-system.cpu.icache.demand_hits 4373 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 4373 # number of overall hits
-system.cpu.icache.ReadReq_misses 241 # number of ReadReq misses
-system.cpu.icache.demand_misses 241 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 241 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 12824000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 12824000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 12824000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 4614 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 4614 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 4614 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.052232 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.052232 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.052232 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 53211.618257 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 53211.618257 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 53211.618257 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 114.525744 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.055921 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.055921 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 4373 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4373 # number of ReadReq hits
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+system.cpu.icache.demand_hits::total 4373 # number of demand (read+write) hits
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+system.cpu.icache.overall_hits::total 4373 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses
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+system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses
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+system.cpu.icache.ReadReq_miss_latency::cpu.inst 12824000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 12824000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 12824000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 12824000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 12824000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 12824000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 4614 # number of ReadReq accesses(hits+misses)
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+system.cpu.icache.overall_accesses::total 4614 # number of overall (read+write) accesses
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+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 241 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 241 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 241 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12101000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 12101000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 12101000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.052232 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.052232 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.052232 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses
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+system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses
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+system.cpu.icache.demand_mshr_miss_latency::total 12101000 # number of demand (read+write) MSHR miss cycles
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+system.cpu.icache.overall_mshr_miss_latency::total 12101000 # number of overall MSHR miss cycles
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 82.937979 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 13.765957 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 82.937979 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.020249 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1049 # number of ReadReq hits
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-system.cpu.dcache.StoreCondReq_hits 11 # number of StoreCondReq hits
-system.cpu.dcache.demand_hits 1919 # number of demand (read+write) hits
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-system.cpu.dcache.ReadReq_miss_latency 4816000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 2408000 # number of WriteReq miss cycles
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-system.cpu.dcache.ReadReq_accesses 1147 # number of ReadReq accesses(hits+misses)
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-system.cpu.dcache.StoreCondReq_accesses 11 # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 2060 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 2060 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.085440 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.047097 # miss rate for WriteReq accesses
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-system.cpu.dcache.overall_miss_rate 0.068447 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 51234.042553 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 51234.042553 # average overall miss latency
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+system.cpu.dcache.ReadReq_accesses::cpu.data 1147 # number of ReadReq accesses(hits+misses)
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+system.cpu.dcache.demand_accesses::cpu.data 2060 # number of demand (read+write) accesses
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+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 98 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 43 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 141 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 141 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 4522000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 2279000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 6801000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 6801000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.085440 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.047097 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.068447 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.068447 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4522000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 2279000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 6801000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 6801000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.085440 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.068447 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 153.954484 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 307 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.104235 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 153.954484 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.004698 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 32 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 32 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 32 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 307 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 43 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 350 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 350 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 15964000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2236000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 18200000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 18200000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 339 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 43 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 382 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 382 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.905605 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.916230 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.916230 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 105.806385 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 48.148099 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.003229 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.004698 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits
+system.cpu.l2cache.overall_hits::total 32 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses
+system.cpu.l2cache.overall_misses::total 350 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11700000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4264000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 15964000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2236000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2236000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 11700000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 6500000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 18200000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 11700000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 6500000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 18200000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 307 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 43 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 350 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 350 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 12280000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1720000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 14000000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 14000000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.905605 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.916230 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.916230 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9000000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1720000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1720000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 14000000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 14000000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:29
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:30
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 19785000 # Number of ticks simulated
final_tick 19785000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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system.cpu.cpi 6.790973 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.790973 # CPI: Total CPI of All Threads
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system.cpu.l2cache.tagsinuse 205.469583 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks.
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-system.cpu.l2cache.occ_blocks::0 205.469583 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.006270 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 404 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 51 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 455 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 455 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 21170500 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 2682500 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 23853000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 23853000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 406 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 51 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 457 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 457 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.995074 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.995624 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.995624 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52424.175824 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52424.175824 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 149.779235 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 55.690348 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004571 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.001700 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.006270 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 317 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 404 # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 317 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 455 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.l2cache.overall_misses::total 455 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16585500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4585000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 21170500 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2682500 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 2682500 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 16585500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7267500 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 23853000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 16585500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7267500 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 23853000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 319 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 457 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 319 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 457 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993730 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993730 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 404 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 455 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 455 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 16247000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2058000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 18305000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 18305000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.995074 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.995624 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.995624 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 317 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 404 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 317 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 455 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12717500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3529500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16247000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2058000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2058000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12717500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5587500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 18305000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12717500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5587500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 18305000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:41
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:39
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 12272500 # Number of ticks simulated
final_tick 12272500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 65845 # Simulator instruction rate (inst/s)
-host_tick_rate 156294886 # Simulator tick rate (ticks/s)
-host_mem_usage 208908 # Number of bytes of host memory used
-host_seconds 0.08 # Real time elapsed on the host
+host_inst_rate 97350 # Simulator instruction rate (inst/s)
+host_op_rate 97317 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 230983195 # Simulator tick rate (ticks/s)
+host_mem_usage 211060 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5169 # Number of instructions simulated
+sim_ops 5169 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30400 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21312 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.698936 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4197 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 357 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 11871 # Number of insts commited each cycle
-system.cpu.commit.count 5826 # Number of instructions committed
+system.cpu.commit.committedInsts 5826 # Number of instructions committed
+system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2089 # Number of memory references committed
system.cpu.commit.loads 1164 # Number of loads committed
system.cpu.timesIdled 251 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11938 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5169 # Number of Instructions Simulated
+system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5169 # Number of Instructions Simulated
system.cpu.cpi 4.748694 # CPI: Cycles Per Instruction
system.cpu.cpi_total 4.748694 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 336 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 4.056548 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 161.224498 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.078723 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1363 # number of ReadReq hits
-system.cpu.icache.demand_hits 1363 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1363 # number of overall hits
-system.cpu.icache.ReadReq_misses 418 # number of ReadReq misses
-system.cpu.icache.demand_misses 418 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 418 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15148000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 15148000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 15148000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1781 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1781 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1781 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.234700 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.234700 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.234700 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36239.234450 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36239.234450 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36239.234450 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 161.224498 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.078723 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.078723 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1363 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1363 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1363 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1363 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1363 # number of overall hits
+system.cpu.icache.overall_hits::total 1363 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 418 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 418 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 418 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 418 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 418 # number of overall misses
+system.cpu.icache.overall_misses::total 418 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15148000 # number of ReadReq miss cycles
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+system.cpu.l2cache.overall_miss_latency::cpu.data 4903000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 16321500 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 336 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 427 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 336 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 478 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 336 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 478 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991071 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991071 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991071 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 424 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 475 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 475 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13198000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 1598500 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 14796500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 14796500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.992974 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.993724 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.993724 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 424 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 475 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 475 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10340500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2857500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13198000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1598500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1598500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10340500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4456000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 14796500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10340500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4456000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 14796500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991071 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=MipsTLB
size=64
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:47
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:41
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 2913500 # Number of ticks simulated
final_tick 2913500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 231601 # Simulator instruction rate (inst/s)
-host_tick_rate 115720913 # Simulator tick rate (ticks/s)
-host_mem_usage 199128 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
+host_inst_rate 1078442 # Simulator instruction rate (inst/s)
+host_op_rate 1075012 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 535874927 # Simulator tick rate (ticks/s)
+host_mem_usage 200784 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27687 # Number of bytes read from this memory
system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3658 # Number of bytes written to this memory
system.cpu.numCycles 5828 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.committedInsts 5827 # Number of instructions committed
+system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=MipsTLB
size=64
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:56
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:52
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 292960 # Number of ticks simulated
final_tick 292960 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 55801 # Simulator instruction rate (inst/s)
-host_tick_rate 2804966 # Simulator tick rate (ticks/s)
-host_mem_usage 220172 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 71598 # Simulator instruction rate (inst/s)
+host_op_rate 71583 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3598224 # Simulator tick rate (ticks/s)
+host_mem_usage 221836 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27687 # Number of bytes read from this memory
system.physmem.bytes_inst_read 23312 # Number of instructions bytes read from this memory
system.physmem.bytes_written 3658 # Number of bytes written to this memory
system.cpu.numCycles 292960 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.committedInsts 5827 # Number of instructions committed
+system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=MipsInterrupts
+
[system.cpu.itb]
type=MipsTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:52
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:50
gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 32088000 # Number of ticks simulated
final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 263412 # Simulator instruction rate (inst/s)
-host_tick_rate 1449372115 # Simulator tick rate (ticks/s)
-host_mem_usage 207940 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 603210 # Simulator instruction rate (inst/s)
+host_op_rate 602100 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3309896144 # Simulator tick rate (ticks/s)
+host_mem_usage 209992 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5827 # Number of instructions simulated
+sim_ops 5827 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 28096 # Number of bytes read from this memory
system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 64176 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5827 # Number of instructions executed
+system.cpu.committedInsts 5827 # Number of instructions committed
+system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses
system.cpu.num_func_calls 194 # number of times a function call or return occured
system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 132.493866 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.064694 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 5526 # number of ReadReq hits
-system.cpu.icache.demand_hits 5526 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 5526 # number of overall hits
-system.cpu.icache.ReadReq_misses 303 # number of ReadReq misses
-system.cpu.icache.demand_misses 303 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 303 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 16884000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 16884000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 16884000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 5829 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 5829 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 5829 # number of overall (read+write) accesses
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+system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 390 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 388 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 51 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 439 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 439 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 15520000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 2040000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 17560000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 17560000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994872 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.995465 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.995465 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 439 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 439 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12040000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15520000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2040000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2040000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=PowerInterrupts
+
[system.cpu.itb]
type=PowerTLB
size=64
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:58:39
-gem5 started Jan 23 2012 04:24:00
+gem5 compiled Feb 11 2012 13:07:55
+gem5 started Feb 11 2012 13:55:01
gem5 executing on zizzer
-command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
+command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 10910500 # Number of ticks simulated
final_tick 10910500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 80565 # Simulator instruction rate (inst/s)
-host_tick_rate 151515044 # Simulator tick rate (ticks/s)
-host_mem_usage 205800 # Number of bytes of host memory used
-host_seconds 0.07 # Real time elapsed on the host
+host_inst_rate 114395 # Simulator instruction rate (inst/s)
+host_op_rate 114354 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 215042277 # Simulator tick rate (ticks/s)
+host_mem_usage 207892 # Number of bytes of host memory used
+host_seconds 0.05 # Real time elapsed on the host
sim_insts 5800 # Number of instructions simulated
+sim_ops 5800 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 28608 # Number of bytes read from this memory
system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.623674 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 5800 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 5800 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 4208 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 252 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 9777 # Number of insts commited each cycle
-system.cpu.commit.count 5800 # Number of instructions committed
+system.cpu.commit.committedInsts 5800 # Number of instructions committed
+system.cpu.commit.committedOps 5800 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 2008 # Number of memory references committed
system.cpu.commit.loads 962 # Number of loads committed
system.cpu.timesIdled 218 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 11389 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 5800 # Number of Instructions Simulated
+system.cpu.committedOps 5800 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 5800 # Number of Instructions Simulated
system.cpu.cpi 3.762414 # CPI: Cycles Per Instruction
system.cpu.cpi_total 3.762414 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 3.678063 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 169.539680 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.082783 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1291 # number of ReadReq hits
-system.cpu.icache.demand_hits 1291 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1291 # number of overall hits
-system.cpu.icache.ReadReq_misses 420 # number of ReadReq misses
-system.cpu.icache.demand_misses 420 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 420 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15114500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 15114500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 15114500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1711 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1711 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1711 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.245470 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.245470 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.245470 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35986.904762 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35986.904762 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35986.904762 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 169.539680 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.082783 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.082783 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1291 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1291 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1291 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1291 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1291 # number of overall hits
+system.cpu.icache.overall_hits::total 1291 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 420 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 420 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 420 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 420 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 420 # number of overall misses
+system.cpu.icache.overall_misses::total 420 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15114500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15114500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 15114500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15114500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 15114500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15114500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1711 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1711 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1711 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1711 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1711 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1711 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.245470 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.245470 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.245470 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 69 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 69 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 69 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 351 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 351 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 351 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 12207500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 12207500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 12207500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.205143 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.205143 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.205143 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses
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-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 48 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 48 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 103 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 447 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 103 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 447 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10708500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1725500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12434000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1526000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1526000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10708500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3251500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 13960000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10708500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3251500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 13960000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.964912 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.980057 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.980952 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
UnifiedTLB=true
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=PowerTLB
size=64
+[system.cpu.interrupts]
+type=PowerInterrupts
+
[system.cpu.itb]
type=PowerTLB
size=64
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 03:58:39
-gem5 started Jan 23 2012 04:24:03
+gem5 compiled Feb 11 2012 13:07:55
+gem5 started Feb 11 2012 13:55:02
gem5 executing on zizzer
-command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic
+command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 2900000 # Number of ticks simulated
final_tick 2900000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 305071 # Simulator instruction rate (inst/s)
-host_tick_rate 152367478 # Simulator tick rate (ticks/s)
-host_mem_usage 196296 # Number of bytes of host memory used
-host_seconds 0.02 # Real time elapsed on the host
+host_inst_rate 430782 # Simulator instruction rate (inst/s)
+host_op_rate 430227 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 214814147 # Simulator tick rate (ticks/s)
+host_mem_usage 197864 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5801 # Number of instructions simulated
+sim_ops 5801 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 26925 # Number of bytes read from this memory
system.physmem.bytes_inst_read 23204 # Number of instructions bytes read from this memory
system.physmem.bytes_written 4209 # Number of bytes written to this memory
system.cpu.numCycles 5801 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5801 # Number of instructions executed
+system.cpu.committedInsts 5801 # Number of instructions committed
+system.cpu.committedOps 5801 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 5706 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 22 # Number of float alu accesses
system.cpu.num_func_calls 200 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:09
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:12
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 18201500 because target called exit()
sim_ticks 18201500 # Number of ticks simulated
final_tick 18201500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 29731 # Simulator instruction rate (inst/s)
-host_tick_rate 101330259 # Simulator tick rate (ticks/s)
-host_mem_usage 213072 # Number of bytes of host memory used
-host_seconds 0.18 # Real time elapsed on the host
+host_inst_rate 71915 # Simulator instruction rate (inst/s)
+host_op_rate 71898 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 245008016 # Simulator tick rate (ticks/s)
+host_mem_usage 211144 # Number of bytes of host memory used
+host_seconds 0.07 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27072 # Number of bytes read from this memory
system.physmem.bytes_inst_read 18496 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.comNonSpec 106 # Number of Non-Speculative instructions committed
system.cpu.comInts 2537 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
-system.cpu.committedInsts 5340 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 5340 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 5340 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 5340 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 5340 # Number of Instructions committed (Total)
system.cpu.cpi 6.817228 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 6.817228 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 2.718213 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 136.669321 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.066733 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 791 # number of ReadReq hits
-system.cpu.icache.demand_hits 791 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 791 # number of overall hits
-system.cpu.icache.ReadReq_misses 347 # number of ReadReq misses
-system.cpu.icache.demand_misses 347 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 347 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 19110500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 19110500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 19110500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1138 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1138 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1138 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.304921 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.304921 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.304921 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55073.487032 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55073.487032 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55073.487032 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 136.669321 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.066733 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.066733 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 791 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 791 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 791 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 791 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 791 # number of overall hits
+system.cpu.icache.overall_hits::total 791 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 347 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 347 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 347 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 347 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 347 # number of overall misses
+system.cpu.icache.overall_misses::total 347 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 19110500 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 19110500 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 19110500 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 19110500 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 19110500 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 19110500 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1138 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1138 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1138 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1138 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1138 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1138 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.304921 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.304921 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.304921 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 104500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 56 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 56 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 56 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 291 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 291 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 291 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15470000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 15470000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 15470000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.255712 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.255712 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.255712 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 56 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 56 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 56 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 56 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 56 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 56 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15470000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 15470000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15470000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 15470000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15470000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 15470000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.255712 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
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+system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11603500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2143500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13747000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3255500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3255500 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11603500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5399000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17002500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11603500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5399000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17002500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:11
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:13
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 2701000 because target called exit()
sim_ticks 2701000 # Number of ticks simulated
final_tick 2701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 117056 # Simulator instruction rate (inst/s)
-host_tick_rate 59184907 # Simulator tick rate (ticks/s)
-host_mem_usage 203964 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 963329 # Simulator instruction rate (inst/s)
+host_op_rate 960313 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 484321069 # Simulator tick rate (ticks/s)
+host_mem_usage 201636 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 26135 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5065 # Number of bytes written to this memory
system.cpu.numCycles 5403 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.committedInsts 5340 # Number of instructions committed
+system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:20
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:24
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 253364 because target called exit()
sim_ticks 253364 # Number of ticks simulated
final_tick 253364 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 57666 # Simulator instruction rate (inst/s)
-host_tick_rate 2735530 # Simulator tick rate (ticks/s)
-host_mem_usage 224736 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
+host_inst_rate 70723 # Simulator instruction rate (inst/s)
+host_op_rate 70707 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3354080 # Simulator tick rate (ticks/s)
+host_mem_usage 222404 # Number of bytes of host memory used
+host_seconds 0.08 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 26135 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21532 # Number of instructions bytes read from this memory
system.physmem.bytes_written 5065 # Number of bytes written to this memory
system.cpu.numCycles 253364 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.committedInsts 5340 # Number of instructions committed
+system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:14
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:23
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello World!Exiting @ tick 28206000 because target called exit()
sim_ticks 28206000 # Number of ticks simulated
final_tick 28206000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 103151 # Simulator instruction rate (inst/s)
-host_tick_rate 544654705 # Simulator tick rate (ticks/s)
-host_mem_usage 212680 # Number of bytes of host memory used
-host_seconds 0.05 # Real time elapsed on the host
+host_inst_rate 534426 # Simulator instruction rate (inst/s)
+host_op_rate 533460 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2812998715 # Simulator tick rate (ticks/s)
+host_mem_usage 210748 # Number of bytes of host memory used
+host_seconds 0.01 # Real time elapsed on the host
sim_insts 5340 # Number of instructions simulated
+sim_ops 5340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 24896 # Number of bytes read from this memory
system.physmem.bytes_inst_read 16320 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 56412 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 5340 # Number of instructions executed
+system.cpu.committedInsts 5340 # Number of instructions committed
+system.cpu.committedOps 5340 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 4517 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 146 # number of times a function call or return occured
system.cpu.icache.sampled_refs 257 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 19.949416 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 116.975932 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.057117 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 5127 # number of ReadReq hits
-system.cpu.icache.demand_hits 5127 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 5127 # number of overall hits
-system.cpu.icache.ReadReq_misses 257 # number of ReadReq misses
-system.cpu.icache.demand_misses 257 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 257 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 14308000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 14308000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 14308000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 5384 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 5384 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 5384 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.047734 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.047734 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.047734 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55673.151751 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55673.151751 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55673.151751 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 116.975932 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.057117 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.057117 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 5127 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 5127 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 5127 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 5127 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 5127 # number of overall hits
+system.cpu.icache.overall_hits::total 5127 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 257 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 257 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 257 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 257 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 257 # number of overall misses
+system.cpu.icache.overall_misses::total 257 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 14308000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 14308000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 14308000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 14308000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 14308000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 14308000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 5384 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 5384 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 5384 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 5384 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 5384 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 5384 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.047734 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.047734 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.047734 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 257 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 257 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 257 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 13537000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 13537000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 13537000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.047734 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.047734 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.047734 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 257 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 257 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 257 # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total 257 # number of overall MSHR misses
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+system.cpu.l2cache.demand_mshr_misses::total 389 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 255 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 389 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10200000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12320000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3240000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10200000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 15560000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10200000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 15560000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992218 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.fuPool]
type=FUPool
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
env=
errout=cerr
euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
gid=100
input=cin
max_stack_size=67108864
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 28 2012 12:11:40
-gem5 started Jan 28 2012 12:11:57
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:05
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 11989500 # Number of ticks simulated
final_tick 11989500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1330 # Simulator instruction rate (inst/s)
-host_tick_rate 1625690 # Simulator tick rate (ticks/s)
-host_mem_usage 239860 # Number of bytes of host memory used
-host_seconds 7.38 # Real time elapsed on the host
-sim_insts 9809 # Number of instructions simulated
+host_inst_rate 61798 # Simulator instruction rate (inst/s)
+host_op_rate 111900 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 136747555 # Simulator tick rate (ticks/s)
+host_mem_usage 218292 # Number of bytes of host memory used
+host_seconds 0.09 # Real time elapsed on the host
+sim_insts 5416 # Number of instructions simulated
+sim_ops 9809 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 28288 # Number of bytes read from this memory
system.physmem.bytes_inst_read 18944 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_rate 0.651043 # insts written-back per cycle
system.cpu.iew.wb_fanout 0.677483 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts 9809 # The number of committed instructions
+system.cpu.commit.commitCommittedInsts 5416 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 9809 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 10533 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 495 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 14495 # Number of insts commited each cycle
-system.cpu.commit.count 9809 # Number of instructions committed
+system.cpu.commit.committedInsts 5416 # Number of instructions committed
+system.cpu.commit.committedOps 9809 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 1990 # Number of memory references committed
system.cpu.commit.loads 1056 # Number of loads committed
system.cpu.rob.rob_writes 42403 # The number of ROB writes
system.cpu.timesIdled 150 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7798 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts 9809 # Number of Instructions Simulated
-system.cpu.committedInsts_total 9809 # Number of Instructions Simulated
-system.cpu.cpi 2.444694 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 2.444694 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.409049 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.409049 # IPC: Total IPC of All Threads
+system.cpu.committedInsts 5416 # Number of Instructions Simulated
+system.cpu.committedOps 9809 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 5416 # Number of Instructions Simulated
+system.cpu.cpi 4.427622 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 4.427622 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.225855 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.225855 # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads 23430 # number of integer regfile reads
system.cpu.int_regfile_writes 14518 # number of integer regfile writes
system.cpu.fp_regfile_reads 4 # number of floating regfile reads
system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.026846 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 140.870525 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.068784 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 1498 # number of ReadReq hits
-system.cpu.icache.demand_hits 1498 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 1498 # number of overall hits
-system.cpu.icache.ReadReq_misses 368 # number of ReadReq misses
-system.cpu.icache.demand_misses 368 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 368 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 13394000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 13394000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 13394000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 1866 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 1866 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 1866 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.197213 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.197213 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.197213 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36396.739130 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36396.739130 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36396.739130 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 140.870525 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.068784 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.068784 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 1498 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 1498 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 1498 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 1498 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 1498 # number of overall hits
+system.cpu.icache.overall_hits::total 1498 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 368 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 368 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 368 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 368 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 368 # number of overall misses
+system.cpu.icache.overall_misses::total 368 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 13394000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 13394000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 13394000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 13394000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 13394000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 13394000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 1866 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 1866 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 1866 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 1866 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 1866 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 1866 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197213 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.197213 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.197213 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 70 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 70 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 70 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 298 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 298 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 298 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 10471500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 10471500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 10471500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.159700 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.159700 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.159700 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35139.261745 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35139.261745 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 70 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 70 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 70 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 70 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 70 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10471500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 10471500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10471500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 10471500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10471500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 10471500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.159700 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 83.526549 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 15.689655 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 83.526549 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.020392 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 1417 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 858 # number of WriteReq hits
-system.cpu.dcache.demand_hits 2275 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 2275 # number of overall hits
-system.cpu.dcache.ReadReq_misses 111 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 76 # number of WriteReq misses
-system.cpu.dcache.demand_misses 187 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 187 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 3859500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 2916500 # number of WriteReq miss cycles
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+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993289 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
[system.cpu.tracer]
type=ExeTracer
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:38
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:16
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 5651000 # Number of ticks simulated
final_tick 5651000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 225004 # Simulator instruction rate (inst/s)
-host_tick_rate 129531520 # Simulator tick rate (ticks/s)
-host_mem_usage 202604 # Number of bytes of host memory used
-host_seconds 0.04 # Real time elapsed on the host
-sim_insts 9810 # Number of instructions simulated
+host_inst_rate 364793 # Simulator instruction rate (inst/s)
+host_op_rate 659825 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 379660541 # Simulator tick rate (ticks/s)
+host_mem_usage 207748 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 5417 # Number of instructions simulated
+sim_ops 9810 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 62348 # Number of bytes read from this memory
system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7110 # Number of bytes written to this memory
system.cpu.numCycles 11303 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 9810 # Number of instructions executed
+system.cpu.committedInsts 5417 # Number of instructions committed
+system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000
time_sync_spin_threshold=100000
[system]
type=System
children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=1
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.l1_cntrl0.sequencer.port[3]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1
+pio_addr=2305843009213693952
+pio_latency=1
+system=system
+int_port=system.l1_cntrl0.sequencer.port[5]
+pio=system.l1_cntrl0.sequencer.port[4]
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.l1_cntrl0.sequencer.port[2]
[system.cpu.tracer]
type=ExeTracer
number_of_TBEs=256
recycle_latency=10
ruby_system=system.ruby
+send_evictions=false
sequencer=system.l1_cntrl0.sequencer
transitions_per_cycle=32
version=0
using_ruby_tester=false
version=0
physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+port=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:43
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:37
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 276484 # Number of ticks simulated
final_tick 276484 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_inst_rate 88128 # Simulator instruction rate (inst/s)
-host_tick_rate 2483404 # Simulator tick rate (ticks/s)
-host_mem_usage 223444 # Number of bytes of host memory used
+host_inst_rate 47191 # Simulator instruction rate (inst/s)
+host_op_rate 85448 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2407911 # Simulator tick rate (ticks/s)
+host_mem_usage 228676 # Number of bytes of host memory used
host_seconds 0.11 # Real time elapsed on the host
-sim_insts 9810 # Number of instructions simulated
+sim_insts 5417 # Number of instructions simulated
+sim_ops 9810 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 62348 # Number of bytes read from this memory
system.physmem.bytes_inst_read 55280 # Number of instructions bytes read from this memory
system.physmem.bytes_written 7110 # Number of bytes written to this memory
system.cpu.numCycles 276484 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 9810 # Number of instructions executed
+system.cpu.committedInsts 5417 # Number of instructions committed
+system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
[system.cpu.dtb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
[system.cpu.icache]
type=BaseCache
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
[system.cpu.itb]
type=X86TLB
+children=walker
size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
[system.cpu.l2cache]
type=BaseCache
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
mem_side=system.membus.port[2]
[system.cpu.toL2Bus]
header_cycles=1
use_default_range=false
width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
[system.cpu.tracer]
type=ExeTracer
header_cycles=1
use_default_range=false
width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
[system.physmem]
type=PhysicalMemory
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:38
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:26
gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Hello world!
sim_ticks 28768000 # Number of ticks simulated
final_tick 28768000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 320748 # Simulator instruction rate (inst/s)
-host_tick_rate 940055576 # Simulator tick rate (ticks/s)
-host_mem_usage 211332 # Number of bytes of host memory used
-host_seconds 0.03 # Real time elapsed on the host
-sim_insts 9810 # Number of instructions simulated
+host_inst_rate 265683 # Simulator instruction rate (inst/s)
+host_op_rate 480724 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1408532008 # Simulator tick rate (ticks/s)
+host_mem_usage 216996 # Number of bytes of host memory used
+host_seconds 0.02 # Real time elapsed on the host
+sim_insts 5417 # Number of instructions simulated
+sim_ops 9810 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 23104 # Number of bytes read from this memory
system.physmem.bytes_inst_read 14528 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 57536 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 9810 # Number of instructions executed
+system.cpu.committedInsts 5417 # Number of instructions committed
+system.cpu.committedOps 9810 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 9715 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
system.cpu.icache.sampled_refs 228 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 29.311404 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 105.363985 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.051447 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 6683 # number of ReadReq hits
-system.cpu.icache.demand_hits 6683 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 6683 # number of overall hits
-system.cpu.icache.ReadReq_misses 228 # number of ReadReq misses
-system.cpu.icache.demand_misses 228 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 228 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 12726000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 12726000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 12726000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 6911 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 6911 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 6911 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.032991 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.032991 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.032991 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55815.789474 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55815.789474 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55815.789474 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 105.363985 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.051447 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.051447 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 6683 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 6683 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 6683 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 6683 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 6683 # number of overall hits
+system.cpu.icache.overall_hits::total 6683 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 228 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 228 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 228 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 228 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 228 # number of overall misses
+system.cpu.icache.overall_misses::total 228 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 12726000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 12726000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 12726000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 12726000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 12726000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 12726000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 6911 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 6911 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 6911 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 6911 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 6911 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 6911 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032991 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.032991 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.032991 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.996466 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.997238 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.997238 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 227 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 282 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 227 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 134 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 361 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 227 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 361 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9080000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2200000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11280000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3160000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9080000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5360000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 14440000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9080000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5360000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 14440000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.995614 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=2
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
[system.cpu.itb]
type=AlphaTLB
size=48
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
sim_ticks 13202000 # Number of ticks simulated
final_tick 13202000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 76140 # Simulator instruction rate (inst/s)
-host_tick_rate 78688554 # Simulator tick rate (ticks/s)
-host_mem_usage 208616 # Number of bytes of host memory used
-host_seconds 0.17 # Real time elapsed on the host
+host_inst_rate 91406 # Simulator instruction rate (inst/s)
+host_op_rate 91394 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 94452628 # Simulator tick rate (ticks/s)
+host_mem_usage 210624 # Number of bytes of host memory used
+host_seconds 0.14 # Real time elapsed on the host
sim_insts 12773 # Number of instructions simulated
+sim_ops 12773 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 62144 # Number of bytes read from this memory
system.physmem.bytes_inst_read 39936 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 12807 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 12807 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 9596 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 953 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 20176 # Number of insts commited each cycle
-system.cpu.commit.count::0 6403 # Number of instructions committed
-system.cpu.commit.count::1 6404 # Number of instructions committed
-system.cpu.commit.count::total 12807 # Number of instructions committed
+system.cpu.commit.committedInsts::0 6403 # Number of instructions committed
+system.cpu.commit.committedInsts::1 6404 # Number of instructions committed
+system.cpu.commit.committedInsts::total 12807 # Number of instructions committed
+system.cpu.commit.committedOps::0 6403 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1 6404 # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::total 12807 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
system.cpu.idleCycles 6204 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts::0 6386 # Number of Instructions Simulated
system.cpu.committedInsts::1 6387 # Number of Instructions Simulated
+system.cpu.committedOps::0 6386 # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1 6387 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 12773 # Number of Instructions Simulated
system.cpu.cpi::0 4.134826 # CPI: Cycles Per Instruction
system.cpu.cpi::1 4.134179 # CPI: Cycles Per Instruction
system.cpu.icache.sampled_refs 626 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 5.169329 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 314.165301 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.153401 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 3236 # number of ReadReq hits
-system.cpu.icache.demand_hits 3236 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 3236 # number of overall hits
-system.cpu.icache.ReadReq_misses 855 # number of ReadReq misses
-system.cpu.icache.demand_misses 855 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 855 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::0 30710500 # number of ReadReq miss cycles
+system.cpu.icache.occ_blocks::cpu.inst 314.165301 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.153401 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.153401 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 3236 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 3236 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 3236 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 3236 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 3236 # number of overall hits
+system.cpu.icache.overall_hits::total 3236 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 855 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 855 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 855 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 855 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 855 # number of overall misses
+system.cpu.icache.overall_misses::total 855 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 30710500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 30710500 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::0 30710500 # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::1 0 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 30710500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 30710500 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::0 30710500 # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::1 0 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 30710500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 30710500 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 4091 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 4091 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 4091 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.208995 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.208995 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.208995 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 35918.713450 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35918.713450 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 35918.713450 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1 0 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35918.713450 # average overall miss latency
+system.cpu.icache.ReadReq_accesses::cpu.inst 4091 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 4091 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 4091 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 4091 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 4091 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 4091 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.208995 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.208995 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.208995 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks::0 0 # number of writebacks
-system.cpu.icache.writebacks::1 0 # number of writebacks
-system.cpu.icache.writebacks::total 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::0 229 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 229 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 229 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::0 229 # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 229 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 229 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::0 229 # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::1 0 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 229 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 229 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::0 626 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 626 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 626 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::0 626 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 626 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 626 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::0 626 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::1 0 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 626 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 626 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::0 22267000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22267000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 22267000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::0 22267000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22267000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 22267000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::0 22267000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22267000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 22267000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0 0.153019 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153019 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0 0.153019 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.153019 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0 0.153019 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.153019 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35570.287540 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::0 35570.287540 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
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+system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses)
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+system.cpu.l2cache.demand_accesses::cpu.data 347 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 973 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 626 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 347 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 973 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996805 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996805 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996805 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 21000 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 4 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks::0 0 # number of writebacks
-system.cpu.l2cache.writebacks::1 0 # number of writebacks
-system.cpu.l2cache.writebacks::total 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits::0 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::1 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::0 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::1 0 # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::0 825 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 624 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 201 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 825 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::0 146 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::0 971 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::1 0 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 624 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 347 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 971 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::0 971 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::1 0 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 624 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 347 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 971 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::0 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::1 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::0 25887000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19514500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6372500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25887000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::0 4614000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4614000 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4614000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::0 30501000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::1 0 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19514500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10986500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 30501000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::0 30501000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::1 0 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19514500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10986500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 30501000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::0 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::1 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::0 0.997582 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997582 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::0 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::0 0.997945 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 0.997945 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::0 0.997945 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.997945 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::1 no_value # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total no_value # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0 no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1 no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events::0 0 # number of times MSHR cap was activated
-system.cpu.l2cache.mshr_cap_events::1 0 # number of times MSHR cap was activated
-system.cpu.l2cache.mshr_cap_events::total 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full::0 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.soft_prefetch_mshr_full::1 0 # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.soft_prefetch_mshr_full::total 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996805 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
RASSize=16
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchBuffSize=4
globalHistoryBits=13
globalPredictorSize=8192
instShiftAmt=2
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
localCtrBits=2
localHistoryBits=11
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
stageTracing=false
stageWidth=4
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:21
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:34
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
sim_ticks 25058500 # Number of ticks simulated
final_tick 25058500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 55020 # Simulator instruction rate (inst/s)
-host_tick_rate 90849063 # Simulator tick rate (ticks/s)
-host_mem_usage 212976 # Number of bytes of host memory used
-host_seconds 0.28 # Real time elapsed on the host
+host_inst_rate 93467 # Simulator instruction rate (inst/s)
+host_op_rate 93457 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 154309649 # Simulator tick rate (ticks/s)
+host_mem_usage 211048 # Number of bytes of host memory used
+host_seconds 0.16 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
+sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 27904 # Number of bytes read from this memory
system.physmem.bytes_inst_read 19072 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.comNonSpec 222 # Number of Non-Speculative instructions committed
system.cpu.comInts 7177 # Number of Integer instructions committed
system.cpu.comFloats 0 # Number of Floating Point instructions committed
-system.cpu.committedInsts 15175 # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts 0 # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total 15175 # Number of Instructions Simulated (Total)
+system.cpu.committedInsts 15175 # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps 15175 # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total 15175 # Number of Instructions committed (Total)
system.cpu.cpi 3.302669 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi no_value # CPI: Total SMT-CPI
system.cpu.cpi_total 3.302669 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 10.317726 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 165.645515 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.080882 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 3085 # number of ReadReq hits
-system.cpu.icache.demand_hits 3085 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 3085 # number of overall hits
-system.cpu.icache.ReadReq_misses 366 # number of ReadReq misses
-system.cpu.icache.demand_misses 366 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 366 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 20100000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 20100000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 20100000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 3451 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 3451 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 3451 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.106056 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.106056 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.106056 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54918.032787 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54918.032787 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54918.032787 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 165.645515 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.080882 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.080882 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 3085 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 3085 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 3085 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 3085 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 3085 # number of overall hits
+system.cpu.icache.overall_hits::total 3085 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 366 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 366 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 366 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 366 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 366 # number of overall misses
+system.cpu.icache.overall_misses::total 366 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 20100000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 20100000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 20100000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 20100000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 20100000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 20100000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 3451 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 3451 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 3451 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 3451 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 3451 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 3451 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.106056 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.106056 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.106056 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 19500 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 19500 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 65 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 65 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 301 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 301 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 301 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 15872000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 15872000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 15872000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 352 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 437 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 437 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 14048500 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3416000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 17464500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 17464500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.994350 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.995444 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.995444 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39910.511364 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40188.235294 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 39964.530892 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 299 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 352 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 299 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 437 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11916000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2132500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14048500 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3416000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3416000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11916000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 17464500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11916000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 17464500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:22
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:35
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
sim_ticks 18114000 # Number of ticks simulated
final_tick 18114000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 74785 # Simulator instruction rate (inst/s)
-host_tick_rate 93746300 # Simulator tick rate (ticks/s)
-host_mem_usage 213808 # Number of bytes of host memory used
-host_seconds 0.19 # Real time elapsed on the host
+host_inst_rate 120891 # Simulator instruction rate (inst/s)
+host_op_rate 120873 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 151511225 # Simulator tick rate (ticks/s)
+host_mem_usage 211580 # Number of bytes of host memory used
+host_seconds 0.12 # Real time elapsed on the host
sim_insts 14449 # Number of instructions simulated
+sim_ops 14449 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 30464 # Number of bytes read from this memory
system.physmem.bytes_inst_read 21120 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.iew.wb_fanout 0.835184 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu.commit.commitCommittedInsts 15175 # The number of committed instructions
+system.cpu.commit.commitCommittedOps 15175 # The number of committed instructions
system.cpu.commit.commitSquashedInsts 5794 # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts 847 # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total 26259 # Number of insts commited each cycle
-system.cpu.commit.count 15175 # Number of instructions committed
+system.cpu.commit.committedInsts 15175 # Number of instructions committed
+system.cpu.commit.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu.commit.refs 3674 # Number of memory references committed
system.cpu.commit.loads 2226 # Number of loads committed
system.cpu.timesIdled 181 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 8623 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts 14449 # Number of Instructions Simulated
+system.cpu.committedOps 14449 # Number of Ops (including micro ops) Simulated
system.cpu.committedInsts_total 14449 # Number of Instructions Simulated
system.cpu.cpi 2.507371 # CPI: Cycles Per Instruction
system.cpu.cpi_total 2.507371 # CPI: Total CPI of All Threads
system.cpu.icache.sampled_refs 332 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 12.503012 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 193.216525 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.094344 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 4151 # number of ReadReq hits
-system.cpu.icache.demand_hits 4151 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 4151 # number of overall hits
-system.cpu.icache.ReadReq_misses 457 # number of ReadReq misses
-system.cpu.icache.demand_misses 457 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 457 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15956000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 15956000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 15956000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 4608 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 4608 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 4608 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.099175 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.099175 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.099175 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34914.660832 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34914.660832 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34914.660832 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 193.216525 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.094344 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.094344 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 4151 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 4151 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 4151 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 4151 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 4151 # number of overall hits
+system.cpu.icache.overall_hits::total 4151 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 457 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 457 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 457 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 457 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 457 # number of overall misses
+system.cpu.icache.overall_misses::total 457 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15956000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15956000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 15956000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15956000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 15956000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15956000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 4608 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 4608 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 4608 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 4608 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 4608 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 4608 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.099175 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.099175 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.099175 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits 125 # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits 125 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 125 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 332 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 332 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 332 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 11653500 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 11653500 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 11653500 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.072049 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.072049 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.072049 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst 125 # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total 125 # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst 125 # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total 125 # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst 125 # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total 125 # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11653500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 11653500 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11653500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 11653500 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11653500 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 11653500 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.072049 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 102.149831 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25.424658 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 102.149831 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.024939 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 2672 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 1034 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
-system.cpu.dcache.demand_hits 3706 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 3706 # number of overall hits
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+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10246500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4577000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 14823500 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10246500 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4577000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 14823500 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993976 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31050 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31050 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
type=SparcTLB
size=64
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:24
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:45
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
sim_ticks 7618500 # Number of ticks simulated
final_tick 7618500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 296178 # Simulator instruction rate (inst/s)
-host_tick_rate 148615294 # Simulator tick rate (ticks/s)
-host_mem_usage 203776 # Number of bytes of host memory used
+host_inst_rate 298140 # Simulator instruction rate (inst/s)
+host_op_rate 298037 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 149578582 # Simulator tick rate (ticks/s)
+host_mem_usage 201436 # Number of bytes of host memory used
host_seconds 0.05 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
+sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 72223 # Number of bytes read from this memory
system.physmem.bytes_inst_read 60880 # Number of instructions bytes read from this memory
system.physmem.bytes_written 9042 # Number of bytes written to this memory
system.cpu.numCycles 15238 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 15175 # Number of instructions executed
+system.cpu.committedInsts 15175 # Number of instructions committed
+system.cpu.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu]
type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu.interrupts
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu.tracer
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=262144
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=131072
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.port[0]
+[system.cpu.interrupts]
+type=SparcInterrupts
+
[system.cpu.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=2097152
subblock_size=0
+system=system
tgts_per_mshr=5
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:28
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:45
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Begining test of difficult SPARC instructions...
sim_ticks 41800000 # Number of ticks simulated
final_tick 41800000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 146106 # Simulator instruction rate (inst/s)
-host_tick_rate 402347608 # Simulator tick rate (ticks/s)
-host_mem_usage 212484 # Number of bytes of host memory used
-host_seconds 0.10 # Real time elapsed on the host
+host_inst_rate 399467 # Simulator instruction rate (inst/s)
+host_op_rate 399277 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1099343547 # Simulator tick rate (ticks/s)
+host_mem_usage 210560 # Number of bytes of host memory used
+host_seconds 0.04 # Real time elapsed on the host
sim_insts 15175 # Number of instructions simulated
+sim_ops 15175 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 26624 # Number of bytes read from this memory
system.physmem.bytes_inst_read 17792 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu.numCycles 83600 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.num_insts 15175 # Number of instructions executed
+system.cpu.committedInsts 15175 # Number of instructions committed
+system.cpu.committedOps 15175 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 12231 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 385 # number of times a function call or return occured
system.cpu.icache.sampled_refs 280 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 53.360714 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0 153.436702 # Average occupied blocks per context
-system.cpu.icache.occ_percent::0 0.074920 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits 14941 # number of ReadReq hits
-system.cpu.icache.demand_hits 14941 # number of demand (read+write) hits
-system.cpu.icache.overall_hits 14941 # number of overall hits
-system.cpu.icache.ReadReq_misses 280 # number of ReadReq misses
-system.cpu.icache.demand_misses 280 # number of demand (read+write) misses
-system.cpu.icache.overall_misses 280 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency 15596000 # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency 15596000 # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency 15596000 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses 15221 # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses 15221 # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses 15221 # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate 0.018396 # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate 0.018396 # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate 0.018396 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55700 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55700 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55700 # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst 153.436702 # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst 0.074920 # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total 0.074920 # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst 14941 # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total 14941 # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst 14941 # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total 14941 # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst 14941 # number of overall hits
+system.cpu.icache.overall_hits::total 14941 # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst 280 # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total 280 # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst 280 # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total 280 # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst 280 # number of overall misses
+system.cpu.icache.overall_misses::total 280 # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst 15596000 # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total 15596000 # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst 15596000 # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total 15596000 # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst 15596000 # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total 15596000 # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst 15221 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total 15221 # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst 15221 # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total 15221 # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst 15221 # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total 15221 # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018396 # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst 0.018396 # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst 0.018396 # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55700 # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55700 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55700 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
-system.cpu.icache.writebacks 0 # number of writebacks
-system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses 280 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses 280 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses 280 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency 14756000 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency 14756000 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency 14756000 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate 0.018396 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate 0.018396 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate 0.018396 # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52700 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52700 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52700 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total 280 # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst 280 # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total 280 # number of demand (read+write) MSHR misses
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+system.cpu.icache.overall_mshr_misses::total 280 # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14756000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total 14756000 # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14756000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total 14756000 # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14756000 # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total 14756000 # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018396 # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52700 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52700 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 0 # number of replacements
system.cpu.dcache.tagsinuse 97.842991 # Cycle average of tags in use
system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 25.623188 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0 97.842991 # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0 0.023887 # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits 2173 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits 1357 # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits 6 # number of SwapReq hits
-system.cpu.dcache.demand_hits 3530 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits 3530 # number of overall hits
-system.cpu.dcache.ReadReq_misses 53 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses 85 # number of WriteReq misses
-system.cpu.dcache.demand_misses 138 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses 138 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency 2968000 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency 4760000 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency 7728000 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency 7728000 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses 2226 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses 1442 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses 6 # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses 3668 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses 3668 # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate 0.023810 # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate 0.058946 # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate 0.037623 # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate 0.037623 # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 56000 # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 56000 # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 56000 # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 56000 # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data 97.842991 # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data 0.023887 # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total 0.023887 # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data 2173 # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total 2173 # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data 1357 # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total 1357 # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data 3530 # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total 3530 # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data 3530 # number of overall hits
+system.cpu.dcache.overall_hits::total 3530 # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total 53 # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data 85 # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total 85 # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.dcache.overall_misses::total 138 # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 2968000 # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 2968000 # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 4760000 # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 4760000 # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 7728000 # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 7728000 # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 7728000 # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 7728000 # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data 2226 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total 2226 # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data 3668 # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total 3668 # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data 3668 # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total 3668 # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023810 # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data 0.037623 # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data 0.037623 # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
-system.cpu.dcache.writebacks 0 # number of writebacks
-system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses 53 # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses 85 # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses 138 # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses 138 # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 2809000 # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency 4505000 # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 7314000 # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 7314000 # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate 0.023810 # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate 0.058946 # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate 0.037623 # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate 0.037623 # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53000 # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 85 # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 2809000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 4505000 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023810 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037623 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 0 # number of replacements
system.cpu.l2cache.tagsinuse 184.236128 # Cycle average of tags in use
system.cpu.l2cache.sampled_refs 331 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 0.006042 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0 184.236128 # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0 0.005622 # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits 2 # number of ReadReq hits
-system.cpu.l2cache.demand_hits 2 # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits 2 # number of overall hits
-system.cpu.l2cache.ReadReq_misses 331 # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses 85 # number of ReadExReq misses
-system.cpu.l2cache.demand_misses 416 # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses 416 # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency 17212000 # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency 4420000 # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency 21632000 # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency 21632000 # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses 333 # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses 85 # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses 418 # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses 418 # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate 0.993994 # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate 0.995215 # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate 0.995215 # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52000 # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000 # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000 # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst 152.765242 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data 31.470886 # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst 0.004662 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data 0.000960 # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total 0.005622 # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits
+system.cpu.l2cache.overall_hits::total 2 # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data 53 # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total 331 # number of ReadReq misses
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+system.cpu.l2cache.ReadExReq_misses::total 85 # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data 138 # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total 416 # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses
+system.cpu.l2cache.overall_misses::total 416 # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14456000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2756000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total 17212000 # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4420000 # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total 4420000 # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst 14456000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 7176000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 21632000 # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst 14456000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 7176000 # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 21632000 # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst 280 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total 333 # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total 85 # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst 280 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total 418 # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst 280 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total 418 # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.992857 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
-system.cpu.l2cache.writebacks 0 # number of writebacks
-system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses 331 # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses 85 # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses 416 # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses 416 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency 13240000 # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency 3400000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 16640000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 16640000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate 0.993994 # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate 0.995215 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate 0.995215 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total 85 # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total 416 # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total 416 # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2120000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13240000 # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3400000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3400000 # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11120000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 16640000 # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11120000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 16640000 # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu0]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer workload
+children=dcache dtb fuPool icache interrupts itb tracer workload
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu0.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu0.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
[system.cpu0.itb]
type=SparcTLB
size=64
[system.cpu1]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu1.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu1.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu2]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu2.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu2.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu3]
type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
BTBEntries=4096
BTBTagSize=16
LFSTSize=1024
defer_registration=false
dispatchWidth=8
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
fetchToDecodeDelay=1
iewToFetchDelay=1
iewToRenameDelay=1
instShiftAmt=2
+interrupts=system.cpu3.interrupts
issueToExecuteDelay=1
issueWidth=8
itb=system.cpu3.itb
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
+needsTSO=false
numIQEntries=64
numPhysFloatRegs=256
numPhysIntRegs=256
numThreads=1
phase=0
predType=tournament
+profile=0
progress_interval=0
renameToDecodeDelay=1
renameToFetchDelay=1
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=20
trace_addr=0
two_queue=false
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
[system.cpu3.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:31
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:55
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
sim_ticks 104317500 # Number of ticks simulated
final_tick 104317500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 132902 # Simulator instruction rate (inst/s)
-host_tick_rate 13605540 # Simulator tick rate (ticks/s)
-host_mem_usage 226920 # Number of bytes of host memory used
-host_seconds 7.67 # Real time elapsed on the host
+host_inst_rate 190796 # Simulator instruction rate (inst/s)
+host_op_rate 190795 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 19532213 # Simulator tick rate (ticks/s)
+host_mem_usage 225896 # Number of bytes of host memory used
+host_seconds 5.34 # Real time elapsed on the host
sim_insts 1018993 # Number of instructions simulated
+sim_ops 1018993 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 41984 # Number of bytes read from this memory
system.physmem.bytes_inst_read 28224 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu0.iew.wb_fanout 0.991039 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu0.commit.commitCommittedInsts 462799 # The number of committed instructions
+system.cpu0.commit.commitCommittedOps 462799 # The number of committed instructions
system.cpu0.commit.commitSquashedInsts 9535 # The number of squashed insts skipped by commit
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
system.cpu0.commit.branchMispredicts 1043 # The number of times a branch was mispredicted
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::total 188840 # Number of insts commited each cycle
-system.cpu0.commit.count 462799 # Number of instructions committed
+system.cpu0.commit.committedInsts 462799 # Number of instructions committed
+system.cpu0.commit.committedOps 462799 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu0.commit.refs 226109 # Number of memory references committed
system.cpu0.commit.loads 150402 # Number of loads committed
system.cpu0.timesIdled 320 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu0.idleCycles 17790 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu0.committedInsts 388389 # Number of Instructions Simulated
+system.cpu0.committedOps 388389 # Number of Ops (including micro ops) Simulated
system.cpu0.committedInsts_total 388389 # Number of Instructions Simulated
system.cpu0.cpi 0.537183 # CPI: Cycles Per Instruction
system.cpu0.cpi_total 0.537183 # CPI: Total CPI of All Threads
system.cpu0.icache.sampled_refs 581 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 8.278830 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 244.353680 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.477253 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits 4810 # number of ReadReq hits
-system.cpu0.icache.demand_hits 4810 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits 4810 # number of overall hits
-system.cpu0.icache.ReadReq_misses 705 # number of ReadReq misses
-system.cpu0.icache.demand_misses 705 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses 705 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 27622000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency 27622000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 27622000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses 5515 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses 5515 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses 5515 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate 0.127833 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate 0.127833 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate 0.127833 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39180.141844 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39180.141844 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 244.353680 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.477253 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.477253 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 4810 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 4810 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 4810 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 4810 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 4810 # number of overall hits
+system.cpu0.icache.overall_hits::total 4810 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 705 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 705 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 705 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 705 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 705 # number of overall misses
+system.cpu0.icache.overall_misses::total 705 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 27622000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 27622000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 27622000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 27622000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 27622000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 27622000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 5515 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 5515 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 5515 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 5515 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 5515 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 5515 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.127833 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.127833 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.127833 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits 123 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits 123 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 123 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 582 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 582 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 582 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 21369000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 21369000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 21369000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.105530 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate 0.105530 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate 0.105530 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 123 # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total 123 # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst 123 # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total 123 # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst 123 # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total 123 # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 582 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 582 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 582 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 582 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 582 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 582 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21369000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 21369000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21369000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 21369000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21369000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 21369000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.105530 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 9 # number of replacements
-system.cpu0.dcache.tagsinuse 138.901719 # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse 140.432794 # Cycle average of tags in use
system.cpu0.dcache.total_refs 97328 # Total number of references to valid blocks.
system.cpu0.dcache.sampled_refs 174 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 559.356322 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 140.432794 # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1 -1.531076 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.274283 # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1 -0.002990 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits 77005 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits 75125 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits 23 # number of SwapReq hits
-system.cpu0.dcache.demand_hits 152130 # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits 152130 # number of overall hits
-system.cpu0.dcache.ReadReq_misses 517 # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses 540 # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses 19 # number of SwapReq misses
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-system.cpu0.dcache.ReadReq_miss_latency 14734500 # number of ReadReq miss cycles
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-system.cpu0.dcache.SwapReq_miss_latency 371000 # number of SwapReq miss cycles
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-system.cpu0.dcache.ReadReq_avg_miss_latency 28500 # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148 # average WriteReq miss latency
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-system.cpu0.dcache.overall_avg_miss_latency 37301.309366 # average overall miss latency
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system.cpu0.dcache.blocked_cycles::no_mshrs 180500 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 21 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu0.dcache.ReadReq_mshr_hits 327 # number of ReadReq MSHR hits
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+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602 # average overall mshr miss latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.numCycles 174305 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.iew.wb_fanout 0.968192 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu1.commit.commitCommittedInsts 275667 # The number of committed instructions
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system.cpu1.commit.commitSquashedInsts 9533 # The number of squashed insts skipped by commit
system.cpu1.commit.commitNonSpecStalls 5427 # The number of times commit has been forced to stall to communicate backwards
system.cpu1.commit.branchMispredicts 1085 # The number of times a branch was mispredicted
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::total 163203 # Number of insts commited each cycle
-system.cpu1.commit.count 275667 # Number of instructions committed
+system.cpu1.commit.committedInsts 275667 # Number of instructions committed
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system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu1.commit.refs 118493 # Number of memory references committed
system.cpu1.commit.loads 80399 # Number of loads committed
system.cpu1.idleCycles 2707 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu1.quiesceCycles 34329 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu1.committedInsts 231385 # Number of Instructions Simulated
+system.cpu1.committedOps 231385 # Number of Ops (including micro ops) Simulated
system.cpu1.committedInsts_total 231385 # Number of Instructions Simulated
system.cpu1.cpi 0.753312 # CPI: Cycles Per Instruction
system.cpu1.cpi_total 0.753312 # CPI: Total CPI of All Threads
system.cpu1.icache.sampled_refs 427 # Sample count of references to valid blocks.
system.cpu1.icache.avg_refs 41.850117 # Average number of references to valid blocks.
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu1.icache.occ_percent::0 0.165119 # Average percentage of cache occupancy
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-system.cpu1.icache.ReadReq_miss_latency 7203000 # number of ReadReq miss cycles
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-system.cpu1.icache.ReadReq_accesses 18341 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631 # average ReadReq miss latency
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-system.cpu1.icache.overall_avg_miss_latency 15292.993631 # average overall miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631 # average overall miss latency
system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
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-system.cpu1.icache.ReadReq_mshr_hits 44 # number of ReadReq MSHR hits
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-system.cpu1.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses
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-system.cpu1.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency 5374000 # number of ReadReq MSHR miss cycles
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-system.cpu1.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate 0.023281 # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.overall_mshr_miss_rate 0.023281 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dcache.replacements 2 # number of replacements
-system.cpu1.dcache.tagsinuse 18.588243 # Cycle average of tags in use
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system.cpu1.dcache.total_refs 44082 # Total number of references to valid blocks.
system.cpu1.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu1.dcache.avg_refs 1469.400000 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0 24.401572 # Average occupied blocks per context
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system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.numCycles 174018 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.iew.wb_fanout 0.966435 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitCommittedInsts 256708 # The number of committed instructions
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system.cpu2.commit.commitSquashedInsts 10074 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 5686 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 1149 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 160519 # Number of insts commited each cycle
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system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 108759 # Number of memory references committed
system.cpu2.commit.loads 73984 # Number of loads committed
system.cpu2.idleCycles 5048 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 34616 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 215254 # Number of Instructions Simulated
+system.cpu2.committedOps 215254 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 215254 # Number of Instructions Simulated
system.cpu2.cpi 0.808431 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 0.808431 # CPI: Total CPI of All Threads
system.cpu2.icache.sampled_refs 427 # Sample count of references to valid blocks.
system.cpu2.icache.avg_refs 43.508197 # Average number of references to valid blocks.
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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-system.cpu2.icache.overall_avg_miss_latency 21718.295218 # average overall miss latency
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+system.cpu2.icache.ReadReq_accesses::total 19059 # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst 19059 # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total 19059 # number of demand (read+write) accesses
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+system.cpu2.icache.overall_accesses::total 19059 # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.025237 # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst 0.025237 # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst 0.025237 # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218 # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218 # average overall miss latency
system.cpu2.icache.blocked_cycles::no_mshrs 33000 # number of cycles access was blocked
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.icache.fast_writes 0 # number of fast writes performed
system.cpu2.icache.cache_copies 0 # number of cache copies performed
-system.cpu2.icache.writebacks 0 # number of writebacks
-system.cpu2.icache.ReadReq_mshr_hits 54 # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits 54 # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits 54 # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses 427 # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses 427 # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses 427 # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.icache.ReadReq_mshr_miss_latency 8026500 # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency 8026500 # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency 8026500 # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate 0.022404 # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate 0.022404 # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate 0.022404 # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888 # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888 # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu2.icache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits
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+system.cpu2.icache.demand_mshr_hits::total 54 # number of demand (read+write) MSHR hits
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+system.cpu2.icache.overall_mshr_hits::total 54 # number of overall MSHR hits
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+system.cpu2.icache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst 427 # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total 427 # number of demand (read+write) MSHR misses
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+system.cpu2.icache.ReadReq_mshr_miss_latency::total 8026500 # number of ReadReq MSHR miss cycles
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+system.cpu2.icache.demand_mshr_miss_latency::total 8026500 # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 8026500 # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total 8026500 # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.022404 # mshr miss rate for demand accesses
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+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888 # average overall mshr miss latency
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.dcache.replacements 2 # number of replacements
-system.cpu2.dcache.tagsinuse 19.370911 # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse 26.582846 # Cycle average of tags in use
system.cpu2.dcache.total_refs 40686 # Total number of references to valid blocks.
system.cpu2.dcache.sampled_refs 30 # Sample count of references to valid blocks.
system.cpu2.dcache.avg_refs 1356.200000 # Average number of references to valid blocks.
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::0 26.582846 # Average occupied blocks per context
-system.cpu2.dcache.occ_blocks::1 -7.211935 # Average occupied blocks per context
-system.cpu2.dcache.occ_percent::0 0.051920 # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::1 -0.014086 # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits 43569 # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits 34581 # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits 13 # number of SwapReq hits
-system.cpu2.dcache.demand_hits 78150 # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits 78150 # number of overall hits
-system.cpu2.dcache.ReadReq_misses 459 # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses 120 # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses 61 # number of SwapReq misses
-system.cpu2.dcache.demand_misses 579 # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses 579 # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency 10999500 # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency 2980500 # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency 1343500 # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency 13980000 # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency 13980000 # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses 44028 # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses 34701 # number of WriteReq accesses(hits+misses)
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-system.cpu2.dcache.ReadReq_miss_rate 0.010425 # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate 0.003458 # miss rate for WriteReq accesses
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-system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288 # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000 # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency 22024.590164 # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency 24145.077720 # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency 24145.077720 # average overall miss latency
+system.cpu2.dcache.occ_blocks::cpu2.data 26.582846 # Average occupied blocks per requestor
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+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288 # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000 # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164 # average SwapReq miss latency
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+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720 # average overall miss latency
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
-system.cpu2.dcache.writebacks 1 # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_hits 297 # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits 18 # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits 315 # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits 315 # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses 162 # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses 102 # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses 61 # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses 264 # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses 264 # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency 2380000 # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency 1660000 # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency 1160500 # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency 4040000 # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency 4040000 # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate 0.003679 # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate 0.002939 # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate 0.824324 # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate 0.003353 # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate 0.003353 # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025 # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804 # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164 # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303 # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu2.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu2.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.writebacks::writebacks 1 # number of writebacks
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+system.cpu2.dcache.demand_mshr_miss_latency::total 4040000 # number of demand (read+write) MSHR miss cycles
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+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025 # average ReadReq mshr miss latency
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+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303 # average overall mshr miss latency
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu3.numCycles 173752 # number of cpu cycles simulated
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu3.iew.wb_fanout 0.961453 # average fanout of values written-back
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu3.commit.commitCommittedInsts 222296 # The number of committed instructions
+system.cpu3.commit.commitCommittedOps 222296 # The number of committed instructions
system.cpu3.commit.commitSquashedInsts 9409 # The number of squashed insts skipped by commit
system.cpu3.commit.commitNonSpecStalls 7641 # The number of times commit has been forced to stall to communicate backwards
system.cpu3.commit.branchMispredicts 1065 # The number of times a branch was mispredicted
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu3.commit.committed_per_cycle::total 162652 # Number of insts commited each cycle
-system.cpu3.commit.count 222296 # Number of instructions committed
+system.cpu3.commit.committedInsts 222296 # Number of instructions committed
+system.cpu3.commit.committedOps 222296 # Number of ops (including micro ops) committed
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu3.commit.refs 89597 # Number of memory references committed
system.cpu3.commit.loads 61865 # Number of loads committed
system.cpu3.idleCycles 2770 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu3.quiesceCycles 34882 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu3.committedInsts 183965 # Number of Instructions Simulated
+system.cpu3.committedOps 183965 # Number of Ops (including micro ops) Simulated
system.cpu3.committedInsts_total 183965 # Number of Instructions Simulated
system.cpu3.cpi 0.944484 # CPI: Cycles Per Instruction
system.cpu3.cpi_total 0.944484 # CPI: Total CPI of All Threads
system.cpu3.icache.sampled_refs 426 # Sample count of references to valid blocks.
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system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606529 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.032787 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.520000 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst 0.170960 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data 0.740741 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst 0.002347 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data 0.520000 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 40000 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40125 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40225 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=atomic
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu0]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu0.interrupts
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
[system.cpu0.itb]
type=SparcTLB
size=64
[system.cpu1]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu1.interrupts
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu2]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu2.interrupts
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu3]
type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu3.interrupts
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
simulate_data_stalls=false
simulate_inst_stalls=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
[system.cpu3.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:32
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:56
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
sim_ticks 87713500 # Number of ticks simulated
final_tick 87713500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1650324 # Simulator instruction rate (inst/s)
-host_tick_rate 213702670 # Simulator tick rate (ticks/s)
-host_mem_usage 1140448 # Number of bytes of host memory used
+host_inst_rate 1664146 # Simulator instruction rate (inst/s)
+host_op_rate 1664073 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 215483439 # Simulator tick rate (ticks/s)
+host_mem_usage 1139232 # Number of bytes of host memory used
host_seconds 0.41 # Real time elapsed on the host
sim_insts 677340 # Number of instructions simulated
+sim_ops 677340 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 35776 # Number of bytes read from this memory
system.physmem.bytes_inst_read 22272 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu0.numCycles 175428 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 175339 # Number of instructions executed
+system.cpu0.committedInsts 175339 # Number of instructions committed
+system.cpu0.committedOps 175339 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 120388 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 374.591006 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 222.757301 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.435073 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits 174934 # number of ReadReq hits
-system.cpu0.icache.demand_hits 174934 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits 174934 # number of overall hits
-system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses
-system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses 467 # number of overall misses
-system.cpu0.icache.demand_miss_latency 0 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 0 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses 175401 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses 175401 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses 175401 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate 0.002662 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate 0.002662 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate 0.002662 # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency 0 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 0 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 222.757301 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.435073 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.435073 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 174934 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 174934 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 174934 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 174934 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 174934 # number of overall hits
+system.cpu0.icache.overall_hits::total 174934 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
+system.cpu0.icache.overall_misses::total 467 # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 175401 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 175401 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 175401 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 175401 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 175401 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 175401 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002662 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002662 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002662 # miss rate for overall accesses
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 0 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate 0 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate 0 # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.replacements 9 # number of replacements
system.cpu0.dcache.tagsinuse 145.712770 # Cycle average of tags in use
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
system.cpu0.dcache.avg_refs 362.347059 # Average number of references to valid blocks.
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0 145.712770 # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0 0.284595 # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits 54431 # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits 27578 # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits 15 # number of SwapReq hits
-system.cpu0.dcache.demand_hits 82009 # number of demand (read+write) hits
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+system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
-system.l2c.writebacks 0 # number of writebacks
-system.l2c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits 0 # number of overall MSHR hits
-system.l2c.demand_mshr_misses 0 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 0 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency 0 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 0 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 0 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 0 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 0 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0 # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency no_value # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
[system.cpu0]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
checker=Null
clock=500
cpu_id=0
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu0.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu0.interrupts
itb=system.cpu0.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu0.tracer
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu0.icache_port
mem_side=system.toL2Bus.port[1]
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
[system.cpu0.itb]
type=SparcTLB
size=64
[system.cpu1]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=1
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu1.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu1.interrupts
itb=system.cpu1.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu1.tracer
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu1.icache_port
mem_side=system.toL2Bus.port[3]
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
[system.cpu1.itb]
type=SparcTLB
size=64
[system.cpu2]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=2
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu2.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu2.interrupts
itb=system.cpu2.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu2.tracer
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu2.icache_port
mem_side=system.toL2Bus.port[5]
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
[system.cpu2.itb]
type=SparcTLB
size=64
[system.cpu3]
type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
checker=Null
clock=500
cpu_id=3
defer_registration=false
do_checkpoint_insts=true
+do_quiesce=true
do_statistics_insts=true
dtb=system.cpu3.dtb
function_trace=false
function_trace_start=0
+interrupts=system.cpu3.interrupts
itb=system.cpu3.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_any_thread=0
numThreads=1
phase=0
+profile=0
progress_interval=0
system=system
tracer=system.cpu3.tracer
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=1000
max_miss_count=0
mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
cpu_side=system.cpu3.icache_port
mem_side=system.toL2Bus.port[7]
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
[system.cpu3.itb]
type=SparcTLB
size=64
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=4194304
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:33
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:07
gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Init done
sim_ticks 262298000 # Number of ticks simulated
final_tick 262298000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1158712 # Simulator instruction rate (inst/s)
-host_tick_rate 458877844 # Simulator tick rate (ticks/s)
-host_mem_usage 222944 # Number of bytes of host memory used
-host_seconds 0.57 # Real time elapsed on the host
+host_inst_rate 1330969 # Simulator instruction rate (inst/s)
+host_op_rate 1330920 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 527074583 # Simulator tick rate (ticks/s)
+host_mem_usage 221728 # Number of bytes of host memory used
+host_seconds 0.50 # Real time elapsed on the host
sim_insts 662307 # Number of instructions simulated
+sim_ops 662307 # Number of ops (including micro ops) simulated
system.physmem.bytes_read 36608 # Number of bytes read from this memory
system.physmem.bytes_inst_read 22656 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
system.cpu0.numCycles 524596 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.num_insts 158353 # Number of instructions executed
+system.cpu0.committedInsts 158353 # Number of instructions committed
+system.cpu0.committedOps 158353 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 390 # number of times a function call or return occured
system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks.
system.cpu0.icache.avg_refs 338.220557 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0 212.479188 # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0 0.414998 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits 157949 # number of ReadReq hits
-system.cpu0.icache.demand_hits 157949 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits 157949 # number of overall hits
-system.cpu0.icache.ReadReq_misses 467 # number of ReadReq misses
-system.cpu0.icache.demand_misses 467 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses 467 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency 18524000 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency 18524000 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency 18524000 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses 158416 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses 158416 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses 158416 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate 0.002948 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate 0.002948 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate 0.002948 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39665.952891 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39665.952891 # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst 212.479188 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.414998 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.414998 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 157949 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 157949 # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst 157949 # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total 157949 # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst 157949 # number of overall hits
+system.cpu0.icache.overall_hits::total 157949 # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses
+system.cpu0.icache.overall_misses::total 467 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18524000 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 18524000 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 18524000 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 18524000 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 18524000 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 18524000 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 158416 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total 158416 # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst 158416 # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total 158416 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 158416 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 158416 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002948 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002948 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002948 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.writebacks 0 # number of writebacks
-system.cpu0.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses 467 # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses 467 # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses 467 # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency 17123000 # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency 17123000 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency 17123000 # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate 0.002948 # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate 0.002948 # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate 0.002948 # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 467 # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total 467 # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst 467 # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total 467 # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst 467 # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total 467 # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17123000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total 17123000 # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17123000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total 17123000 # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17123000 # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total 17123000 # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.002948 # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891 # average overall mshr miss latency
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+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262 # average overall mshr miss latency
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-system.cpu1.dcache.overall_avg_miss_latency 20078.853047 # average overall miss latency
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+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047 # average overall mshr miss latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
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-system.l2c.ReadExReq_mshr_misses 142 # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses 572 # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses 572 # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency 17203000 # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency 2880000 # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency 5681000 # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency 22884000 # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency 22884000 # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0 0.799257 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1 1.134565 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2 1.134565 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3 1.131579 # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total 4.199965 # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0 2.400000 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1 6 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2 4.500000 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3 4.500000 # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total 17.400000 # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0 1.434343 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1 9.466667 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2 10.142857 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3 10.142857 # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total 31.186724 # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0 0.897959 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1 1.451777 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2 1.455471 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3 1.451777 # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total 5.256983 # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0 0.897959 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1 1.451777 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2 1.455471 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3 1.451777 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 5.256983 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40006.976744 # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40000 # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40007.042254 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency 40006.993007 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40006.993007 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency no_value # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data 1 # number of ReadReq MSHR hits
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+system.l2c.ReadReq_mshr_hits::cpu3.inst 8 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.data 1 # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total 20 # number of ReadReq MSHR hits
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+system.l2c.demand_mshr_hits::cpu1.data 1 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst 3 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst 8 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data 1 # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total 20 # number of demand (read+write) MSHR hits
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+system.l2c.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
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+system.l2c.UpgradeReq_mshr_misses::total 72 # number of UpgradeReq MSHR misses
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+system.l2c.demand_mshr_misses::cpu2.data 16 # number of demand (read+write) MSHR misses
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+system.l2c.UpgradeReq_mshr_miss_latency::total 2880000 # number of UpgradeReq MSHR miss cycles
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+system.l2c.overall_mshr_miss_latency::total 22884000 # number of overall MSHR miss cycles
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+system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.153846 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.076923 # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.933333 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
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+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
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+system.l2c.demand_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst 0.002725 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data 0.555556 # mshr miss rate for demand accesses
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+system.l2c.overall_mshr_miss_rate::cpu0.data 0.970588 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::cpu2.data 0.592593 # mshr miss rate for overall accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 40000 # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40000 # average overall mshr miss latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[0]
test=system.l1_cntrl0.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[1]
test=system.l1_cntrl1.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[2]
test=system.l1_cntrl2.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[3]
test=system.l1_cntrl3.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[4]
test=system.l1_cntrl4.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[5]
test=system.l1_cntrl5.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[6]
test=system.l1_cntrl6.sequencer.port[0]
percent_uncacheable=0
progress_interval=10000
suppress_func_warnings=true
+sys=system
trace_addr=0
functional=system.funcmem.port[7]
test=system.l1_cntrl7.sequencer.port[0]
================ End RubySystem Configuration Print ================
-Real time: Feb/12/2012 12:58:05
+Real time: Feb/12/2012 15:36:31
Profiler Stats
--------------
-Elapsed_time_in_seconds: 110
-Elapsed_time_in_minutes: 1.83333
-Elapsed_time_in_hours: 0.0305556
-Elapsed_time_in_days: 0.00127315
+Elapsed_time_in_seconds: 190
+Elapsed_time_in_minutes: 3.16667
+Elapsed_time_in_hours: 0.0527778
+Elapsed_time_in_days: 0.00219907
-Virtual_time_in_seconds: 110.38
-Virtual_time_in_minutes: 1.83967
-Virtual_time_in_hours: 0.0306611
-Virtual_time_in_days: 0.00127755
+Virtual_time_in_seconds: 189.25
+Virtual_time_in_minutes: 3.15417
+Virtual_time_in_hours: 0.0525694
+Virtual_time_in_days: 0.00219039
Ruby_current_time: 22495354
Ruby_start_time: 0
Ruby_cycles: 22495354
-mbytes_resident: 41.8164
-mbytes_total: 371.512
-resident_ratio: 0.112578
+mbytes_resident: 0
+mbytes_total: 0
ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ]
Resource Usage
--------------
page_size: 4096
-user_time: 110
+user_time: 188
system_time: 0
-page_reclaims: 11719
-page_faults: 18
+page_reclaims: 12571
+page_faults: 0
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1
+block_outputs: 44
Network Stats
-------------
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 12 2012 12:56:01
-gem5 started Feb 12 2012 12:56:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 22495354 # Number of ticks simulated
final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 204320 # Simulator tick rate (ticks/s)
-host_mem_usage 380432 # Number of bytes of host memory used
-host_seconds 110.10 # Real time elapsed on the host
+host_tick_rate 118487 # Simulator tick rate (ticks/s)
+host_mem_usage 398520 # Number of bytes of host memory used
+host_seconds 189.86 # Real time elapsed on the host
system.physmem.bytes_read 0 # Number of bytes read from this memory
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
[root]
type=Root
children=system
+full_system=false
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
mem_mode=timing
memories=system.physmem system.funcmem
num_work_ids=16
physmem=system.physmem
+readfile=
+symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[0]
test=system.cpu0.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[1]
test=system.cpu1.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[2]
test=system.cpu2.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[3]
test=system.cpu3.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[4]
test=system.cpu4.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[5]
test=system.cpu5.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[6]
test=system.cpu6.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
percent_uncacheable=10
progress_interval=10000
suppress_func_warnings=false
+sys=system
trace_addr=0
functional=system.funcmem.port[7]
test=system.cpu7.l1c.cpu_side
latency=1000
max_miss_count=0
mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=32768
subblock_size=0
+system=system
tgts_per_mshr=8
trace_addr=0
two_queue=false
latency=10000
max_miss_count=0
mshrs=92
-num_cpus=8
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
prioritizeRequests=false
repl=Null
size=65536
subblock_size=0
+system=system
tgts_per_mshr=16
trace_addr=0
two_queue=false
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:28
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
Exiting @ tick 263488655 because maximum number of loads reached
sim_ticks 263488655 # Number of ticks simulated
final_tick 263488655 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_tick_rate 1768401 # Simulator tick rate (ticks/s)
-host_mem_usage 335780 # Number of bytes of host memory used
-host_seconds 149.00 # Real time elapsed on the host
+host_tick_rate 1938715 # Simulator tick rate (ticks/s)
+host_mem_usage 338552 # Number of bytes of host memory used
+host_seconds 135.91 # Real time elapsed on the host
system.physmem.bytes_read 4057580 # Number of bytes read from this memory
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.physmem.bytes_written 2644316 # Number of bytes written to this memory
system.l2c.sampled_refs 77525 # Sample count of references to valid blocks.
system.l2c.avg_refs 1.794905 # Average number of references to valid blocks.
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0 24.077198 # Average occupied blocks per context
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+system.l2c.UpgradeReq_miss_rate::cpu0 0.782485 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1 0.792266 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2 0.783810 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3 0.776652 # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4 0.786706 # miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_miss_rate::cpu7 0.793778 # miss rate for UpgradeReq accesses
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+system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646 # average ReadReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910 # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571 # average UpgradeReq miss latency
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+system.l2c.UpgradeReq_avg_miss_latency::cpu3 20034.267702 # average UpgradeReq miss latency
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system.l2c.blocked_cycles::no_mshrs 97509 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 14 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
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-system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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-system.l2c.ReadReq_mshr_uncacheable_latency 3189139994 # number of ReadReq MSHR uncacheable cycles
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-system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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-system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.788299 # mshr miss rate for UpgradeReq accesses
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.773275 # mshr miss rate for UpgradeReq accesses
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system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.num_reads 99815 # number of read accesses completed
system.cpu0.num_writes 53929 # number of write accesses completed
system.cpu0.num_copies 0 # number of copy accesses completed
system.cpu0.l1c.replacements 27826 # number of replacements
-system.cpu0.l1c.tagsinuse 102.742005 # Cycle average of tags in use
+system.cpu0.l1c.tagsinuse 347.331950 # Cycle average of tags in use
system.cpu0.l1c.total_refs 11604 # Total number of references to valid blocks.
system.cpu0.l1c.sampled_refs 28187 # Sample count of references to valid blocks.
system.cpu0.l1c.avg_refs 0.411679 # Average number of references to valid blocks.
system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.occ_blocks::0 347.331950 # Average occupied blocks per context
-system.cpu0.l1c.occ_blocks::1 -244.589945 # Average occupied blocks per context
-system.cpu0.l1c.occ_percent::0 0.678383 # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::1 -0.477715 # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits 7530 # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits 1059 # number of WriteReq hits
-system.cpu0.l1c.demand_hits 8589 # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits 8589 # number of overall hits
-system.cpu0.l1c.ReadReq_misses 37279 # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses 23202 # number of WriteReq misses
-system.cpu0.l1c.demand_misses 60481 # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses 60481 # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency 1299667421 # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency 1001508092 # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency 2301175513 # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency 2301175513 # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses 44809 # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses 24261 # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses 69070 # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses 69070 # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate 0.831953 # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate 0.956350 # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate 0.875648 # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate 0.875648 # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698 # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144 # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency 38047.907822 # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency 38047.907822 # average overall miss latency
+system.cpu0.l1c.occ_blocks::cpu0 347.331950 # Average occupied blocks per requestor
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+system.cpu0.l1c.occ_percent::total 0.678383 # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits::cpu0 7530 # number of ReadReq hits
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+system.cpu0.l1c.ReadReq_miss_latency::total 1299667421 # number of ReadReq miss cycles
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+system.cpu0.l1c.overall_miss_latency::total 2301175513 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 44809 # number of ReadReq accesses(hits+misses)
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+system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822 # average overall miss latency
system.cpu0.l1c.blocked_cycles::no_mshrs 253845135 # number of cycles access was blocked
system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.l1c.blocked::no_mshrs 69110 # number of cycles access was blocked
system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu0.l1c.fast_writes 0 # number of fast writes performed
system.cpu0.l1c.cache_copies 0 # number of cache copies performed
-system.cpu0.l1c.writebacks 11972 # number of writebacks
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-system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu0.l1c.ReadReq_mshr_misses 37279 # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses 23202 # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses 60481 # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses 60481 # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency 1262244251 # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency 978215253 # number of WriteReq MSHR miss cycles
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-system.cpu0.l1c.overall_mshr_miss_latency 2240459504 # number of overall MSHR miss cycles
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-system.cpu0.l1c.overall_mshr_miss_rate 0.875648 # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373 # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007 # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156 # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156 # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
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-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.num_reads 98493 # number of read accesses completed
system.cpu1.num_writes 53671 # number of write accesses completed
system.cpu1.num_copies 0 # number of copy accesses completed
system.cpu1.l1c.replacements 27684 # number of replacements
-system.cpu1.l1c.tagsinuse 93.018974 # Cycle average of tags in use
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system.cpu1.l1c.total_refs 11419 # Total number of references to valid blocks.
system.cpu1.l1c.sampled_refs 28039 # Sample count of references to valid blocks.
system.cpu1.l1c.avg_refs 0.407254 # Average number of references to valid blocks.
system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.occ_blocks::0 345.656340 # Average occupied blocks per context
-system.cpu1.l1c.occ_blocks::1 -252.637366 # Average occupied blocks per context
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-system.cpu1.l1c.occ_percent::1 -0.493432 # Average percentage of cache occupancy
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-system.cpu1.l1c.ReadReq_avg_miss_latency 35078.437375 # average ReadReq miss latency
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-system.cpu1.l1c.overall_avg_miss_latency 38354.853291 # average overall miss latency
+system.cpu1.l1c.occ_blocks::cpu1 345.656340 # Average occupied blocks per requestor
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+system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291 # average overall miss latency
system.cpu1.l1c.blocked_cycles::no_mshrs 253325402 # number of cycles access was blocked
system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu1.l1c.blocked::no_mshrs 68822 # number of cycles access was blocked
system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu1.l1c.fast_writes 0 # number of fast writes performed
system.cpu1.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu1.l1c.ReadReq_mshr_misses 37110 # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses 23275 # number of WriteReq MSHR misses
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-system.cpu1.l1c.overall_mshr_misses 60385 # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency 1264508347 # number of ReadReq MSHR miss cycles
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-system.cpu1.l1c.overall_mshr_miss_latency 2255442236 # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 877119159 # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 578327433 # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency 1455446592 # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate 0.833202 # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate 0.956206 # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate 0.876670 # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate 0.876670 # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410 # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825 # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793 # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793 # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
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+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 877119159 # number of ReadReq MSHR uncacheable cycles
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+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 578327433 # number of WriteReq MSHR uncacheable cycles
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+system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1455446592 # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.833202 # mshr miss rate for ReadReq accesses
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+system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.876670 # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410 # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825 # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793 # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
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system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu4.num_writes 53533 # number of write accesses completed
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system.cpu4.l1c.total_refs 11724 # Total number of references to valid blocks.
system.cpu4.l1c.sampled_refs 28041 # Sample count of references to valid blocks.
system.cpu4.l1c.avg_refs 0.418102 # Average number of references to valid blocks.
system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu4.l1c.blocked_cycles::no_mshrs 254136532 # number of cycles access was blocked
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system.cpu4.l1c.blocked::no_mshrs 68868 # number of cycles access was blocked
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system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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system.cpu5.num_writes 53710 # number of write accesses completed
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system.cpu5.l1c.total_refs 11748 # Total number of references to valid blocks.
system.cpu5.l1c.sampled_refs 28191 # Sample count of references to valid blocks.
system.cpu5.l1c.avg_refs 0.416729 # Average number of references to valid blocks.
system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu5.l1c.ReadReq_miss_latency::total 1291933371 # number of ReadReq miss cycles
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+system.cpu5.l1c.demand_miss_latency::cpu5 2290237416 # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total 2290237416 # number of demand (read+write) miss cycles
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+system.cpu5.l1c.overall_miss_latency::total 2290237416 # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5 44941 # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total 44941 # number of ReadReq accesses(hits+misses)
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+system.cpu5.l1c.WriteReq_accesses::total 24139 # number of WriteReq accesses(hits+misses)
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+system.cpu5.l1c.overall_accesses::total 69080 # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.831067 # miss rate for ReadReq accesses
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+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352 # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563 # average WriteReq miss latency
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+system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625 # average overall miss latency
system.cpu5.l1c.blocked_cycles::no_mshrs 253381114 # number of cycles access was blocked
system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu5.l1c.blocked::no_mshrs 68969 # number of cycles access was blocked
system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu5.l1c.fast_writes 0 # number of fast writes performed
system.cpu5.l1c.cache_copies 0 # number of cache copies performed
-system.cpu5.l1c.writebacks 11908 # number of writebacks
-system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu5.l1c.ReadReq_mshr_misses 37349 # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses 23013 # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses 60362 # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses 60362 # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency 1254436910 # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency 975203983 # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency 2229640893 # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency 2229640893 # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 902856034 # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 567587171 # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency 1470443205 # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate 0.831067 # mshr miss rate for ReadReq accesses
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-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160 # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397 # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349 # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349 # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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-system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu6.num_reads 99389 # number of read accesses completed
system.cpu6.num_writes 53686 # number of write accesses completed
system.cpu6.num_copies 0 # number of copy accesses completed
system.cpu6.l1c.replacements 27861 # number of replacements
-system.cpu6.l1c.tagsinuse 89.788098 # Cycle average of tags in use
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system.cpu6.l1c.total_refs 11520 # Total number of references to valid blocks.
system.cpu6.l1c.sampled_refs 28198 # Sample count of references to valid blocks.
system.cpu6.l1c.avg_refs 0.408540 # Average number of references to valid blocks.
system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.occ_blocks::0 347.289326 # Average occupied blocks per context
-system.cpu6.l1c.occ_blocks::1 -257.501227 # Average occupied blocks per context
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-system.cpu6.l1c.occ_percent::1 -0.502932 # Average percentage of cache occupancy
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-system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844 # average ReadReq miss latency
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-system.cpu6.l1c.overall_avg_miss_latency 38432.141740 # average overall miss latency
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system.cpu6.l1c.blocked_cycles::no_mshrs 253794713 # number of cycles access was blocked
system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu6.l1c.blocked::no_mshrs 68612 # number of cycles access was blocked
system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu6.l1c.fast_writes 0 # number of fast writes performed
system.cpu6.l1c.cache_copies 0 # number of cache copies performed
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-system.cpu6.l1c.ReadReq_mshr_misses 37109 # number of ReadReq MSHR misses
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-system.cpu6.l1c.demand_mshr_misses 60251 # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses 60251 # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency 1262548698 # number of ReadReq MSHR miss cycles
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-system.cpu6.l1c.demand_mshr_miss_latency 2255089912 # number of demand (read+write) MSHR miss cycles
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-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 877981455 # number of ReadReq MSHR uncacheable cycles
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-system.cpu6.l1c.overall_mshr_uncacheable_latency 1452670464 # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831071 # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate 0.953877 # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate 0.874305 # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate 0.874305 # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723 # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809 # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992 # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992 # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
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+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 574689009 # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 574689009 # number of WriteReq MSHR uncacheable cycles
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+system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1452670464 # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.831071 # mshr miss rate for ReadReq accesses
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+system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.874305 # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723 # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809 # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992 # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu7.num_reads 99694 # number of read accesses completed
system.cpu7.num_writes 53501 # number of write accesses completed
system.cpu7.num_copies 0 # number of copy accesses completed
system.cpu7.l1c.replacements 27727 # number of replacements
-system.cpu7.l1c.tagsinuse 84.250612 # Cycle average of tags in use
+system.cpu7.l1c.tagsinuse 346.094259 # Cycle average of tags in use
system.cpu7.l1c.total_refs 11534 # Total number of references to valid blocks.
system.cpu7.l1c.sampled_refs 28062 # Sample count of references to valid blocks.
system.cpu7.l1c.avg_refs 0.411018 # Average number of references to valid blocks.
system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.occ_blocks::0 346.094259 # Average occupied blocks per context
-system.cpu7.l1c.occ_blocks::1 -261.843648 # Average occupied blocks per context
-system.cpu7.l1c.occ_percent::0 0.675965 # Average percentage of cache occupancy
-system.cpu7.l1c.occ_percent::1 -0.511413 # Average percentage of cache occupancy
-system.cpu7.l1c.ReadReq_hits 7593 # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits 1111 # number of WriteReq hits
-system.cpu7.l1c.demand_hits 8704 # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits 8704 # number of overall hits
-system.cpu7.l1c.ReadReq_misses 37155 # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses 23121 # number of WriteReq misses
-system.cpu7.l1c.demand_misses 60276 # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses 60276 # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency 1287127315 # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency 1006139538 # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency 2293266853 # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency 2293266853 # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses 44748 # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses 24232 # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses 68980 # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses 68980 # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate 0.830316 # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate 0.954152 # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate 0.873818 # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate 0.873818 # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409 # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916 # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency 38046.102147 # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency 38046.102147 # average overall miss latency
+system.cpu7.l1c.occ_blocks::cpu7 346.094259 # Average occupied blocks per requestor
+system.cpu7.l1c.occ_percent::cpu7 0.675965 # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::total 0.675965 # Average percentage of cache occupancy
+system.cpu7.l1c.ReadReq_hits::cpu7 7593 # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total 7593 # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7 1111 # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total 1111 # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7 8704 # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total 8704 # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7 8704 # number of overall hits
+system.cpu7.l1c.overall_hits::total 8704 # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7 37155 # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total 37155 # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7 23121 # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total 23121 # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7 60276 # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total 60276 # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7 60276 # number of overall misses
+system.cpu7.l1c.overall_misses::total 60276 # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7 1287127315 # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total 1287127315 # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7 1006139538 # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total 1006139538 # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7 2293266853 # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total 2293266853 # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7 2293266853 # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total 2293266853 # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7 44748 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total 44748 # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7 24232 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total 24232 # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7 68980 # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total 68980 # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7 68980 # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total 68980 # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.830316 # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954152 # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7 0.873818 # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7 0.873818 # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409 # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916 # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147 # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147 # average overall miss latency
system.cpu7.l1c.blocked_cycles::no_mshrs 254008986 # number of cycles access was blocked
system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu7.l1c.blocked::no_mshrs 69036 # number of cycles access was blocked
system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked
system.cpu7.l1c.fast_writes 0 # number of fast writes performed
system.cpu7.l1c.cache_copies 0 # number of cache copies performed
-system.cpu7.l1c.writebacks 11797 # number of writebacks
-system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
-system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits
-system.cpu7.l1c.ReadReq_mshr_misses 37155 # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses 23121 # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses 60276 # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses 60276 # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency 1249829653 # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency 982928032 # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency 2232757685 # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency 2232757685 # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 901961636 # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 558194703 # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency 1460156339 # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830316 # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate 0.954152 # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate 0.873818 # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate 0.873818 # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764 # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466 # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808 # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808 # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency
-system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated
-system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
+system.cpu7.l1c.writebacks::writebacks 11797 # number of writebacks
+system.cpu7.l1c.writebacks::total 11797 # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7 37155 # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total 37155 # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23121 # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total 23121 # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7 60276 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total 60276 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7 60276 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total 60276 # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1249829653 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1249829653 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 982928032 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total 982928032 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2232757685 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total 2232757685 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2232757685 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 2232757685 # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 901961636 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 901961636 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 558194703 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 558194703 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1460156339 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1460156339 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.830316 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954152 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.873818 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808 # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
check_flush=false
checks_to_complete=100
deadlock_threshold=50000
+system=system
wakeup_frequency=10
cpuPort=system.l1_cntrl0.sequencer.port[0]
================ End RubySystem Configuration Print ================
-Real time: Feb/12/2012 12:56:15
+Real time: Feb/12/2012 15:33:22
Profiler Stats
--------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
-Virtual_time_in_seconds: 0.46
-Virtual_time_in_minutes: 0.00766667
-Virtual_time_in_hours: 0.000127778
-Virtual_time_in_days: 5.32407e-06
+Virtual_time_in_seconds: 0.95
+Virtual_time_in_minutes: 0.0158333
+Virtual_time_in_hours: 0.000263889
+Virtual_time_in_days: 1.09954e-05
Ruby_current_time: 366301
Ruby_start_time: 0
Ruby_cycles: 366301
-mbytes_resident: 39.4219
-mbytes_total: 241.242
-resident_ratio: 0.163461
+mbytes_resident: 0
+mbytes_total: 0
ruby_cycles_executed: [ 366302 ]
page_size: 4096
user_time: 0
system_time: 0
-page_reclaims: 11076
-page_faults: 18
+page_reclaims: 11904
+page_faults: 0
swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 4
+block_outputs: 5
Network Stats
-------------
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Feb 12 2012 12:56:01
-gem5 started Feb 12 2012 12:56:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
Global frequency set at 1000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
sim_ticks 366301 # Number of ticks simulated
final_tick 366301 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000 # Frequency of simulated ticks
-host_tick_rate 1737283 # Simulator tick rate (ticks/s)
-host_mem_usage 247036 # Number of bytes of host memory used
-host_seconds 0.21 # Real time elapsed on the host
+host_tick_rate 728650 # Simulator tick rate (ticks/s)
+host_mem_usage 266424 # Number of bytes of host memory used
+host_seconds 0.50 # Real time elapsed on the host
system.physmem.bytes_read 0 # Number of bytes read from this memory
system.physmem.bytes_inst_read 0 # Number of instructions bytes read from this memory
system.physmem.bytes_written 0 # Number of bytes written to this memory
projects / gem5.git / commitdiff