stats: update stats for insts/ops and master id changes
authorAli Saidi <Ali.Saidi@ARM.com>
Sun, 12 Feb 2012 22:07:43 +0000 (16:07 -0600)
committerAli Saidi <Ali.Saidi@ARM.com>
Sun, 12 Feb 2012 22:07:43 +0000 (16:07 -0600)
403 files changed:
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/stats.txt
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/config.ini
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/simout
tests/long/se/00.gzip/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/config.ini
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/simout
tests/long/se/00.gzip/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/config.ini
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/simout
tests/long/se/00.gzip/ref/alpha/tru64/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/config.ini
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/simout
tests/long/se/00.gzip/ref/alpha/tru64/simple-timing/stats.txt
tests/long/se/00.gzip/ref/arm/linux/o3-timing/config.ini
tests/long/se/00.gzip/ref/arm/linux/o3-timing/simout
tests/long/se/00.gzip/ref/arm/linux/o3-timing/stats.txt
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/config.ini
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/simout
tests/long/se/00.gzip/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/arm/linux/simple-timing/config.ini
tests/long/se/00.gzip/ref/arm/linux/simple-timing/simout
tests/long/se/00.gzip/ref/arm/linux/simple-timing/stats.txt
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/config.ini
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/simout
tests/long/se/00.gzip/ref/sparc/linux/o3-timing/stats.txt
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/simout
tests/long/se/00.gzip/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/config.ini
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/simout
tests/long/se/00.gzip/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/00.gzip/ref/x86/linux/o3-timing/config.ini
tests/long/se/00.gzip/ref/x86/linux/o3-timing/simout
tests/long/se/00.gzip/ref/x86/linux/o3-timing/stats.txt
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/config.ini
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/simout
tests/long/se/00.gzip/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/00.gzip/ref/x86/linux/simple-timing/config.ini
tests/long/se/00.gzip/ref/x86/linux/simple-timing/simout
tests/long/se/00.gzip/ref/x86/linux/simple-timing/stats.txt
tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
tests/long/se/10.mcf/ref/arm/linux/o3-timing/stats.txt
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
tests/long/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
tests/long/se/10.mcf/ref/arm/linux/simple-timing/stats.txt
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
tests/long/se/10.mcf/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
tests/long/se/10.mcf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
tests/long/se/10.mcf/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
tests/long/se/10.mcf/ref/x86/linux/simple-timing/stats.txt
tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
tests/long/se/20.parser/ref/arm/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
tests/long/se/20.parser/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
tests/long/se/20.parser/ref/arm/linux/simple-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
tests/long/se/20.parser/ref/x86/linux/o3-timing/stats.txt
tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
tests/long/se/20.parser/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
tests/long/se/20.parser/ref/x86/linux/simple-timing/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
tests/long/se/30.eon/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/stats.txt
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
tests/long/se/30.eon/ref/alpha/tru64/simple-timing/stats.txt
tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
tests/long/se/30.eon/ref/arm/linux/o3-timing/stats.txt
tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
tests/long/se/30.eon/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
tests/long/se/30.eon/ref/arm/linux/simple-timing/stats.txt
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/stats.txt
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/stats.txt
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/stats.txt
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/stats.txt
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/stats.txt
tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
tests/long/se/50.vortex/ref/arm/linux/o3-timing/stats.txt
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
tests/long/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
tests/long/se/50.vortex/ref/arm/linux/simple-timing/stats.txt
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
tests/long/se/50.vortex/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/stats.txt
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/stats.txt
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
tests/long/se/60.bzip2/ref/arm/linux/o3-timing/stats.txt
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
tests/long/se/60.bzip2/ref/arm/linux/simple-timing/stats.txt
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
tests/long/se/60.bzip2/ref/x86/linux/simple-timing/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/stats.txt
tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
tests/long/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
tests/long/se/70.twolf/ref/arm/linux/simple-timing/stats.txt
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
tests/long/se/70.twolf/ref/sparc/linux/simple-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
tests/long/se/70.twolf/ref/x86/linux/o3-timing/stats.txt
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
tests/long/se/70.twolf/ref/x86/linux/simple-atomic/stats.txt
tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
tests/long/se/70.twolf/ref/x86/linux/simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
tests/quick/se/00.hello/ref/alpha/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/stats.txt
tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/mips/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
tests/quick/se/00.hello/ref/mips/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/power/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
tests/quick/se/00.hello/ref/sparc/linux/simple-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
tests/quick/se/00.hello/ref/x86/linux/simple-atomic/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
tests/quick/se/00.hello/ref/x86/linux/simple-timing/stats.txt
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/stats.txt
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/stats.txt
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
tests/quick/se/50.memtest/ref/alpha/linux/memtest/config.ini
tests/quick/se/50.memtest/ref/alpha/linux/memtest/simout
tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt

index 46790add4b0f92bc43d4e72da45799225a102e27..62b96c7c4d3b68629e6e41e119224fcd61d5cdb5 100644 (file)
@@ -11,14 +11,14 @@ type=LinuxAlphaSystem
 children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -152,20 +152,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -451,20 +444,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -590,20 +576,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -889,20 +868,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -937,7 +909,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -957,7 +929,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -986,20 +958,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -1018,20 +983,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -1085,7 +1043,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
index fd99ca0d025395769c876c17d2121893fa8e2347..70213a160c305c3c334d2937ad94ea1f5a6f01cb 100755 (executable)
@@ -1,15 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  3 2012 13:46:22
-gem5 started Feb  3 2012 13:46:34
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:47:49
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 106949500
 Exiting @ tick 1897464893500 because m5_exit instruction encountered
index 78411ca4d8cfa79ad64b3224f23f1fca1f6ef4e8..89ae1dc03aa822ee3c2e4dfa4af8142371fc98c5 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.897465                       # Nu
 sim_ticks                                1897464893500                       # Number of ticks simulated
 final_tick                               1897464893500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100310                       # Simulator instruction rate (inst/s)
-host_tick_rate                             3391719918                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 326488                       # Number of bytes of host memory used
-host_seconds                                   559.44                       # Real time elapsed on the host
+host_inst_rate                                 189830                       # Simulator instruction rate (inst/s)
+host_op_rate                                   189830                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6418636186                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 296280                       # Number of bytes of host memory used
+host_seconds                                   295.62                       # Real time elapsed on the host
 sim_insts                                    56117221                       # Number of instructions simulated
+sim_ops                                      56117221                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    30408512                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1099328                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10470144                       # Number of bytes written to this memory
@@ -25,122 +27,153 @@ system.l2c.total_refs                         2482376                       # To
 system.l2c.sampled_refs                        433566                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          5.725486                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    9252063000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 12005.589305                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   237.479904                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 22866.713220                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.183191                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.003624                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.348918                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1720206                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     147304                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        22866.713220                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          4068.067496                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          7937.521810                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           126.484558                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data           110.995347                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.348918                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.062074                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.121117                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.001930                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.001694                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.535733                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             955732                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             764474                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             109195                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              38109                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1867510                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   827202                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          827202                       # number of Writeback hits
 system.l2c.Writeback_hits::total               827202                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     175                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                      45                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data             175                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              45                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 220                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                    29                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                    27                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            29                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            27                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                56                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   168180                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    11095                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data           168180                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            11095                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               179275                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1888386                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      158399                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              955732                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              932654                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              109195                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               49204                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 2046785                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1888386                       # number of overall hits
-system.l2c.overall_hits::1                     158399                       # number of overall hits
-system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             955732                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             932654                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             109195                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              49204                       # number of overall hits
 system.l2c.overall_hits::total                2046785                       # number of overall hits
-system.l2c.ReadReq_misses::0                   305580                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     4046                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            15234                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           290346                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             1960                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             2086                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               309626                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  2447                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                   562                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2447                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           562                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              3009                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                  45                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                  84                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           45                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           84                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total             129                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                 113888                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  10746                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data         113888                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          10746                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             124634                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    419468                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     14792                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             15234                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            404234                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              1960                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             12832                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                434260                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   419468                       # number of overall misses
-system.l2c.overall_misses::1                    14792                       # number of overall misses
-system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            15234                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           404234                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             1960                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            12832                       # number of overall misses
 system.l2c.overall_misses::total               434260                       # number of overall misses
-system.l2c.ReadReq_miss_latency           16117985000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency            4084000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency           629500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6538201500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            22656186500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           22656186500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2025786                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 151350                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0.inst    796850500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  15107982000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    102548000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    110604500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    16117985000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      2465000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data      1619000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      4084000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       420000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       209500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       629500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5974507500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    563694000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6538201500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    796850500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  21082489500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    102548000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    674298500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     22656186500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    796850500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  21082489500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    102548000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    674298500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    22656186500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         970966                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1054820                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         111155                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          40195                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2177136                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               827202                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       827202                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           827202                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2622                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                 607                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2622                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          607                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            3229                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0                74                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               111                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           74                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          111                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total           185                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               282068                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                21841                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       282068                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        21841                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           303909                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2307854                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  173191                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          970966                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1336888                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          111155                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           62036                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2481045                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2307854                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 173191                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         970966                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1336888                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         111155                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          62036                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2481045                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.150845                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.026733                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.933257                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.925865                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.608108                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.756757                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.403761                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.492010                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.181757                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.085409                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.181757                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.085409                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52745.549447                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   3983683.885319                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  1668.982427                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1  7266.903915                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0 13988.888889                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1  7494.047619                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 57409.046607                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 608431.183696                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    54011.716031                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    1531651.331801                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   54011.716031                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   1531651.331801                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015690                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.275256                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.017633                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.051897                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933257                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.925865                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.608108                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.756757                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.403761                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.492010                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015690                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.302369                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.017633                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.206848                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015690                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.302369                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.017633                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.206848                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52307.371669                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52034.407224                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52320.408163                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 53022.291467                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  1007.355946                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2880.782918                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  9333.333333                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  2494.047619                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52459.499684                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52456.169738                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52307.371669                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52154.171841                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52320.408163                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52548.199813                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52307.371669                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52154.171841                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52320.408163                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52548.199813                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -149,61 +182,116 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          122076                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                       18                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                        18                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                       18                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                 309608                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                3009                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses               129                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               124634                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  434242                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 434242                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency      12394422500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     120428500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency      5161500                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5022578000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency       17417000500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency      17417000500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency    838122000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1420361498                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   2258483498                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.152834                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         2.045643                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.147597                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      4.957166                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.743243                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.162162                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.441858                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       5.706424                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.188158                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          2.507301                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.188158                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         2.507301                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40032.629971                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40022.765038                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40011.627907                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40298.618355                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40108.972647                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40108.972647                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              122076                       # number of writebacks
+system.l2c.writebacks::total                   122076                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu1.inst            16                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data             2                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                18                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             16                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data              2                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 18                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst            16                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data             2                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                18                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst        15234                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       290346                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         1944                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         2084                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          309608                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2447                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          562                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3009                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           45                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           84                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total          129                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       113888                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        10746                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        124634                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        15234                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       404234                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         1944                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        12830                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           434242                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        15234                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       404234                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         1944                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        12830                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          434242                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    610356500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  11621105000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     77934000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     85027000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  12394422500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     97946500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     22482000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    120428500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data      1801500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      3360000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      5161500                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4590092500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    432485500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5022578000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    610356500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  16211197500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     77934000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    517512500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  17417000500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    610356500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  16211197500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     77934000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    517512500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  17417000500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    821008500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     17113500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    838122000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1130592498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    289769000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1420361498                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1951600998                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    306882500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   2258483498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015690                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.275256                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.017489                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.051847                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933257                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.925865                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.608108                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.756757                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.403761                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.492010                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015690                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.302369                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.017489                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.206815                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015690                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.302369                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.017489                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.206815                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40065.412892                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40025.021870                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40089.506173                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40799.904031                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40027.176134                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40003.558719                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40033.333333                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40303.565784                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40246.184627                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40065.412892                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40103.498221                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40089.506173                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40336.126267                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40065.412892                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40103.498221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40089.506173                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40336.126267                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41697                       # number of replacements
 system.iocache.tagsinuse                     0.463236                       # Cycle average of tags in use
@@ -211,58 +299,41 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     41713                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1709322783000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.463236                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.028952                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  177                       # number of ReadReq misses
+system.iocache.occ_blocks::tsunami.ide       0.463236                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.028952                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.028952                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          177                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              177                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41729                       # number of demand (read+write) misses
+system.iocache.demand_misses::tsunami.ide        41729                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41729                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41729                       # number of overall misses
+system.iocache.overall_misses::tsunami.ide        41729                       # number of overall misses
 system.iocache.overall_misses::total            41729                       # number of overall misses
-system.iocache.ReadReq_miss_latency          20391998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       5720293806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         5740685804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        5740685804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                177                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_latency::tsunami.ide     20391998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     20391998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   5720293806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5720293806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5740685804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5740685804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5740685804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5740685804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          177                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            177                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41729                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41729                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41729                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41729                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41729                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41729                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115209.028249                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137665.907923                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137570.653598                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137570.653598                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115209.028249                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137665.907923                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 137570.653598                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 137570.653598                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64638062                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10457                       # number of cycles access was blocked
@@ -271,38 +342,32 @@ system.iocache.avg_blocked_cycles::no_mshrs  6181.319881                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41520                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                177                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               41729                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              41729                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     11187998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3559436992                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    3570624990                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   3570624990                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63209.028249                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85662.230266                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85566.991541                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85566.991541                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          177                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          177                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41729                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41729                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41729                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41729                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11187998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11187998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3559436992                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3559436992                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3570624990                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3570624990                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3570624990                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3570624990                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63209.028249                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85662.230266                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85566.991541                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85566.991541                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -570,6 +635,7 @@ system.cpu0.iew.wb_rate                      0.479623                       # in
 system.cpu0.iew.wb_fanout                    0.742958                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu0.commit.commitCommittedInsts      53643051                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        53643051                       # The number of committed instructions
 system.cpu0.commit.commitSquashedInsts        8183882                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls         637663                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts           648245                       # The number of times a branch was mispredicted
@@ -590,7 +656,8 @@ system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::total     76953268                       # Number of insts commited each cycle
-system.cpu0.commit.count                     53643051                       # Number of instructions committed
+system.cpu0.commit.committedInsts            53643051                       # Number of instructions committed
+system.cpu0.commit.committedOps              53643051                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu0.commit.refs                      14593748                       # Number of memory references committed
 system.cpu0.commit.loads                      8594447                       # Number of loads committed
@@ -607,6 +674,7 @@ system.cpu0.timesIdled                        1231743                       # Nu
 system.cpu0.idleCycles                       33834806                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu0.quiesceCycles                  3682779567                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu0.committedInsts                   50529139                       # Number of Instructions Simulated
+system.cpu0.committedOps                     50529139                       # Number of Ops (including micro ops) Simulated
 system.cpu0.committedInsts_total             50529139                       # Number of Instructions Simulated
 system.cpu0.cpi                              2.219390                       # CPI: Cycles Per Instruction
 system.cpu0.cpi_total                        2.219390                       # CPI: Total CPI of All Threads
@@ -655,51 +723,39 @@ system.cpu0.icache.total_refs                 7511566                       # To
 system.cpu0.icache.sampled_refs                970922                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                  7.736529                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           23358767000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           510.008513                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.996110                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0            7511566                       # number of ReadReq hits
+system.cpu0.icache.occ_blocks::cpu0.inst   510.008513                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.996110                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.996110                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      7511566                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total        7511566                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0             7511566                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu0.inst      7511566                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::total         7511566                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0            7511566                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu0.inst      7511566                       # number of overall hits
 system.cpu0.icache.overall_hits::total        7511566                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0          1025306                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu0.inst      1025306                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total      1025306                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0           1025306                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu0.inst      1025306                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total       1025306                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0          1025306                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu0.inst      1025306                       # number of overall misses
 system.cpu0.icache.overall_misses::total      1025306                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency   15323045497                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency    15323045497                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency   15323045497                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0        8536872                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  15323045497                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  15323045497                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  15323045497                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  15323045497                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  15323045497                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  15323045497                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      8536872                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total      8536872                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0         8536872                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu0.inst      8536872                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::total      8536872                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0        8536872                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      8536872                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total      8536872                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.120103                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.120103                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.120103                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14944.851095                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14944.851095                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14944.851095                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.120103                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.120103                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.120103                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14944.851095                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14944.851095                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14944.851095                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs      1297498                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs              107                       # number of cycles access was blocked
@@ -708,120 +764,102 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs 12126.149533
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                     220                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits            54249                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits             54249                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits            54249                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses         971057                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses          971057                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses         971057                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency  11617533498                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency  11617533498                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency  11617533498                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.113749                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0     0.113749                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0     0.113749                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11963.801814                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11963.801814                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11963.801814                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.writebacks::writebacks          220                       # number of writebacks
+system.cpu0.icache.writebacks::total              220                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        54249                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        54249                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        54249                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        54249                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        54249                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        54249                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       971057                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       971057                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       971057                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       971057                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       971057                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       971057                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  11617533498                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  11617533498                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  11617533498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  11617533498                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  11617533498                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  11617533498                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.113749                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.113749                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.113749                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11963.801814                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11963.801814                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11963.801814                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements               1340651                       # number of replacements
-system.cpu0.dcache.tagsinuse               503.872538                       # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse               504.872538                       # Cycle average of tags in use
 system.cpu0.dcache.total_refs                11358067                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs               1341162                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                  8.468826                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           504.872538                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.986079                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            6993872                       # number of ReadReq hits
+system.cpu0.dcache.warmup_cycle              19222000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   504.872538                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.986079                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.986079                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      6993872                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        6993872                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           3966970                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      3966970                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total       3966970                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       182544                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       182544                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       182544                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::       208490                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       208490                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       208490                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0            10960842                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data     10960842                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::total        10960842                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0           10960842                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu0.data     10960842                       # number of overall hits
 system.cpu0.dcache.overall_hits::total       10960842                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0          1697480                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1697480                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      1697480                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0         1808304                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1808304                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total      1808304                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0        21693                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        21693                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total        21693                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0          688                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          688                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total          688                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0           3505784                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data      3505784                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total       3505784                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0          3505784                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu0.data      3505784                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      3505784                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency   37053025000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency  55161743853                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency    326351000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency      6342500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency    92214768853                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency   92214768853                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        8691352                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  37053025000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  37053025000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  55161743853                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  55161743853                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    326351000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    326351000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      6342500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      6342500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  92214768853                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  92214768853                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  92214768853                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  92214768853                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8691352                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      8691352                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::      5775274                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5775274                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5775274                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       204237                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       204237                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       204237                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       209178                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       209178                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       209178                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        14466626                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     14466626                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total     14466626                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       14466626                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14466626                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14466626                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.195307                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.313111                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.106215                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003289                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.242336                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.242336                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 21828.254236                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 30504.684972                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 15044.069516                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  9218.750000                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 26303.608224                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 26303.608224                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.195307                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.313111                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.106215                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003289                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.242336                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.242336                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 21828.254236                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 30504.684972                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15044.069516                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  9218.750000                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26303.608224                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26303.608224                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs    888039305                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets       192000                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs            98700                       # number of cycles access was blocked
@@ -830,57 +868,63 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8997.358713
 system.cpu0.dcache.avg_blocked_cycles::no_targets        24000                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  791009                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits           651385                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits         1523767                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits         4864                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits           2175152                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits          2175152                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses        1046095                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses        284537                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        16829                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses          688                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses         1330632                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses        1330632                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  24225951000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency   8293520304                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    195490000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency      4269500                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency  32519471304                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency  32519471304                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    916801000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1252089998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2168890998                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.120360                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049268                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.082399                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.003289                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.091979                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.091979                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 23158.461708                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 29147.423021                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11616.257650                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  6205.668605                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 24439.117129                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 24439.117129                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks       791009                       # number of writebacks
+system.cpu0.dcache.writebacks::total           791009                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       651385                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       651385                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1523767                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1523767                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data         4864                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total         4864                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      2175152                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      2175152                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      2175152                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      2175152                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1046095                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1046095                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       284537                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       284537                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16829                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16829                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          688                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          688                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1330632                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1330632                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1330632                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1330632                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  24225951000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  24225951000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8293520304                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8293520304                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    195490000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    195490000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      4269500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      4269500                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  32519471304                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  32519471304                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  32519471304                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  32519471304                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    916801000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    916801000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1252089998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1252089998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2168890998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2168890998                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.120360                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049268                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.082399                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.003289                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.091979                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.091979                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 23158.461708                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 29147.423021                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11616.257650                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  6205.668605                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24439.117129                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24439.117129                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
@@ -1136,6 +1180,7 @@ system.cpu1.iew.wb_rate                      0.614403                       # in
 system.cpu1.iew.wb_fanout                    0.731621                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu1.commit.commitCommittedInsts       5811574                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps         5811574                       # The number of committed instructions
 system.cpu1.commit.commitSquashedInsts        1309607                       # The number of squashed insts skipped by commit
 system.cpu1.commit.commitNonSpecStalls          75493                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu1.commit.branchMispredicts           100450                       # The number of times a branch was mispredicted
@@ -1156,7 +1201,8 @@ system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::total      9046955                       # Number of insts commited each cycle
-system.cpu1.commit.count                      5811574                       # Number of instructions committed
+system.cpu1.commit.committedInsts             5811574                       # Number of instructions committed
+system.cpu1.commit.committedOps               5811574                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu1.commit.refs                       1881487                       # Number of memory references committed
 system.cpu1.commit.loads                      1153406                       # Number of loads committed
@@ -1173,6 +1219,7 @@ system.cpu1.timesIdled                          81901                       # Nu
 system.cpu1.idleCycles                         697375                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu1.quiesceCycles                  3784961926                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu1.committedInsts                    5588082                       # Number of Instructions Simulated
+system.cpu1.committedOps                      5588082                       # Number of Ops (including micro ops) Simulated
 system.cpu1.committedInsts_total              5588082                       # Number of Instructions Simulated
 system.cpu1.cpi                              1.783238                       # CPI: Cycles Per Instruction
 system.cpu1.cpi_total                        1.783238                       # CPI: Total CPI of All Threads
@@ -1190,51 +1237,39 @@ system.cpu1.icache.total_refs                  936898                       # To
 system.cpu1.icache.sampled_refs                111117                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                  8.431635                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle          1874818624000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           453.435417                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.885616                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0             936898                       # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst   453.435417                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.885616                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.885616                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst       936898                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         936898                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0              936898                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::cpu1.inst       936898                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::total          936898                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0             936898                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::cpu1.inst       936898                       # number of overall hits
 system.cpu1.icache.overall_hits::total         936898                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0           116421                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::cpu1.inst       116421                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total       116421                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0            116421                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst       116421                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total        116421                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0           116421                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst       116421                       # number of overall misses
 system.cpu1.icache.overall_misses::total       116421                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency    1750783999                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency     1750783999                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency    1750783999                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0        1053319                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1750783999                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   1750783999                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   1750783999                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   1750783999                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   1750783999                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   1750783999                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      1053319                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total      1053319                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0         1053319                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::cpu1.inst      1053319                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::total      1053319                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0        1053319                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      1053319                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      1053319                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.110528                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.110528                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.110528                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 15038.386537                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 15038.386537                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 15038.386537                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.110528                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.110528                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.110528                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15038.386537                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15038.386537                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15038.386537                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs        96999                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs               14                       # number of cycles access was blocked
@@ -1243,33 +1278,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs  6928.500000
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                      37                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits             5236                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits              5236                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits             5236                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses         111185                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses          111185                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses         111185                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   1333353499                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency   1333353499                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency   1333353499                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.105557                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0     0.105557                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0     0.105557                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11992.206674                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11992.206674                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11992.206674                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks           37                       # number of writebacks
+system.cpu1.icache.writebacks::total               37                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst         5236                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total         5236                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst         5236                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total         5236                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst         5236                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total         5236                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       111185                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       111185                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       111185                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       111185                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       111185                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       111185                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   1333353499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   1333353499                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   1333353499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   1333353499                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   1333353499                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   1333353499                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.105557                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.105557                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.105557                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11992.206674                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11992.206674                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11992.206674                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                 62388                       # number of replacements
 system.cpu1.dcache.tagsinuse               392.324021                       # Cycle average of tags in use
@@ -1277,84 +1311,69 @@ system.cpu1.dcache.total_refs                 1699992                       # To
 system.cpu1.dcache.sampled_refs                 62715                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                 27.106625                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1874614053500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           392.324021                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.766258                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            1127254                       # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data   392.324021                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.766258                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.766258                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1127254                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        1127254                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0            549515                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       549515                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total        549515                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0        16791                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        16791                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        16791                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::        14923                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        14923                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        14923                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0             1676769                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data      1676769                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total         1676769                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0            1676769                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data      1676769                       # number of overall hits
 system.cpu1.dcache.overall_hits::total        1676769                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0           106582                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data       106582                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total       106582                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0          157839                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       157839                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total       157839                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0         1481                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1481                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total         1481                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0          695                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          695                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total          695                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0            264421                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data       264421                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total        264421                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0           264421                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data       264421                       # number of overall misses
 system.cpu1.dcache.overall_misses::total       264421                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency    1787903500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency   5181152780                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency     19396000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency      8380000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency     6969056280                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency    6969056280                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        1233836                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   1787903500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   1787903500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   5181152780                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   5181152780                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     19396000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     19396000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      8380000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      8380000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6969056280                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6969056280                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6969056280                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6969056280                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1233836                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      1233836                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::       707354                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data       707354                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total       707354                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0        18272                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        18272                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        18272                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0        15618                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        15618                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        15618                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0         1941190                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data      1941190                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total      1941190                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0        1941190                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      1941190                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1941190                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.086383                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.223140                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.081053                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044500                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.136216                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.136216                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 16774.910398                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 32825.555028                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13096.556381                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12057.553957                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 26355.910764                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 26355.910764                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.086383                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.223140                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.081053                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044500                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.136216                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.136216                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16774.910398                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 32825.555028                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.556381                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12057.553957                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26355.910764                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 26355.910764                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs     86281997                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs             6886                       # number of cycles access was blocked
@@ -1363,57 +1382,63 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs 12530.060558
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                   35937                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits            62835                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits          134042                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits          295                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits            196877                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits           196877                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses          43747                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses         23797                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses         1186                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses          695                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses           67544                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses          67544                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency    555340000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency    753314485                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     11632000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency      6287000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency   1308654485                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency   1308654485                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     19116500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    320800500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency    339917000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035456                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.033642                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.064908                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.044500                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.034795                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.034795                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 12694.356184                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 31655.859352                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  9807.757167                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9046.043165                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 19374.844324                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 19374.844324                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks        35937                       # number of writebacks
+system.cpu1.dcache.writebacks::total            35937                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data        62835                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total        62835                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data       134042                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total       134042                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data          295                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total          295                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data       196877                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total       196877                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data       196877                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total       196877                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        43747                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        43747                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        23797                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        23797                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data         1186                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total         1186                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          695                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          695                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data        67544                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total        67544                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data        67544                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total        67544                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    555340000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    555340000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    753314485                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    753314485                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     11632000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     11632000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      6287000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      6287000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   1308654485                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   1308654485                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   1308654485                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   1308654485                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     19116500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     19116500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    320800500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    320800500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    339917000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    339917000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035456                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.033642                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.064908                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.044500                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034795                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034795                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12694.356184                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31655.859352                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  9807.757167                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  9046.043165                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19374.844324                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19374.844324                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                    6366                       # number of quiesce instructions executed
index c884dc4821ef9556a5e18fe9cae8d642eea87a0d..ecd4c00a8c89111526cb6bf11507471db684f2c3 100644 (file)
@@ -11,14 +11,14 @@ type=LinuxAlphaSystem
 children=bridge cpu disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-console=/scratch/nilay/GEM5/system/binaries/console
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 physmem=system.physmem
 readfile=tests/halt.sh
 symbolfile=
@@ -152,20 +152,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -451,20 +444,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -499,7 +485,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -519,7 +505,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -548,20 +534,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -580,20 +559,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -647,7 +619,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
index 0ab209212a7aa8446718ea5c14520f44d06e7a20..c3587ff5d9e63ddcdecdc17cb694648f312edfac 100755 (executable)
@@ -1,14 +1,11 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  3 2012 13:46:22
-gem5 started Feb  3 2012 13:46:34
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:47:47
+gem5 executing on zizzer
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/fast/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1859850554500 because m5_exit instruction encountered
index 44b3ca5817710b5dbfa59491e5fd1e96de771c28..3b4a45a9b27776e84441f5356b100fb215066ea3 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.859851                       # Nu
 sim_ticks                                1859850554500                       # Number of ticks simulated
 final_tick                               1859850554500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 100457                       # Simulator instruction rate (inst/s)
-host_tick_rate                             3519496587                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 323652                       # Number of bytes of host memory used
-host_seconds                                   528.44                       # Real time elapsed on the host
+host_inst_rate                                 188989                       # Simulator instruction rate (inst/s)
+host_op_rate                                   188989                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             6621174751                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 292896                       # Number of bytes of host memory used
+host_seconds                                   280.89                       # Real time elapsed on the host
 sim_insts                                    53085804                       # Number of instructions simulated
+sim_ops                                      53085804                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    29820864                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1064000                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10193536                       # Number of bytes written to this memory
@@ -25,83 +27,89 @@ system.l2c.total_refs                         2406767                       # To
 system.l2c.sampled_refs                        424249                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          5.673006                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    5619831000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 12305.465353                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 22620.354669                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.187767                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.345159                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1800764                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        22620.354669                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           4081.669847                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           8223.795506                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.345159                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.062281                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.125485                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.532926                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst              988583                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              812181                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1800764                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   835189                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          835189                       # number of Writeback hits
 system.l2c.Writeback_hits::total               835189                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      16                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data               16                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  16                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                     2                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data              2                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                 2                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   183241                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            183241                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               183241                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1984005                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               988583                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               995422                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1984005                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1984005                       # number of overall hits
-system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              988583                       # number of overall hits
+system.l2c.overall_hits::cpu.data              995422                       # number of overall hits
 system.l2c.overall_hits::total                1984005                       # number of overall hits
-system.l2c.ReadReq_misses::0                   308137                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             16626                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            291511                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               308137                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                    35                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data             35                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                35                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 116889                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          116889                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             116889                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    425026                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              16626                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             408400                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                425026                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   425026                       # number of overall misses
-system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             16626                       # number of overall misses
+system.l2c.overall_misses::cpu.data            408400                       # number of overall misses
 system.l2c.overall_misses::total               425026                       # number of overall misses
-system.l2c.ReadReq_miss_latency           16037812500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency             424500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6132457500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            22170270000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           22170270000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2108901                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.inst    869674000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  15168138500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    16037812500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       424500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       424500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6132457500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6132457500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    869674000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  21300596000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     22170270000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    869674000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  21300596000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    22170270000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst         1005209                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1103692                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2108901                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               835189                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       835189                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           835189                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  51                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           51                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              51                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0                 2                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data            2                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total             2                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               300130                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        300130                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           300130                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2409031                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1005209                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1403822                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2409031                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2409031                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1005209                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1403822                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2409031                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.146113                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.686275                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.389461                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.176430                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.176430                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52047.668732                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 12128.571429                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52463.940148                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52162.150080                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52162.150080                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.inst       0.016540                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.264124                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.686275                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.389461                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.016540                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.290920                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.016540                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.290920                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52308.071695                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52032.816943                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 12128.571429                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52463.940148                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52308.071695                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52156.209598                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52308.071695                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52156.209598                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -110,48 +118,59 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          117762                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                 308137                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                  35                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               116889                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  425026                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 425026                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency      12334071500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency       1460000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4711233500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency       17045305000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency      17045305000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency    809589500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1114928998                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   1924518498                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.146113                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.686275                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.389461                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.176430                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.176430                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40027.882078                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 41714.285714                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40305.191250                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40104.146570                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40104.146570                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              117762                       # number of writebacks
+system.l2c.writebacks::total                   117762                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.inst        16626                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       291511                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          308137                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data           35                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           35                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       116889                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        116889                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         16626                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        408400                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           425026                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        16626                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       408400                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          425026                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    666148500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  11667923000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  12334071500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data      1460000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      1460000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4711233500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4711233500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    666148500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  16379156500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  17045305000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    666148500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  16379156500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  17045305000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    809589500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    809589500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1114928998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1114928998                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   1924518498                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1924518498                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.264124                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.686275                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.389461                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.290920                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.016540                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.290920                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40066.672681                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40025.669700                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 41714.285714                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40305.191250                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40066.672681                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40105.672135                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40066.672681                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40105.672135                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.tagsinuse                     1.276011                       # Cycle average of tags in use
@@ -159,58 +178,41 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1708338781000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 1.276011                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.079751                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
+system.iocache.occ_blocks::tsunami.ide       1.276011                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.079751                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.079751                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41725                       # number of overall misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency          19937998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       5721891806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         5741829804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        5741829804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_latency::tsunami.ide     19937998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     19937998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   5721891806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5721891806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5741829804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5741829804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5741829804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5741829804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115248.543353                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137704.365759                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137611.259533                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137611.259533                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115248.543353                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137704.365759                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 137611.259533                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 137611.259533                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64612060                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10475                       # number of cycles access was blocked
@@ -219,38 +221,32 @@ system.iocache.avg_blocked_cycles::no_mshrs  6168.215752                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41512                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     10941998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3561041984                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    3571983982                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   3571983982                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63248.543353                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85700.856373                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85607.764697                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85607.764697                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     10941998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     10941998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3561041984                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3561041984                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3571983982                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3571983982                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3571983982                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3571983982                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63248.543353                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85700.856373                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85607.764697                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85607.764697                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -518,6 +514,7 @@ system.cpu.iew.wb_rate                       0.487979                       # in
 system.cpu.iew.wb_fanout                     0.742132                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       56280196                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         56280196                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts         9036196                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls          667545                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            701106                       # The number of times a branch was mispredicted
@@ -538,7 +535,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total     80658204                       # Number of insts commited each cycle
-system.cpu.commit.count                      56280196                       # Number of instructions committed
+system.cpu.commit.committedInsts             56280196                       # Number of instructions committed
+system.cpu.commit.committedOps               56280196                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       15504446                       # Number of memory references committed
 system.cpu.commit.loads                       9112319                       # Number of loads committed
@@ -555,6 +553,7 @@ system.cpu.timesIdled                         1255783                       # Nu
 system.cpu.idleCycles                        34112637                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.quiesceCycles                   3603423163                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu.committedInsts                    53085804                       # Number of Instructions Simulated
+system.cpu.committedOps                      53085804                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              53085804                       # Number of Instructions Simulated
 system.cpu.cpi                               2.190256                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         2.190256                       # CPI: Total CPI of All Threads
@@ -603,51 +602,39 @@ system.cpu.icache.total_refs                  7985769                       # To
 system.cpu.icache.sampled_refs                1005097                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   7.945272                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            23358400000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            509.963959                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.996023                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             7985770                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     509.963959                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996023                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996023                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      7985770                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         7985770                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              7985770                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst       7985770                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total          7985770                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             7985770                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst      7985770                       # number of overall hits
 system.cpu.icache.overall_hits::total         7985770                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1065446                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst      1065446                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total       1065446                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1065446                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst      1065446                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total        1065446                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1065446                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst      1065446                       # number of overall misses
 system.cpu.icache.overall_misses::total       1065446                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    15927822494                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     15927822494                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    15927822494                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         9051216                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15927822494                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15927822494                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15927822494                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15927822494                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15927822494                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15927822494                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9051216                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total      9051216                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          9051216                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst      9051216                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total      9051216                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         9051216                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9051216                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total      9051216                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.117713                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.117713                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.117713                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14949.441355                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14949.441355                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14949.441355                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.117713                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.117713                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.117713                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14949.441355                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14949.441355                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14949.441355                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs      1315496                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs               121                       # number of cycles access was blocked
@@ -656,33 +643,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 10871.867769
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      234                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             60134                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              60134                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             60134                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses         1005312                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses          1005312                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses         1005312                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  12047333996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  12047333996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  12047333996                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.111069                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.111069                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.111069                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11983.676705                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11983.676705                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11983.676705                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks          234                       # number of writebacks
+system.cpu.icache.writebacks::total               234                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60134                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        60134                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        60134                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        60134                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        60134                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        60134                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1005312                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1005312                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1005312                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1005312                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1005312                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1005312                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12047333996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12047333996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12047333996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12047333996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12047333996                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12047333996                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.111069                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.111069                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.111069                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11983.676705                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11983.676705                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11983.676705                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1403406                       # number of replacements
 system.cpu.dcache.tagsinuse                511.996008                       # Cycle average of tags in use
@@ -690,84 +676,69 @@ system.cpu.dcache.total_refs                 12086534                       # To
 system.cpu.dcache.sampled_refs                1403918                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   8.609145                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               19221000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.996008                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999992                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0             7453772                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.996008                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999992                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999992                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7453772                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7453772                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            4220462                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4220462                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        4220462                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::       192050                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       192050                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       192050                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         220033                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       220033                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       220033                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             11674234                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      11674234                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         11674234                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            11674234                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     11674234                       # number of overall hits
 system.cpu.dcache.overall_hits::total        11674234                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1809182                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1809182                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1809182                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          1936475                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1936475                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total      1936475                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        22599                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        22599                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        22599                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::0            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::0            3745657                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      3745657                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        3745657                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           3745657                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      3745657                       # number of overall misses
 system.cpu.dcache.overall_misses::total       3745657                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    38930236000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   57815325976                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency    338636000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency        28500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency     96745561976                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    96745561976                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0         9262954                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  38930236000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  38930236000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  57815325976                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  57815325976                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    338636000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    338636000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data        28500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total        28500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  96745561976                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  96745561976                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  96745561976                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  96745561976                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      9262954                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      9262954                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        6156937                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6156937                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6156937                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       214649                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       214649                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       214649                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       220035                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       220035                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       220035                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         15419891                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     15419891                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     15419891                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        15419891                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15419891                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15419891                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.195314                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.314519                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.105284                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::0     0.000009                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.242911                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.242911                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 21518.142453                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 29855.963013                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14984.556839                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0        14250                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 25828.729640                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 25828.729640                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.195314                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.314519                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.105284                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000009                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.242911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.242911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 21518.142453                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29855.963013                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14984.556839                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        14250                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 25828.729640                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 25828.729640                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs    920169326                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       212000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs            101826                       # number of cycles access was blocked
@@ -776,57 +747,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  9036.683421
 system.cpu.dcache.avg_blocked_cycles::no_targets 23555.555556                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   834955                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            721461                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1637588                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits         5103                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2359049                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2359049                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1087721                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         298887                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17496                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1386608                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1386608                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  24804888500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8509686826                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    206420500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency        22000                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  33314575326                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  33314575326                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    904009500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1234178998                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency   2138188498                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.117427                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.048545                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.081510                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000009                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.089923                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.089923                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22804.458588                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 28471.251095                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11798.153864                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency        11000                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 24025.950612                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 24025.950612                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       834955                       # number of writebacks
+system.cpu.dcache.writebacks::total            834955                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       721461                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       721461                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1637588                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1637588                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         5103                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         5103                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2359049                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2359049                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2359049                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2359049                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1087721                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1087721                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298887                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       298887                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17496                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17496                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1386608                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1386608                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1386608                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1386608                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  24804888500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  24804888500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8509686826                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8509686826                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    206420500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    206420500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total        22000                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  33314575326                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  33314575326                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  33314575326                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  33314575326                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    904009500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    904009500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1234178998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1234178998                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2138188498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   2138188498                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.117427                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.048545                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.081510                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.089923                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.089923                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22804.458588                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 28471.251095                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11798.153864                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        11000                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24025.950612                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24025.950612                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                     6433                       # number of quiesce instructions executed
index 631ad091d4281f344c48e6bb3c19a627226aed30..23b3ee99254c32ad5477f11093917a47ad203b15 100644 (file)
@@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -62,7 +62,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
@@ -173,20 +173,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -481,20 +474,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -629,20 +615,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -937,20 +916,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -1002,20 +974,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -1034,20 +999,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
index 6780ea1b9df111e809dc39b9ebf109018e9eacba..6921c92e47b2d77d4dbde0b804130cecaf4b287a 100755 (executable)
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  3 2012 14:00:40
-gem5 started Feb  3 2012 14:01:00
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:40:16
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2582494330500 because m5_exit instruction encountered
index d8f37781af73f7ce524f087e18e20c48b70cb5c1..6605c6d1b0eb7da8e92ac8eac4a2928eb11a528b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.582494                       # Nu
 sim_ticks                                2582494330500                       # Number of ticks simulated
 final_tick                               2582494330500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  58235                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1883208568                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 413296                       # Number of bytes of host memory used
-host_seconds                                  1371.33                       # Real time elapsed on the host
-sim_insts                                    79859495                       # Number of instructions simulated
+host_inst_rate                                  80373                       # Simulator instruction rate (inst/s)
+host_op_rate                                   103823                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3357432165                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 383300                       # Number of bytes of host memory used
+host_seconds                                   769.19                       # Real time elapsed on the host
+sim_insts                                    61822124                       # Number of instructions simulated
+sim_ops                                      79859495                       # Number of ops (including micro ops) simulated
 system.nvmem.bytes_read                           384                       # Number of bytes read from this memory
 system.nvmem.bytes_inst_read                      384                       # Number of instructions bytes read from this memory
 system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
@@ -34,127 +36,233 @@ system.l2c.total_refs                         1820044                       # To
 system.l2c.sampled_refs                        162190                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         11.221678                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  4997.961622                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                  7175.690427                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 15403.191755                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.076263                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.109492                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.235034                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                     739066                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     627724                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                     184257                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        15356.692298                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker      22.670587                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       1.636552                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3410.170856                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          1587.790766                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker      18.616033                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.itb.walker       3.576285                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2636.430831                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          4539.259596                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.234325                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000346                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker      0.000025                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.052035                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.024228                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker      0.000284                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.itb.walker      0.000055                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.040229                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.069264                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.420789                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker        89183                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker        17213                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             526448                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             212618                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker        73946                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         3915                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             477126                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             150598                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1551047                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   599046                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          599046                       # number of Writeback hits
 system.l2c.Writeback_hits::total               599046                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     992                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                    1000                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data             992                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data            1000                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                1992                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                   175                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                   443                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           175                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           443                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total               618                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                    58603                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    38925                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data            58603                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            38925                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total                97528                       # number of ReadExReq hits
-system.l2c.demand_hits::0                      797669                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      666649                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                      184257                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.dtb.walker         89183                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker         17213                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              526448                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              271221                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker         73946                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          3915                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              477126                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              189523                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1648575                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                     797669                       # number of overall hits
-system.l2c.overall_hits::1                     666649                       # number of overall hits
-system.l2c.overall_hits::2                     184257                       # number of overall hits
+system.l2c.overall_hits::cpu0.dtb.walker        89183                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker        17213                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             526448                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             271221                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker        73946                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         3915                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             477126                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             189523                       # number of overall hits
 system.l2c.overall_hits::total                1648575                       # number of overall hits
-system.l2c.ReadReq_misses::0                    19787                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                    20563                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                      170                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.dtb.walker           70                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker           10                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            10849                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data             8938                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker           78                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker           12                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             7504                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data            13059                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                40520                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  7351                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  3816                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          7351                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          3816                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total             11167                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                 849                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                 448                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          849                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          448                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total            1297                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                  97885                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  50394                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data          97885                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          50394                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             148279                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    117672                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     70957                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                       170                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.dtb.walker           70                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker           10                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             10849                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            106823                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker           78                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker           12                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              7504                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             63453                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                188799                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   117672                       # number of overall misses
-system.l2c.overall_misses::1                    70957                       # number of overall misses
-system.l2c.overall_misses::2                      170                       # number of overall misses
+system.l2c.overall_misses::cpu0.dtb.walker           70                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker           10                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            10849                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           106823                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker           78                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker           12                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             7504                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            63453                       # number of overall misses
 system.l2c.overall_misses::total               188799                       # number of overall misses
-system.l2c.ReadReq_miss_latency            2117109000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           60330000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency          7673500                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7779101999                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             9896210999                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            9896210999                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                 758853                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 648287                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                 184427                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      3650500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       521000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    567333500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    466408000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker      4067500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker       625000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    392575500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    681928000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2117109000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     27539500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     32790500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     60330000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1772000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      5901500                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      7673500                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5139681999                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   2639420000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7779101999                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      3650500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       521000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    567333500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   5606089999                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker      4067500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker       625000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    392575500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   3321348000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9896210999                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      3650500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       521000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    567333500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5606089999                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker      4067500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker       625000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    392575500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   3321348000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9896210999                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker        89253                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker        17223                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         537297                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         221556                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker        74024                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         3927                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         484630                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         163657                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            1591567                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               599046                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       599046                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           599046                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                8343                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                4816                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         8343                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         4816                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total           13159                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0              1024                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               891                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data         1024                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          891                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total          1915                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               156488                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                89319                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       156488                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        89319                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           245807                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                  915341                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  737606                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                  184427                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.dtb.walker        89253                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker        17223                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          537297                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          378044                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker        74024                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         3927                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          484630                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          252976                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             1837374                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                 915341                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 737606                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                 184427                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker        89253                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker        17223                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         537297                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         378044                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker        74024                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         3927                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         484630                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         252976                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            1837374                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.026075                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.031719                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.000922                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.058716                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.881098                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.792359                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.829102                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.502806                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.625511                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.564202                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.128555                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.096199                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.000922                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.225676                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.128555                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.096199                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.000922                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.225676                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   106994.946177                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   102957.204688                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   12453582.352941                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 12663534.503806                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  8207.046660                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 15809.748428                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0  9038.280330                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 17128.348214                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 79471.849609                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 154365.638747                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    84099.964299                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    139467.719873                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    58213005.876471                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 58436573.560642                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   84099.964299                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   139467.719873                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   58213005.876471                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 58436573.560642                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.000784                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.000581                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.020192                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.040342                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001054                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.003056                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.015484                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.079795                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.881098                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.792359                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.829102                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.502806                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.625511                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.564202                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.000784                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.000581                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.020192                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.282568                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001054                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.003056                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.015484                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.250826                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.000784                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.000581                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.020192                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.282568                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001054                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.003056                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.015484                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.250826                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker        52150                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker        52100                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52293.621532                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52182.591184                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52147.435897                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 52083.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52315.498401                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52219.006049                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  3746.361039                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  8592.898323                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  2087.161366                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 13172.991071                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52507.350452                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52375.679644                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker        52100                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52293.621532                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52480.177481                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52147.435897                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker 52083.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52315.498401                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52343.435299                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker        52150                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker        52100                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52293.621532                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52480.177481                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52147.435897                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker 52083.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52315.498401                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52343.435299                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -163,61 +271,178 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          112618                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                       97                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                        97                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                       97                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  40423                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses               11167                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses              1297                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               148279                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  188702                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 188702                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       1619864500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     446963000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency     51939000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5941339999                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        7561204499                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       7561204499                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131964916000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency  32535008680                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 164499924680                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.053269                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.062354                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         0.219182                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.334804                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.338487                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      2.318729                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.266602                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.455668                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.947542                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       1.660106                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.206155                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          0.255830                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          1.023180                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.485165                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.206155                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         0.255830                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         1.023180                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.485165                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40072.842194                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40025.342527                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40045.489591                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40068.654354                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40069.551457                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40069.551457                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              112618                       # number of writebacks
+system.l2c.writebacks::total                   112618                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data            42                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst            10                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data            37                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                97                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data             42                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             10                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data             37                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 97                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data            42                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst            10                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data            37                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                97                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           70                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker           10                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst        10841                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data         8896                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker           78                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker           12                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         7494                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data        13022                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           40423                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         7351                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         3816                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        11167                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          849                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          448                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1297                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        97885                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        50394                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        148279                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           70                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker           10                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        10841                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       106781                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker           78                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker           12                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         7494                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        63416                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           188702                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           70                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker           10                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        10841                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       106781                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker           78                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker           12                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         7494                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        63416                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          188702                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker      2801500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       401000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    434490500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    356315000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker      3121000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       480000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    300775500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    521480000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1619864500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    294259500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    152703500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    446963000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     33985000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     17954000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     51939000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3922908499                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2018431500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5941339999                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker      2801500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       401000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    434490500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4279223499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker      3121000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       480000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    300775500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2539911500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7561204499                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker      2801500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       401000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    434490500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4279223499                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker      3121000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       480000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    300775500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2539911500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7561204499                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst      4981000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 124405850500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      1891000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data   7552193500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131964916000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data    881564880                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data  31653443800                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32535008680                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst      4981000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data 125287415380                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      1891000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data  39205637300                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164499924680                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.000784                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.000581                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.020177                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.040152                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001054                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.003056                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.015463                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.079569                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.881098                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.792359                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.829102                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.502806                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.625511                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.564202                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.000784                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.000581                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.020177                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.282457                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001054                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.003056                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.015463                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.250680                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.000784                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.000581                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.020177                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.282457                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001054                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.003056                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.015463                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.250680                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40100                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40078.452172                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40053.394784                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40135.508407                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40046.075872                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.859883                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40016.640461                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40029.446408                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40075.892857                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40076.707350                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40053.012263                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40100                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40078.452172                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40074.765164                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40135.508407                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40051.587927                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40021.428571                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40100                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40078.452172                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40074.765164                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40012.820513                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40135.508407                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40051.587927                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -471,9 +696,9 @@ system.cpu0.iew.iewDispNonSpecInsts            864933                       # Nu
 system.cpu0.iew.iewIQFullEvents                 62296                       # Number of times the IQ has become full, causing a stall
 system.cpu0.iew.iewLSQFullEvents                 5639                       # Number of times the LSQ has become full, causing a stall
 system.cpu0.iew.memOrderViolationEvents         20483                       # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect        506934                       # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedTakenIncorrect        506933                       # Number of branches that were predicted taken incorrectly
 system.cpu0.iew.predictedNotTakenIncorrect       135852                       # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts              642786                       # Number of branch mispredicts detected at execute
+system.cpu0.iew.branchMispredicts              642785                       # Number of branch mispredicts detected at execute
 system.cpu0.iew.iewExecutedInsts             79552569                       # Number of executed instructions
 system.cpu0.iew.iewExecLoadInsts             42849690                       # Number of load instructions executed
 system.cpu0.iew.iewExecSquashedInsts           723060                       # Number of squashed instructions skipped in execute
@@ -491,7 +716,8 @@ system.cpu0.iew.wb_penalized                        0                       # nu
 system.cpu0.iew.wb_rate                      0.132406                       # insts written-back per cycle
 system.cpu0.iew.wb_fanout                    0.537861                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitCommittedInsts      41923639                       # The number of committed instructions
+system.cpu0.commit.commitCommittedInsts      31935522                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps        41923639                       # The number of committed instructions
 system.cpu0.commit.commitSquashedInsts       10377261                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls        1044424                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts           567428                       # The number of times a branch was mispredicted
@@ -512,7 +738,8 @@ system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::total    108046246                       # Number of insts commited each cycle
-system.cpu0.commit.count                     41923639                       # Number of instructions committed
+system.cpu0.commit.committedInsts            31935522                       # Number of instructions committed
+system.cpu0.commit.committedOps              41923639                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu0.commit.refs                      15936098                       # Number of memory references committed
 system.cpu0.commit.loads                      9243307                       # Number of loads committed
@@ -528,12 +755,13 @@ system.cpu0.rob.rob_writes                  106372981                       # Th
 system.cpu0.timesIdled                        1454145                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu0.idleCycles                      242719810                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu0.quiesceCycles                  4812449027                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts                   41797812                       # Number of Instructions Simulated
-system.cpu0.committedInsts_total             41797812                       # Number of Instructions Simulated
-system.cpu0.cpi                              8.433071                       # CPI: Cycles Per Instruction
-system.cpu0.cpi_total                        8.433071                       # CPI: Total CPI of All Threads
-system.cpu0.ipc                              0.118581                       # IPC: Instructions Per Cycle
-system.cpu0.ipc_total                        0.118581                       # IPC: Total IPC of All Threads
+system.cpu0.committedInsts                   31809695                       # Number of Instructions Simulated
+system.cpu0.committedOps                     41797812                       # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total             31809695                       # Number of Instructions Simulated
+system.cpu0.cpi                             11.081021                       # CPI: Cycles Per Instruction
+system.cpu0.cpi_total                       11.081021                       # CPI: Total CPI of All Threads
+system.cpu0.ipc                              0.090244                       # IPC: Instructions Per Cycle
+system.cpu0.ipc_total                        0.090244                       # IPC: Total IPC of All Threads
 system.cpu0.int_regfile_reads               354190813                       # number of integer regfile reads
 system.cpu0.int_regfile_writes               46128461                       # number of integer regfile writes
 system.cpu0.fp_regfile_reads                     3999                       # number of floating regfile reads
@@ -546,51 +774,39 @@ system.cpu0.icache.total_refs                 5838964                       # To
 system.cpu0.icache.sampled_refs                539299                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                 10.826951                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           16020224000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           511.612990                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.999244                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0            5838964                       # number of ReadReq hits
+system.cpu0.icache.occ_blocks::cpu0.inst   511.612990                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.999244                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.999244                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst      5838964                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total        5838964                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0             5838964                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu0.inst      5838964                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::total         5838964                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0            5838964                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu0.inst      5838964                       # number of overall hits
 system.cpu0.icache.overall_hits::total        5838964                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0           583385                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu0.inst       583385                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total       583385                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0            583385                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu0.inst       583385                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total        583385                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0           583385                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu0.inst       583385                       # number of overall misses
 system.cpu0.icache.overall_misses::total       583385                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency    8740145988                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency     8740145988                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency    8740145988                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0        6422349                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   8740145988                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   8740145988                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   8740145988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   8740145988                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   8740145988                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   8740145988                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst      6422349                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total      6422349                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0         6422349                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu0.inst      6422349                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::total      6422349                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0        6422349                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst      6422349                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total      6422349                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.090837                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.090837                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.090837                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14981.780450                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14981.780450                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14981.780450                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.090837                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.090837                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.090837                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14981.780450                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14981.780450                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14981.780450                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs      1633991                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs              240                       # number of cycles access was blocked
@@ -599,122 +815,108 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs  6808.295833
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                   29665                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits            44065                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits             44065                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits            44065                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses         539320                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses          539320                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses         539320                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency   6552239991                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency   6552239991                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency   6552239991                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency      6685500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency      6685500                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.083976                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0     0.083976                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0     0.083976                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 12149.076598                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 12149.076598                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 12149.076598                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.writebacks::writebacks        29665                       # number of writebacks
+system.cpu0.icache.writebacks::total            29665                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst        44065                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total        44065                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst        44065                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total        44065                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst        44065                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total        44065                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       539320                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       539320                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       539320                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       539320                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       539320                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       539320                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   6552239991                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   6552239991                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   6552239991                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   6552239991                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   6552239991                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   6552239991                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst      6685500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total      6685500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst      6685500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total      6685500                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.083976                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.083976                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.083976                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12149.076598                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12149.076598                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12149.076598                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                372182                       # number of replacements
-system.cpu0.dcache.tagsinuse               487.975562                       # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse               487.992960                       # Cycle average of tags in use
 system.cpu0.dcache.total_refs                12779920                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                372694                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                 34.290651                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              49147000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           487.992960                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -0.017397                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.953111                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1           -0.000034                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            7966835                       # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   487.992960                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.953111                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.953111                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7966835                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        7966835                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           4346487                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      4346487                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total       4346487                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       221211                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       221211                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       221211                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::       199868                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       199868                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       199868                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0            12313322                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data     12313322                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::total        12313322                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0           12313322                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu0.data     12313322                       # number of overall hits
 system.cpu0.dcache.overall_hits::total       12313322                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0           463412                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu0.data       463412                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total       463412                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0         1864293                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data      1864293                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total      1864293                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0        10042                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        10042                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total        10042                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0         7686                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         7686                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total         7686                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0           2327705                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data      2327705                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total       2327705                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0          2327705                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu0.data      2327705                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      2327705                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency    6478995500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency  70420524827                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency    122158000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency     87202500                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency    76899520327                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency   76899520327                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        8430247                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   6478995500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   6478995500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data  70420524827                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total  70420524827                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    122158000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    122158000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     87202500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     87202500                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  76899520327                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  76899520327                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  76899520327                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  76899520327                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8430247                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      8430247                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::      6210780                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      6210780                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      6210780                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       231253                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       231253                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       231253                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       207554                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       207554                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       207554                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        14641027                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     14641027                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total     14641027                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       14641027                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14641027                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14641027                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.054970                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.300171                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.043424                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.037031                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.158985                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.158985                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 13981.069761                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 37773.313973                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 12164.708225                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0 11345.628415                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 33036.626345                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 33036.626345                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.054970                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.300171                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.043424                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.037031                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.158985                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.158985                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13981.069761                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 37773.313973                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12164.708225                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11345.628415                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33036.626345                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33036.626345                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs      6780486                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets      1857500                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs              854                       # number of cycles access was blocked
@@ -723,59 +925,66 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs  7939.679157
 system.cpu0.dcache.avg_blocked_cycles::no_targets 14511.718750                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  327766                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits           223882                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits         1685987                       # number of WriteReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_hits          318                       # number of LoadLockedReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits           1909869                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits          1909869                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses         239530                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses        178306                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses         9724                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses         7685                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses          417836                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses         417836                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency   2943060000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency   6370530485                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency     87975000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency     64109000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency   9313590485                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency   9313590485                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 138958680000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1038766498                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency 139997446498                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.028413                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.028709                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.042049                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.037027                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.028539                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.028539                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12286.811673                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 35728.076930                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  9047.202797                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  8342.094990                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 22290.062333                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 22290.062333                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks       327766                       # number of writebacks
+system.cpu0.dcache.writebacks::total           327766                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data       223882                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total       223882                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data      1685987                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total      1685987                       # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data          318                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total          318                       # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data      1909869                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total      1909869                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data      1909869                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total      1909869                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       239530                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       239530                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       178306                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       178306                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9724                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9724                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         7685                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         7685                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       417836                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       417836                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       417836                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       417836                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2943060000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2943060000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   6370530485                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   6370530485                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     87975000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     87975000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     64109000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     64109000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   9313590485                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   9313590485                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   9313590485                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   9313590485                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 138958680000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 138958680000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1038766498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1038766498                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 139997446498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 139997446498                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028413                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.028709                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.042049                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.037027                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028539                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028539                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12286.811673                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35728.076930                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  9047.202797                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  8342.094990                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22290.062333                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22290.062333                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
@@ -1043,7 +1252,8 @@ system.cpu1.iew.wb_penalized                        0                       # nu
 system.cpu1.iew.wb_rate                      0.640894                       # insts written-back per cycle
 system.cpu1.iew.wb_fanout                    0.545985                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitCommittedInsts      38086237                       # The number of committed instructions
+system.cpu1.commit.commitCommittedInsts      30036983                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps        38086237                       # The number of committed instructions
 system.cpu1.commit.commitSquashedInsts       18573771                       # The number of squashed insts skipped by commit
 system.cpu1.commit.commitNonSpecStalls         519501                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu1.commit.branchMispredicts           450480                       # The number of times a branch was mispredicted
@@ -1064,7 +1274,8 @@ system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::total     47701192                       # Number of insts commited each cycle
-system.cpu1.commit.count                     38086237                       # Number of instructions committed
+system.cpu1.commit.committedInsts            30036983                       # Number of instructions committed
+system.cpu1.commit.committedOps              38086237                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu1.commit.refs                      12651383                       # Number of memory references committed
 system.cpu1.commit.loads                      7112761                       # Number of loads committed
@@ -1080,12 +1291,13 @@ system.cpu1.rob.rob_writes                  116493771                       # Th
 system.cpu1.timesIdled                         450197                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu1.idleCycles                       18365285                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu1.quiesceCycles                  5095139417                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts                   38061683                       # Number of Instructions Simulated
-system.cpu1.committedInsts_total             38061683                       # Number of Instructions Simulated
-system.cpu1.cpi                              1.814944                       # CPI: Cycles Per Instruction
-system.cpu1.cpi_total                        1.814944                       # CPI: Total CPI of All Threads
-system.cpu1.ipc                              0.550981                       # IPC: Instructions Per Cycle
-system.cpu1.ipc_total                        0.550981                       # IPC: Total IPC of All Threads
+system.cpu1.committedInsts                   30012429                       # Number of Instructions Simulated
+system.cpu1.committedOps                     38061683                       # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total             30012429                       # Number of Instructions Simulated
+system.cpu1.cpi                              2.301707                       # CPI: Cycles Per Instruction
+system.cpu1.cpi_total                        2.301707                       # CPI: Total CPI of All Threads
+system.cpu1.ipc                              0.434460                       # IPC: Instructions Per Cycle
+system.cpu1.ipc_total                        0.434460                       # IPC: Total IPC of All Threads
 system.cpu1.int_regfile_reads               222861231                       # number of integer regfile reads
 system.cpu1.int_regfile_writes               47167724                       # number of integer regfile writes
 system.cpu1.fp_regfile_reads                     4217                       # number of floating regfile reads
@@ -1098,51 +1310,39 @@ system.cpu1.icache.total_refs                 7684975                       # To
 system.cpu1.icache.sampled_refs                486098                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                 15.809518                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle           74234723000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           498.788681                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.974197                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0            7684975                       # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst   498.788681                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.974197                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.974197                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      7684975                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        7684975                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0             7684975                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::cpu1.inst      7684975                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::total         7684975                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0            7684975                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::cpu1.inst      7684975                       # number of overall hits
 system.cpu1.icache.overall_hits::total        7684975                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0           527035                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::cpu1.inst       527035                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total       527035                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0            527035                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst       527035                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total        527035                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0           527035                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst       527035                       # number of overall misses
 system.cpu1.icache.overall_misses::total       527035                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency    7752735997                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency     7752735997                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency    7752735997                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0        8212010                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7752735997                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7752735997                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7752735997                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7752735997                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7752735997                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7752735997                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      8212010                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total      8212010                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0         8212010                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::cpu1.inst      8212010                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::total      8212010                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0        8212010                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      8212010                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      8212010                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.064179                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.064179                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.064179                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14710.097047                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14710.097047                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14710.097047                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.064179                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.064179                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.064179                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14710.097047                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14710.097047                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14710.097047                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs      1321997                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs              170                       # number of cycles access was blocked
@@ -1151,35 +1351,38 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs  7776.452941
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                   18538                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits            40914                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits             40914                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits            40914                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses         486121                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses          486121                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses         486121                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   5799471497                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency   5799471497                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency   5799471497                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency      2517500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency      2517500                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.059196                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0     0.059196                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0     0.059196                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11930.098673                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11930.098673                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11930.098673                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks        18538                       # number of writebacks
+system.cpu1.icache.writebacks::total            18538                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst        40914                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total        40914                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst        40914                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total        40914                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst        40914                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total        40914                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       486121                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       486121                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       486121                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       486121                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       486121                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       486121                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5799471497                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5799471497                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5799471497                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5799471497                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5799471497                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5799471497                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      2517500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      2517500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      2517500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      2517500                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.059196                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.059196                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.059196                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11930.098673                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11930.098673                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11930.098673                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                272200                       # number of replacements
 system.cpu1.dcache.tagsinuse               447.953212                       # Cycle average of tags in use
@@ -1187,84 +1390,69 @@ system.cpu1.dcache.total_refs                10416163                       # To
 system.cpu1.dcache.sampled_refs                272587                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                 38.212252                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle           66688833000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           447.953212                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.874909                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            7085363                       # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data   447.953212                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.874909                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.874909                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      7085363                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        7085363                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0           3139669                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      3139669                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total       3139669                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0        75360                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        75360                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        75360                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::        72622                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        72622                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        72622                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0            10225032                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data     10225032                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total        10225032                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0           10225032                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data     10225032                       # number of overall hits
 system.cpu1.dcache.overall_hits::total       10225032                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0           323287                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data       323287                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total       323287                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0         1273508                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data      1273508                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total      1273508                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0        12669                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        12669                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total        12669                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0        11046                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data        11046                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total        11046                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0           1596795                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data      1596795                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total       1596795                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0          1596795                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data      1596795                       # number of overall misses
 system.cpu1.dcache.overall_misses::total      1596795                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency    5044696500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency  46343696337                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency    148164500                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency     87512500                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency    51388392837                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency   51388392837                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        7408650                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   5044696500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   5044696500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data  46343696337                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total  46343696337                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    148164500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    148164500                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     87512500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     87512500                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data  51388392837                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total  51388392837                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data  51388392837                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total  51388392837                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      7408650                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      7408650                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::      4413177                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      4413177                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total      4413177                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0        88029                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        88029                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        88029                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0        83668                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        83668                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        83668                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0        11821827                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data     11821827                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total     11821827                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0       11821827                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     11821827                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total     11821827                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.043636                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.288569                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.143918                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.132022                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.135072                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.135072                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 15604.390217                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 36390.581243                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11695.043018                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0  7922.551150                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 32182.210514                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 32182.210514                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.043636                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.288569                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.143918                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.132022                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.135072                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.135072                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15604.390217                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36390.581243                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11695.043018                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  7922.551150                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 32182.210514                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 32182.210514                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs     13033547                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets      5494000                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs             3077                       # number of cycles access was blocked
@@ -1273,57 +1461,63 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs  4235.796880
 system.cpu1.dcache.avg_blocked_cycles::no_targets 32898.203593                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                  223077                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits           133946                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits         1157260                       # number of WriteReq MSHR hits
-system.cpu1.dcache.LoadLockedReq_mshr_hits         1008                       # number of LoadLockedReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits           1291206                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits          1291206                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses         189341                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses        116248                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses        11661                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses        11046                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses          305589                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses         305589                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency   2489937000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency   3452864547                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     99179500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency     54297000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency   5942801547                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency   5942801547                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency   8455613500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency  41497603581                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency  49953217081                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.025557                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.026341                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.132468                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.132022                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.025850                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.025850                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13150.543200                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 29702.571631                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8505.231112                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  4915.535035                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 19447.040132                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 19447.040132                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks       223077                       # number of writebacks
+system.cpu1.dcache.writebacks::total           223077                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data       133946                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total       133946                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data      1157260                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total      1157260                       # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data         1008                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total         1008                       # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data      1291206                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total      1291206                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data      1291206                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total      1291206                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       189341                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       189341                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       116248                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       116248                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11661                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11661                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data        11046                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total        11046                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       305589                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       305589                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       305589                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       305589                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2489937000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2489937000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3452864547                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3452864547                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     99179500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     99179500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     54297000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     54297000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5942801547                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   5942801547                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5942801547                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5942801547                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data   8455613500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total   8455613500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data  41497603581                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total  41497603581                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data  49953217081                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total  49953217081                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.025557                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.026341                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.132468                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.132022                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.025850                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.025850                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13150.543200                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29702.571631                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8505.231112                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  4915.535035                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19447.040132                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19447.040132                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -1331,38 +1525,6 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -1371,28 +1533,12 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                           0                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1308174844926                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1308174844926                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1308174844926                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1308174844926                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1308174844926                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1308174844926                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   55723                       # number of quiesce instructions executed
index f906b4862cbd1f1f956fa96623f7602766a8fbfd..2ad88f280222f3b270a5a2952632910d24560d80 100644 (file)
@@ -9,13 +9,13 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -62,7 +62,7 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu]
@@ -173,20 +173,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -481,20 +474,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -546,20 +532,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -578,20 +557,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
index 46d2cdea6135c741a396ca824353b2f0a9032916..1c96dc7677e30cfcfaddc603c97dddba0375d271 100755 (executable)
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simout
-Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  3 2012 14:00:40
-gem5 started Feb  3 2012 14:01:01
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:39:00
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/fast/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2503580880500 because m5_exit instruction encountered
index b494abcbb1876b9578225743e1bdfc73f7ea60de..1df010cb5d92d85c98f340dbf4175f7e45d0f078 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.503581                       # Nu
 sim_ticks                                2503580880500                       # Number of ticks simulated
 final_tick                               2503580880500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  56444                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1840259079                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 413160                       # Number of bytes of host memory used
-host_seconds                                  1360.45                       # Real time elapsed on the host
-sim_insts                                    76789886                       # Number of instructions simulated
+host_inst_rate                                  80550                       # Simulator instruction rate (inst/s)
+host_op_rate                                   104045                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3392180683                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 382816                       # Number of bytes of host memory used
+host_seconds                                   738.04                       # Real time elapsed on the host
+sim_insts                                    59449329                       # Number of instructions simulated
+sim_ops                                      76789886                       # Number of ops (including micro ops) simulated
 system.nvmem.bytes_read                            64                       # Number of bytes read from this memory
 system.nvmem.bytes_inst_read                       64                       # Number of instructions bytes read from this memory
 system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
@@ -34,91 +36,132 @@ system.l2c.total_refs                         1795685                       # To
 system.l2c.sampled_refs                        150314                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         11.946226                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 11478.014025                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 14356.915365                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.175141                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.219069                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1349535                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     153277                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        14304.535648                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       48.618373                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        3.761343                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           6047.704729                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           5430.309296                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.218270                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000742                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000057                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.092281                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.082860                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.394210                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        143695                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          9582                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              973305                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              376230                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1502812                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   630148                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          630148                       # number of Writeback hits
 system.l2c.Writeback_hits::total               630148                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      47                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data               47                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  47                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                    17                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu.data             17                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                17                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   105970                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            105970                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               105970                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1455505                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      153277                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker         143695                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           9582                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               973305                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               482200                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1608782                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1455505                       # number of overall hits
-system.l2c.overall_hits::1                     153277                       # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker        143695                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          9582                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              973305                       # number of overall hits
+system.l2c.overall_hits::cpu.data              482200                       # number of overall hits
 system.l2c.overall_hits::total                1608782                       # number of overall hits
-system.l2c.ReadReq_misses::0                    36088                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                      150                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker          134                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           16                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             17088                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             19000                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                36238                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  3252                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data           3252                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              3252                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                   4                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu.data            4                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total               4                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                 140397                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          140397                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             140397                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    176485                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                       150                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker          134                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              17088                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             159397                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                176635                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   176485                       # number of overall misses
-system.l2c.overall_misses::1                      150                       # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker          134                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           16                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             17088                       # number of overall misses
+system.l2c.overall_misses::cpu.data            159397                       # number of overall misses
 system.l2c.overall_misses::total               176635                       # number of overall misses
-system.l2c.ReadReq_miss_latency            1895542500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency            1059500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7383005500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             9278548000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            9278548000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                1385623                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 153427                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      7004000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       843500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    894670500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    993024500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1895542500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data      1059500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      1059500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7383005500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7383005500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      7004000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       843500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    894670500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8376030000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9278548000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      7004000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       843500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    894670500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8376030000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9278548000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       143829                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         9598                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          990393                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          395230                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            1539050                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               630148                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       630148                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           630148                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                3299                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         3299                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            3299                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0                21                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu.data           21                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total            21                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               246367                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        246367                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           246367                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 1631990                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  153427                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker       143829                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         9598                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           990393                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           641597                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             1785417                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                1631990                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 153427                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       143829                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         9598                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          990393                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          641597                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            1785417                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.026045                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000978                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.027022                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.985753                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.190476                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.569869                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.108141                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000978                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.109119                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.108141                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000978                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.109119                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52525.562514                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1       12636950                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 12689475.562514                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0   325.799508                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52586.632905                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52574.145111                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    61856986.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 61909560.811778                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52574.145111                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   61856986.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 61909560.811778                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000932                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001667                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.017254                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.048073                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.985753                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu.data     0.190476                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.569869                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000932                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001667                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.017254                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.248438                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000932                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001667                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.017254                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.248438                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52268.656716                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker 52718.750000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52356.653792                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52264.447368                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   325.799508                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52586.632905                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52268.656716                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker 52718.750000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52356.653792                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52548.228637                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52268.656716                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker 52718.750000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52356.653792                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52548.228637                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -127,55 +170,102 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          102643                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                       94                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                        94                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                       94                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  36144                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                3252                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses                 4                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               140397                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  176541                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 176541                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       1450468000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     131324500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency       160000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5639183500                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        7089651500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       7089651500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131770082500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency  32364127897                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 164134210397                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.026085                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.235578                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.261663                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.985753                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     0.190476                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.569869                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.108175                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.150651                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.258827                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.108175                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.150651                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.258827                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40130.256751                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40382.687577                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40165.982891                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40158.668525                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40158.668525                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              102643                       # number of writebacks
+system.l2c.writebacks::total                   102643                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst             14                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data             80                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                94                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst              14                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data              80                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 94                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst             14                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data             80                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                94                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker          134                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker           16                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        17074                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        18920                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           36144                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         3252                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         3252                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu.data            4                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total            4                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       140397                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140397                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker          134                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker           16                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         17074                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        159317                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           176541                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker          134                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker           16                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        17074                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       159317                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          176541                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      5376000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       651000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    685402500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    759038500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1450468000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    131324500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    131324500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu.data       160000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total       160000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5639183500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5639183500                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      5376000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       651000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    685402500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6398222000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7089651500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      5376000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       651000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    685402500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6398222000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7089651500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst      4738500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131765344000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131770082500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  32364127897                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  32364127897                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst      4738500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 164129471897                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 164134210397                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000932                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001667                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.017240                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.047871                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.985753                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu.data     0.190476                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.569869                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000932                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001667                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.017240                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.248313                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000932                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001667                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.017240                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.248313                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40687.500000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.053766                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40118.313953                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40382.687577                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40165.982891                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40687.500000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.053766                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40160.321874                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40119.402985                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40687.500000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.053766                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40160.321874                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -429,9 +519,9 @@ system.cpu.iew.iewDispNonSpecInsts            1227782                       # Nu
 system.cpu.iew.iewIQFullEvents                  84296                       # Number of times the IQ has become full, causing a stall
 system.cpu.iew.iewLSQFullEvents                  7341                       # Number of times the LSQ has become full, causing a stall
 system.cpu.iew.memOrderViolationEvents          32675                       # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect         852505                       # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedTakenIncorrect         852504                       # Number of branches that were predicted taken incorrectly
 system.cpu.iew.predictedNotTakenIncorrect       256815                       # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts              1109320                       # Number of branch mispredicts detected at execute
+system.cpu.iew.branchMispredicts              1109319                       # Number of branch mispredicts detected at execute
 system.cpu.iew.iewExecutedInsts             123469909                       # Number of executed instructions
 system.cpu.iew.iewExecLoadInsts              52917262                       # Number of load instructions executed
 system.cpu.iew.iewExecSquashedInsts           3434775                       # Number of squashed instructions skipped in execute
@@ -449,7 +539,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       0.209988                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.543006                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       76940267                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts       59599710                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         76940267                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        27835988                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         1499707                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            978113                       # The number of times a branch was mispredicted
@@ -470,7 +561,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    151014616                       # Number of insts commited each cycle
-system.cpu.commit.count                      76940267                       # Number of instructions committed
+system.cpu.commit.committedInsts             59599710                       # Number of instructions committed
+system.cpu.commit.committedOps               76940267                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       27459843                       # Number of memory references committed
 system.cpu.commit.loads                      15680763                       # Number of loads committed
@@ -486,12 +578,13 @@ system.cpu.rob.rob_writes                   214319630                       # Th
 system.cpu.timesIdled                         1877181                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                       260374175                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.quiesceCycles                   4591130340                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                    76789886                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              76789886                       # Number of Instructions Simulated
-system.cpu.cpi                               5.416643                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         5.416643                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.184616                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.184616                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                    59449329                       # Number of Instructions Simulated
+system.cpu.committedOps                      76789886                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              59449329                       # Number of Instructions Simulated
+system.cpu.cpi                               6.996604                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         6.996604                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.142926                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.142926                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                559798057                       # number of integer regfile reads
 system.cpu.int_regfile_writes                89741069                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                      8257                       # number of floating regfile reads
@@ -504,51 +597,39 @@ system.cpu.icache.total_refs                 13035657                       # To
 system.cpu.icache.sampled_refs                 991689                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  13.144904                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle             6445921000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            511.615293                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.999249                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0            13035657                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     511.615293                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999249                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999249                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     13035657                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        13035657                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0             13035657                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst      13035657                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total         13035657                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0            13035657                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst     13035657                       # number of overall hits
 system.cpu.icache.overall_hits::total        13035657                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1079227                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst      1079227                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total       1079227                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1079227                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst      1079227                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total        1079227                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1079227                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst      1079227                       # number of overall misses
 system.cpu.icache.overall_misses::total       1079227                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    15906225491                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     15906225491                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    15906225491                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0        14114884                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  15906225491                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  15906225491                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  15906225491                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  15906225491                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  15906225491                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  15906225491                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14114884                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     14114884                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0         14114884                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst     14114884                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total     14114884                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0        14114884                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14114884                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     14114884                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.076460                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.076460                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.076460                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14738.535536                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14738.535536                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14738.535536                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.076460                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.076460                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.076460                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14738.535536                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14738.535536                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14738.535536                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs      2390996                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs               341                       # number of cycles access was blocked
@@ -557,35 +638,38 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs  7011.718475
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                    57255                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             87505                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              87505                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             87505                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          991722                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           991722                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          991722                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  11850340996                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  11850340996                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  11850340996                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency      6359500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency      6359500                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.070261                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.070261                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.070261                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11949.256945                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11949.256945                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11949.256945                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks        57255                       # number of writebacks
+system.cpu.icache.writebacks::total             57255                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        87505                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        87505                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        87505                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        87505                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        87505                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        87505                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       991722                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       991722                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       991722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       991722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       991722                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       991722                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  11850340996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  11850340996                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  11850340996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  11850340996                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  11850340996                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  11850340996                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst      6359500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total      6359500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst      6359500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total      6359500                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.070261                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.070261                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.070261                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11949.256945                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11949.256945                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11949.256945                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 643728                       # number of replacements
 system.cpu.dcache.tagsinuse                511.991681                       # Cycle average of tags in use
@@ -593,84 +677,69 @@ system.cpu.dcache.total_refs                 22270301                       # To
 system.cpu.dcache.sampled_refs                 644240                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  34.568330                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               48663000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.991681                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999984                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            14416609                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.991681                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999984                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999984                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     14416609                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        14416609                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            7264899                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      7264899                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        7264899                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::       299899                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       299899                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       299899                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         285488                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       285488                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       285488                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             21681508                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      21681508                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         21681508                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            21681508                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     21681508                       # number of overall hits
 system.cpu.dcache.overall_hits::total        21681508                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0            722544                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data       722544                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        722544                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0          2966373                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2966373                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total      2966373                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        13502                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        13502                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        13502                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::0           21                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data           21                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total           21                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::0            3688917                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      3688917                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        3688917                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           3688917                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      3688917                       # number of overall misses
 system.cpu.dcache.overall_misses::total       3688917                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    10864923000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency  110367485740                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency    219139000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency       467500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency    121232408740                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   121232408740                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        15139153                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  10864923000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  10864923000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110367485740                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110367485740                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    219139000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    219139000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       467500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::total       467500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 121232408740                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 121232408740                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 121232408740                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 121232408740                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     15139153                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     15139153                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0       10231272                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10231272                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     10231272                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       313401                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       313401                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       313401                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       285509                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       285509                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       285509                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         25370425                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     25370425                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     25370425                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        25370425                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     25370425                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     25370425                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.047727                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.289932                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.043082                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::0     0.000074                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.145402                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.145402                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15037.039959                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 37206.206280                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16230.114057                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::0 22261.904762                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 32863.956749                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 32863.956749                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047727                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289932                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.043082                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000074                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.145402                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.145402                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15037.039959                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37206.206280                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16230.114057                       # average LoadLockedReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 22261.904762                       # average StoreCondReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32863.956749                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32863.956749                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     16658435                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      7526500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              2975                       # number of cycles access was blocked
@@ -679,57 +748,63 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  5599.473950
 system.cpu.dcache.avg_blocked_cycles::no_targets 27171.480144                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   572893                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            336628                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          2716799                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits         1453                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            3053427                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           3053427                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          385916                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         249574                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses        12049                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses           21                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           635490                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          635490                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   5245615500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8926036935                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    161663500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency       398500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  14171652435                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  14171652435                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 147159299000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency  42287348315                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 189446647315                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.025491                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.024393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.038446                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::0     0.000074                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.025048                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.025048                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13592.635444                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35765.091456                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13417.171550                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency 18976.190476                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 22300.354742                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 22300.354742                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       572893                       # number of writebacks
+system.cpu.dcache.writebacks::total            572893                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       336628                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       336628                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      2716799                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      2716799                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data         1453                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total         1453                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      3053427                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      3053427                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      3053427                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      3053427                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       385916                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       385916                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249574                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249574                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        12049                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        12049                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data           21                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total           21                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       635490                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       635490                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       635490                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       635490                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5245615500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5245615500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8926036935                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8926036935                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    161663500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    161663500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       398500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       398500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  14171652435                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  14171652435                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  14171652435                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  14171652435                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 147159299000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 147159299000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  42287348315                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  42287348315                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 189446647315                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 189446647315                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.025491                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.038446                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000074                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.025048                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.025048                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13592.635444                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35765.091456                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13417.171550                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 18976.190476                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 22300.354742                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22300.354742                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -737,38 +812,6 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -777,28 +820,12 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                           0                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1307927966543                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1307927966543                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1307927966543                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1307927966543                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1307927966543                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1307927966543                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    87993                       # number of quiesce instructions executed
index ea30d17bbbf8972eeff6175d4c2bf43073b203a7..a45397a7de8a72ad3d37a018b0a558f03b25197b 100644 (file)
@@ -8,14 +8,14 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
 e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 memories=system.physmem
@@ -50,6 +50,17 @@ oem_id=
 oem_revision=0
 oem_table_id=
 
+[system.apicbridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
 [system.bridge]
 type=Bridge
 delay=50000
@@ -169,20 +180,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -212,20 +216,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -507,20 +504,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -559,20 +549,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -946,17 +929,6 @@ subtractive_decode=true
 type=IntrControl
 sys=system
 
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
 [system.iobus]
 type=Bus
 block_size=64
@@ -966,7 +938,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -979,20 +951,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -1011,20 +976,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -1042,7 +1000,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -1303,7 +1261,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1323,7 +1281,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
index 647f02ab1fbd7a1d69f0fbb9e2e3b0b06c0e7f20..7b718bc11509b72026d9ad8a71beac5339aa95e5 100755 (executable)
@@ -1,15 +1,12 @@
-Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  3 2012 12:36:19
-gem5 started Feb  3 2012 12:37:07
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:31:16
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5163317092500 because m5_exit instruction encountered
index 9bce828a3063a3b67a099489e32ae4f7bd763265..477cac0b545bb4864cf6b18f43b3503b46c3bfef 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  5.163317                       # Nu
 sim_ticks                                5163317092500                       # Number of ticks simulated
 final_tick                               5163317092500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 210982                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1295931182                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 391560                       # Number of bytes of host memory used
-host_seconds                                  3984.25                       # Real time elapsed on the host
-sim_insts                                   840604148                       # Number of instructions simulated
+host_inst_rate                                 184798                       # Simulator instruction rate (inst/s)
+host_op_rate                                   364169                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2236864416                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 361200                       # Number of bytes of host memory used
+host_seconds                                  2308.28                       # Real time elapsed on the host
+sim_insts                                   426565585                       # Number of instructions simulated
+sim_ops                                     840604148                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    15861056                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                1233408                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 12134976                       # Number of bytes written to this memory
@@ -25,84 +27,125 @@ system.l2c.total_refs                         3777661                       # To
 system.l2c.sampled_refs                        200841                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         18.809212                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 11087.594784                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 26777.855453                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.169183                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.408598                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2326799                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     141457                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        26765.864627                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker       11.948564                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.042262                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           2364.419048                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           8723.175736                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.408415                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000182                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000001                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.036078                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.133105                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.577781                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker        134155                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          7302                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst             1001370                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1325429                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                2468256                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1603120                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks         1603120                       # number of Writeback hits
 system.l2c.Writeback_hits::total              1603120                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     322                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data              322                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 322                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   150704                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            150704                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               150704                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2477503                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      141457                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker         134155                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           7302                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst              1001370                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1476133                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 2618960                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2477503                       # number of overall hits
-system.l2c.overall_hits::1                     141457                       # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker        134155                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          7302                       # number of overall hits
+system.l2c.overall_hits::cpu.inst             1001370                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1476133                       # number of overall hits
 system.l2c.overall_hits::total                2618960                       # number of overall hits
-system.l2c.ReadReq_misses::0                    64223                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       92                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker           82                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           10                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             19273                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             44950                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                64315                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  5079                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data           5079                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              5079                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 141389                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          141389                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             141389                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    205612                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        92                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker           82                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           10                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              19273                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             186339                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                205704                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   205612                       # number of overall misses
-system.l2c.overall_misses::1                       92                       # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker           82                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           10                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             19273                       # number of overall misses
+system.l2c.overall_misses::cpu.data            186339                       # number of overall misses
 system.l2c.overall_misses::total               205704                       # number of overall misses
-system.l2c.ReadReq_miss_latency            3374675500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           37477500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7363267000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            10737942500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           10737942500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2391022                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 141549                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      4278000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       521000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst   1007154000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   2362722500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     3374675500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     37477500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     37477500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7363267000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7363267000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      4278000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       521000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst   1007154000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   9725989500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     10737942500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      4278000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       521000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst   1007154000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   9725989500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    10737942500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker       134237                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         7312                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst         1020643                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1370379                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2532571                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1603120                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1603120                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total          1603120                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                5401                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         5401                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            5401                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               292093                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        292093                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           292093                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2683115                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  141549                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker       134237                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         7312                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst          1020643                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1662472                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2824664                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2683115                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 141549                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker       134237                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         7312                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst         1020643                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1662472                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2824664                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.026860                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.000650                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.027510                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.940381                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.484055                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.076632                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.000650                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.077282                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.076632                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.000650                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.077282                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52546.213973                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   36681255.434783                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 36733801.648756                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  7378.913172                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52078.075381                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52224.298679                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    116716766.304348                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 116768990.603027                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52224.298679                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   116716766.304348                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 116768990.603027                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.000611                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.001368                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.018883                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.032801                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.940381                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.484055                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.000611                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.001368                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.018883                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.112085                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.000611                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.001368                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.018883                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.112085                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52170.731707                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52100                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52257.251077                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52563.348165                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data  7378.913172                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52078.075381                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52170.731707                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker        52100                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52257.251077                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52195.136284                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52170.731707                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker        52100                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52257.251077                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52195.136284                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -111,49 +154,92 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          142942                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                        2                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                         2                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        2                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  64313                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                5079                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               141389                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  205702                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 205702                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       2588909500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     203533000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5656832000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        8245741500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       8245741500                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  59975483500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1228994000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  61204477500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.026898                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.454351                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     0.481249                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.940381                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.484055                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.076665                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.453221                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      1.529887                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.076665                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.453221                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     1.529887                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40254.839613                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40073.439653                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40008.996457                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40085.859642                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40085.859642                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              142942                       # number of writebacks
+system.l2c.writebacks::total                   142942                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu.inst              1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu.data              1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 2                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu.inst               1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu.data               1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  2                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu.inst              1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu.data              1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 2                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           82                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker           10                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        19272                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        44949                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           64313                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         5079                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         5079                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       141389                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        141389                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           82                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker           10                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         19272                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        186338                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           205702                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           82                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker           10                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        19272                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       186338                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          205702                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker      3286000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       400000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    771698500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1813525000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2588909500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    203533000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    203533000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5656832000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5656832000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker      3286000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       400000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    771698500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   7470357000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   8245741500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker      3286000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       400000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    771698500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   7470357000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   8245741500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  59975483500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  59975483500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1228994000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1228994000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  61204477500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  61204477500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.000611                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.001368                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.018882                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.032800                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.940381                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.484055                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.000611                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.001368                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.018882                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.112085                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.000611                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.001368                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.018882                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.112085                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40042.470942                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40346.281341                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40073.439653                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.996457                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40042.470942                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40090.357308                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40073.170732                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40042.470942                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40090.357308                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47580                       # number of replacements
 system.iocache.tagsinuse                     0.183883                       # Cycle average of tags in use
@@ -161,58 +247,41 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     47596                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              4996389534000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.183883                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.011493                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  915                       # number of ReadReq misses
+system.iocache.occ_blocks::pc.south_bridge.ide     0.183883                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.011493                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.011493                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          915                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              915                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
+system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47635                       # number of demand (read+write) misses
+system.iocache.demand_misses::pc.south_bridge.ide        47635                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             47635                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47635                       # number of overall misses
+system.iocache.overall_misses::pc.south_bridge.ide        47635                       # number of overall misses
 system.iocache.overall_misses::total            47635                       # number of overall misses
-system.iocache.ReadReq_miss_latency         114575932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       6365614160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         6480190092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        6480190092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                915                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    114575932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    114575932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6365614160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   6365614160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   6480190092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   6480190092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   6480190092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   6480190092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          915                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            915                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47635                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47635                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           47635                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47635                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47635                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47635                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 125219.597814                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136250.303082                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136038.419062                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136038.419062                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 125219.597814                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136250.303082                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136038.419062                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136038.419062                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      68485452                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                11259                       # number of cycles access was blocked
@@ -221,38 +290,32 @@ system.iocache.avg_blocked_cycles::no_mshrs  6082.729550                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46667                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                915                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               47635                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              47635                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     66972982                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3935855798                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    4002828780                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   4002828780                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 73194.515847                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84243.488827                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84031.253910                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84031.253910                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          915                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          915                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47635                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47635                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47635                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47635                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     66972982                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     66972982                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3935855798                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3935855798                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4002828780                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4002828780                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4002828780                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4002828780                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 73194.515847                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84243.488827                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84031.253910                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -487,7 +550,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.850453                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.573064                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      840604148                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      426565585                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        840604148                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        30510484                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         1519690                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           1250933                       # The number of times a branch was mispredicted
@@ -508,7 +572,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    302314482                       # Number of insts commited each cycle
-system.cpu.commit.count                     840604148                       # Number of instructions committed
+system.cpu.commit.committedInsts            426565585                       # Number of instructions committed
+system.cpu.commit.committedOps              840604148                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       23747567                       # Number of memory references committed
 system.cpu.commit.loads                      15324009                       # Number of loads committed
@@ -524,12 +589,13 @@ system.cpu.rob.rob_writes                  1746826364                       # Th
 system.cpu.timesIdled                         2858532                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                       155577248                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.quiesceCycles                   9864170951                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts                   840604148                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             840604148                       # Number of Instructions Simulated
-system.cpu.cpi                               0.550153                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.550153                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.817677                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.817677                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   426565585                       # Number of Instructions Simulated
+system.cpu.committedOps                     840604148                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             426565585                       # Number of Instructions Simulated
+system.cpu.cpi                               1.084149                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.084149                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.922382                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.922382                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               1406313694                       # number of integer regfile reads
 system.cpu.int_regfile_writes               857070459                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        62                       # number of floating regfile reads
@@ -541,51 +607,39 @@ system.cpu.icache.total_refs                  8587640                       # To
 system.cpu.icache.sampled_refs                1020665                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   8.413769                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            56648796000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            509.928344                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.995954                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0             8587640                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     509.928344                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.995954                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.995954                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      8587640                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total         8587640                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0              8587640                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst       8587640                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total          8587640                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0             8587640                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst      8587640                       # number of overall hits
 system.cpu.icache.overall_hits::total         8587640                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0           1084449                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst      1084449                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total       1084449                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0            1084449                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst      1084449                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total        1084449                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0           1084449                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst      1084449                       # number of overall misses
 system.cpu.icache.overall_misses::total       1084449                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    16282601991                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     16282601991                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    16282601991                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0         9672089                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  16282601991                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  16282601991                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  16282601991                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  16282601991                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  16282601991                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  16282601991                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9672089                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total      9672089                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0          9672089                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst      9672089                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total      9672089                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0         9672089                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9672089                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total      9672089                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.112121                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.112121                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.112121                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 15014.631385                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 15014.631385                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 15014.631385                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.112121                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.112121                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.112121                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15014.631385                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15014.631385                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15014.631385                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs      2694492                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs               263                       # number of cycles access was blocked
@@ -594,33 +648,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 10245.216730
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                     1551                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             60108                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              60108                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             60108                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses         1024341                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses          1024341                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses         1024341                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  12392610492                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  12392610492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  12392610492                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.105907                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.105907                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.105907                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12098.129912                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12098.129912                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12098.129912                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks         1551                       # number of writebacks
+system.cpu.icache.writebacks::total              1551                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        60108                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        60108                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        60108                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        60108                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        60108                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        60108                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst      1024341                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total      1024341                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst      1024341                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total      1024341                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst      1024341                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total      1024341                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  12392610492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  12392610492                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  12392610492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  12392610492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  12392610492                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  12392610492                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.105907                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.105907                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.105907                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12098.129912                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12098.129912                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12098.129912                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         8553                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        6.010935                       # Cycle average of tags in use
@@ -628,55 +681,43 @@ system.cpu.itb_walker_cache.total_refs          26637                       # To
 system.cpu.itb_walker_cache.sampled_refs         8564                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.avg_refs         3.110346                       # Average number of references to valid blocks.
 system.cpu.itb_walker_cache.warmup_cycle 5140402124000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     6.010935                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.375683                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1        26742                       # number of ReadReq hits
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     6.010935                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.375683                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.375683                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker        26742                       # number of ReadReq hits
 system.cpu.itb_walker_cache.ReadReq_hits::total        26742                       # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1            3                       # number of WriteReq hits
+system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            3                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            3                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1        26745                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker        26745                       # number of demand (read+write) hits
 system.cpu.itb_walker_cache.demand_hits::total        26745                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1        26745                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker        26745                       # number of overall hits
 system.cpu.itb_walker_cache.overall_hits::total        26745                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         9424                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         9424                       # number of ReadReq misses
 system.cpu.itb_walker_cache.ReadReq_misses::total         9424                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         9424                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         9424                       # number of demand (read+write) misses
 system.cpu.itb_walker_cache.demand_misses::total         9424                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         9424                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         9424                       # number of overall misses
 system.cpu.itb_walker_cache.overall_misses::total         9424                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency    120935500                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency    120935500                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency    120935500                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        36166                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker    120935500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total    120935500                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker    120935500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total    120935500                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker    120935500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total    120935500                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        36166                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.ReadReq_accesses::total        36166                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1            3                       # number of WriteReq accesses(hits+misses)
+system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            3                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            3                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        36169                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        36169                       # number of demand (read+write) accesses
 system.cpu.itb_walker_cache.demand_accesses::total        36169                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        36169                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        36169                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        36169                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.260576                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.260555                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.260555                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 12832.714346                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 12832.714346                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 12832.714346                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.260576                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.260555                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.260555                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 12832.714346                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 12832.714346                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 12832.714346                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -685,32 +726,26 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks           1616                       # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.ReadReq_mshr_misses         9424                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses         9424                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses         9424                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency     92324000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency     92324000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency     92324000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.260576                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.260555                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.260555                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  9796.689304                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  9796.689304                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  9796.689304                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.itb_walker_cache.writebacks::writebacks         1616                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total         1616                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         9424                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         9424                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         9424                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         9424                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         9424                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         9424                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     92324000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     92324000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     92324000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     92324000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     92324000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     92324000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.260576                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.260555                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.260555                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  9796.689304                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  9796.689304                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  9796.689304                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.replacements       140574                       # number of replacements
 system.cpu.dtb_walker_cache.tagsinuse       13.858803                       # Cycle average of tags in use
@@ -718,51 +753,39 @@ system.cpu.dtb_walker_cache.total_refs         148049                       # To
 system.cpu.dtb_walker_cache.sampled_refs       140589                       # Sample count of references to valid blocks.
 system.cpu.dtb_walker_cache.avg_refs         1.053062                       # Average number of references to valid blocks.
 system.cpu.dtb_walker_cache.warmup_cycle 5108661869000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1    13.858803                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.866175                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1       148058                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker    13.858803                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.866175                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.866175                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker       148058                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.ReadReq_hits::total       148058                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1       148058                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker       148058                       # number of demand (read+write) hits
 system.cpu.dtb_walker_cache.demand_hits::total       148058                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1       148058                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker       148058                       # number of overall hits
 system.cpu.dtb_walker_cache.overall_hits::total       148058                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1       141571                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker       141571                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.ReadReq_misses::total       141571                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1       141571                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker       141571                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.demand_misses::total       141571                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1       141571                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker       141571                       # number of overall misses
 system.cpu.dtb_walker_cache.overall_misses::total       141571                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency   1989434500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency   1989434500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency   1989434500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1       289629                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker   1989434500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total   1989434500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker   1989434500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total   1989434500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker   1989434500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total   1989434500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker       289629                       # number of ReadReq accesses(hits+misses)
 system.cpu.dtb_walker_cache.ReadReq_accesses::total       289629                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1       289629                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker       289629                       # number of demand (read+write) accesses
 system.cpu.dtb_walker_cache.demand_accesses::total       289629                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1       289629                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker       289629                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total       289629                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.488801                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.488801                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.488801                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 14052.556668                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 14052.556668                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 14052.556668                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.488801                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.488801                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.488801                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 14052.556668                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 14052.556668                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 14052.556668                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -771,32 +794,26 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks          49457                       # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses       141571                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses       141571                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses       141571                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency   1560743500                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency   1560743500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency   1560743500                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.488801                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.488801                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.488801                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency 11024.457693                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency 11024.457693                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency 11024.457693                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dtb_walker_cache.writebacks::writebacks        49457                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total        49457                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker       141571                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total       141571                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker       141571                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total       141571                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker       141571                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total       141571                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker   1560743500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total   1560743500                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker   1560743500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total   1560743500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker   1560743500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total   1560743500                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.488801                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.488801                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.488801                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 11024.457693                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1662584                       # number of replacements
 system.cpu.dcache.tagsinuse                511.995323                       # Cycle average of tags in use
@@ -804,62 +821,49 @@ system.cpu.dcache.total_refs                 19274168                       # To
 system.cpu.dcache.sampled_refs                1663096                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  11.589330                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               34335000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.995323                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999991                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            11173849                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.995323                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999991                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999991                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     11173849                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        11173849                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            8093995                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8093995                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        8093995                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             19267844                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      19267844                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         19267844                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            19267844                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     19267844                       # number of overall hits
 system.cpu.dcache.overall_hits::total        19267844                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           2389581                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      2389581                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       2389581                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           320205                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       320205                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       320205                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            2709786                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      2709786                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        2709786                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           2709786                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      2709786                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2709786                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    35746262500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   10712131492                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     46458393992                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    46458393992                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13563430                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  35746262500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  35746262500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10712131492                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10712131492                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  46458393992                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  46458393992                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  46458393992                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  46458393992                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13563430                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     13563430                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8414200                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8414200                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      8414200                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         21977630                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     21977630                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     21977630                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        21977630                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21977630                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21977630                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.176178                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.038055                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.123297                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.123297                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 14959.217746                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33453.979457                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 17144.672676                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 17144.672676                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.176178                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.038055                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.123297                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.123297                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14959.217746                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33453.979457                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 17144.672676                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 17144.672676                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     27702492                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              4792                       # number of cycles access was blocked
@@ -868,44 +872,49 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  5780.987479
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1550496                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           1018010                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits            22803                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1040813                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1040813                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1371571                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         297402                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1668973                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1668973                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  18013626000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   9484899492                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  27498525492                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  27498525492                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  85207760000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1392508500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  86600268500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.101123                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.035345                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.075940                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.075940                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 13133.571649                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31892.520871                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 16476.315370                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 16476.315370                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1550496                       # number of writebacks
+system.cpu.dcache.writebacks::total           1550496                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      1018010                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      1018010                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        22803                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        22803                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1040813                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1040813                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1040813                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1040813                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1371571                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1371571                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       297402                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       297402                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1668973                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1668973                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1668973                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1668973                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  18013626000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  18013626000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   9484899492                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   9484899492                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  27498525492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  27498525492                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  27498525492                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  27498525492                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  85207760000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  85207760000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1392508500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1392508500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  86600268500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  86600268500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.101123                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.035345                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075940                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075940                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13133.571649                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31892.520871                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16476.315370                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16476.315370                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                        0                       # number of quiesce instructions executed
index 409b736b635114e7b6b8a8d950b8c848e3bf1de5..490c0c72f204520d1277b71263eaa75bf59025b8 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=200000000
 time_sync_spin_threshold=200000
@@ -8,7 +9,6 @@ time_sync_spin_threshold=200000
 [system]
 type=SparcSystem
 children=bridge cpu disk0 hypervisor_desc intrctrl iobus membus nvram partition_desc physmem physmem2 rom t1000
-boot_cpu_frequency=1
 boot_osflags=a
 hypervisor_addr=1099243257856
 hypervisor_bin=/dist/m5/system/binaries/q_new.bin
@@ -19,7 +19,7 @@ init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=atomic
-memories=system.physmem2 system.nvram system.partition_desc system.rom system.physmem system.hypervisor_desc
+memories=system.rom system.hypervisor_desc system.physmem2 system.nvram system.physmem system.partition_desc
 num_work_ids=16
 nvram=system.nvram
 nvram_addr=133429198848
@@ -83,6 +83,7 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
+workload=
 dcache_port=system.membus.port[11]
 icache_port=system.membus.port[10]
 
@@ -106,7 +107,6 @@ children=image
 image=system.disk0.image
 pio_addr=134217728000
 pio_latency=2
-platform=system.t1000
 system=system
 pio=system.iobus.port[15]
 
@@ -165,7 +165,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -238,7 +237,6 @@ fake_mem=false
 pio_addr=644245094400
 pio_latency=2
 pio_size=4294967296
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -255,7 +253,6 @@ fake_mem=false
 pio_addr=549755813888
 pio_latency=2
 pio_size=4294967296
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -272,7 +269,6 @@ fake_mem=false
 pio_addr=725849473024
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -289,7 +285,6 @@ fake_mem=false
 pio_addr=725849473088
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -306,7 +301,6 @@ fake_mem=false
 pio_addr=725849473152
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -323,7 +317,6 @@ fake_mem=false
 pio_addr=725849473216
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -340,7 +333,6 @@ fake_mem=false
 pio_addr=734439407616
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -357,7 +349,6 @@ fake_mem=false
 pio_addr=734439407680
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -374,7 +365,6 @@ fake_mem=false
 pio_addr=734439407744
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -391,7 +381,6 @@ fake_mem=false
 pio_addr=734439407808
 pio_latency=2
 pio_size=8
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -408,7 +397,6 @@ fake_mem=false
 pio_addr=648540061696
 pio_latency=2
 pio_size=16384
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -425,7 +413,6 @@ fake_mem=false
 pio_addr=1095216660480
 pio_latency=2
 pio_size=268435456
-platform=system.t1000
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -447,7 +434,6 @@ port=3456
 type=DumbTOD
 pio_addr=1099255906296
 pio_latency=2
-platform=system.t1000
 system=system
 time=Thu Jan  1 00:00:00 2009
 pio=system.membus.port[1]
index d81b5c20f2909c423a2bb667c315e3cd625b3af2..c2315f7a13ab1a0d7876d460a749bcbe6799d120 100755 (executable)
@@ -1,14 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:05:05
-gem5 started Jan 23 2012 06:26:23
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:02:46
 gem5 executing on zizzer
-command line: build/SPARC_FS/gem5.opt -d build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC_FS/tests/opt/long/80.solaris-boot/sparc/solaris/t1000-simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/fast/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
-      0: system.t1000.htod: Real-time clock set to Thu Jan  1 00:00:00 2009
-
-      0: system.t1000.htod: Real-time clock set to 1230768000
 info: No kernel set for full system simulation. Assuming you know what you're doing...
 info: Entering event queue @ 0.  Starting simulation...
 info: Ignoring write to SPARC ERROR regsiter
index 21a50a501fa978b4c05c178a9ef906f1bab43eb1..26c5818ca7e4f52fb493d48517175e92ccfd39c5 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.116889                       # Nu
 sim_ticks                                  2233777512                       # Number of ticks simulated
 final_tick                                 2233777512                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                3505728                       # Simulator instruction rate (inst/s)
-host_tick_rate                                3512989                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 500940                       # Number of bytes of host memory used
-host_seconds                                   635.86                       # Real time elapsed on the host
-sim_insts                                  2229160714                       # Number of instructions simulated
+host_inst_rate                                4520258                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4522035                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                4531400                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 500812                       # Number of bytes of host memory used
+host_seconds                                   492.96                       # Real time elapsed on the host
+sim_insts                                  2228284650                       # Number of instructions simulated
+sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
 system.hypervisor_desc.bytes_read               16792                       # Number of bytes read from this memory
 system.hypervisor_desc.bytes_inst_read              0                       # Number of instructions bytes read from this memory
 system.hypervisor_desc.bytes_written                0                       # Number of bytes written to this memory
@@ -17,6 +19,15 @@ system.hypervisor_desc.num_writes                   0                       # Nu
 system.hypervisor_desc.num_other                    0                       # Number of other requests responded to by this memory
 system.hypervisor_desc.bw_read                  15035                       # Total read bandwidth from this memory (bytes/s)
 system.hypervisor_desc.bw_total                 15035                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read                         1128688                       # Number of bytes read from this memory
+system.rom.bytes_inst_read                     432296                       # Number of instructions bytes read from this memory
+system.rom.bytes_written                            0                       # Number of bytes written to this memory
+system.rom.num_reads                           195123                       # Number of read requests responded to by this memory
+system.rom.num_writes                               0                       # Number of write requests responded to by this memory
+system.rom.num_other                                0                       # Number of other requests responded to by this memory
+system.rom.bw_read                            1010564                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read                        387054                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total                           1010564                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem2.bytes_read                 9813991967                       # Number of bytes read from this memory
 system.physmem2.bytes_inst_read            8318106840                       # Number of instructions bytes read from this memory
 system.physmem2.bytes_written               897268422                       # Number of bytes written to this memory
@@ -36,23 +47,6 @@ system.nvram.num_other                              0                       # Nu
 system.nvram.bw_read                              254                       # Total read bandwidth from this memory (bytes/s)
 system.nvram.bw_write                              82                       # Write bandwidth from this memory (bytes/s)
 system.nvram.bw_total                             337                       # Total bandwidth to/from this memory (bytes/s)
-system.partition_desc.bytes_read                 4846                       # Number of bytes read from this memory
-system.partition_desc.bytes_inst_read               0                       # Number of instructions bytes read from this memory
-system.partition_desc.bytes_written                 0                       # Number of bytes written to this memory
-system.partition_desc.num_reads                   608                       # Number of read requests responded to by this memory
-system.partition_desc.num_writes                    0                       # Number of write requests responded to by this memory
-system.partition_desc.num_other                     0                       # Number of other requests responded to by this memory
-system.partition_desc.bw_read                    4339                       # Total read bandwidth from this memory (bytes/s)
-system.partition_desc.bw_total                   4339                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read                         1128688                       # Number of bytes read from this memory
-system.rom.bytes_inst_read                     432296                       # Number of instructions bytes read from this memory
-system.rom.bytes_written                            0                       # Number of bytes written to this memory
-system.rom.num_reads                           195123                       # Number of read requests responded to by this memory
-system.rom.num_writes                               0                       # Number of write requests responded to by this memory
-system.rom.num_other                                0                       # Number of other requests responded to by this memory
-system.rom.bw_read                            1010564                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read                        387054                       # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total                           1010564                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read                   709825348                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              612291324                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 15400223                       # Number of bytes written to this memory
@@ -63,10 +57,19 @@ system.physmem.bw_read                      635538091                       # To
 system.physmem.bw_inst_read                 548211557                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write                      13788502                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total                     649326593                       # Total bandwidth to/from this memory (bytes/s)
+system.partition_desc.bytes_read                 4846                       # Number of bytes read from this memory
+system.partition_desc.bytes_inst_read               0                       # Number of instructions bytes read from this memory
+system.partition_desc.bytes_written                 0                       # Number of bytes written to this memory
+system.partition_desc.num_reads                   608                       # Number of read requests responded to by this memory
+system.partition_desc.num_writes                    0                       # Number of write requests responded to by this memory
+system.partition_desc.num_other                     0                       # Number of other requests responded to by this memory
+system.partition_desc.bw_read                    4339                       # Total read bandwidth from this memory (bytes/s)
+system.partition_desc.bw_total                   4339                       # Total bandwidth to/from this memory (bytes/s)
 system.cpu.numCycles                       2233777513                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       2229160714                       # Number of instructions executed
+system.cpu.committedInsts                  2228284650                       # Number of instructions committed
+system.cpu.committedOps                    2229160714                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1839325658                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               14608322                       # Number of float alu accesses
 system.cpu.num_func_calls                    44037246                       # number of times a function call or return occured
index 6c1c0e974e724703d10a0dd1f5eb6c0473928d07..b932d7fd7c1a0622aa8c7f91f1747a6b1bef7b99 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -202,7 +194,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
index 30b31a52734db7f08ffc70f395f19abd083ffc06..26d645fed17a1828f2a35288fceab7830192918f 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:21
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index b5662ac02ceb747495f6e83cdc41668844e75d98..1a8f0456164ab3e2abf565b7de0358ccbba38480 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.274500                       # Nu
 sim_ticks                                274500333500                       # Number of ticks simulated
 final_tick                               274500333500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 113367                       # Simulator instruction rate (inst/s)
-host_tick_rate                               51705325                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207980                       # Number of bytes of host memory used
-host_seconds                                  5308.94                       # Real time elapsed on the host
+host_inst_rate                                 160535                       # Simulator instruction rate (inst/s)
+host_op_rate                                   160535                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               73218214                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209892                       # Number of bytes of host memory used
+host_seconds                                  3749.07                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
+sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5894016                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  54720                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3798080                       # Number of bytes written to this memory
@@ -69,9 +71,10 @@ system.cpu.comNops                           36304520                       # Nu
 system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                          349039879                       # Number of Integer instructions committed
 system.cpu.comFloats                               24                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                   601856964                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total             601856964                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                   601856964                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                     601856964                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total             601856964                       # Number of Instructions committed (Total)
 system.cpu.cpi                               0.912178                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         0.912178                       # CPI: Total CPI of All Threads
@@ -125,26 +128,39 @@ system.cpu.icache.total_refs                 27985205                       # To
 system.cpu.icache.sampled_refs                    855                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               32731.233918                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            728.259897                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.355596                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               27985205                       # number of ReadReq hits
-system.cpu.icache.demand_hits                27985205                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               27985205                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1019                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1019                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1019                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       56646500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        56646500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       56646500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           27986224                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            27986224                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           27986224                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000036                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000036                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000036                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55590.284593                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55590.284593                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55590.284593                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     728.259897                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.355596                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.355596                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     27985205                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        27985205                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      27985205                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         27985205                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     27985205                       # number of overall hits
+system.cpu.icache.overall_hits::total        27985205                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1019                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1019                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1019                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1019                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1019                       # number of overall misses
+system.cpu.icache.overall_misses::total          1019                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     56646500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     56646500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     56646500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     56646500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     56646500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     56646500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     27986224                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     27986224                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     27986224                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     27986224                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     27986224                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     27986224                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000036                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000036                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000036                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55590.284593                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55590.284593                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55590.284593                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        43500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets        21750                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               164                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                164                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               164                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             855                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              855                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             855                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     45774000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     45774000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     45774000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000031                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000031                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000031                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53536.842105                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53536.842105                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53536.842105                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          164                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          164                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          164                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          164                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          164                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          164                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          855                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          855                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          855                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          855                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          855                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          855                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     45774000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     45774000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     45774000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     45774000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     45774000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     45774000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000031                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000031                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000031                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53536.842105                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53536.842105                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53536.842105                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 451299                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.126386                       # Cycle average of tags in use
@@ -181,32 +200,49 @@ system.cpu.dcache.total_refs                152394244                       # To
 system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 334.641891                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              267624000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.126386                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999543                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              114120509                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              38273735                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               152394244                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              152394244                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               393533                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1177586                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1571119                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1571119                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     8150453500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   25245531000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     33395984500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    33395984500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          114514042                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           153965363                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.003437                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.029849                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.010204                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.010204                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 20710.978495                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 21438.375626                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 21256.177603                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 21256.177603                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.126386                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999543                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999543                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    114120509                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114120509                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     38273735                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       38273735                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     152394244                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        152394244                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    152394244                       # number of overall hits
+system.cpu.dcache.overall_hits::total       152394244                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       393533                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        393533                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1177586                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1177586                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1571119                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1571119                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1571119                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1571119                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8150453500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8150453500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  25245531000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  25245531000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  33395984500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  33395984500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  33395984500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  33395984500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003437                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029849                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.010204                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.010204                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20710.978495                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 21438.375626                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 21256.177603                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 21256.177603                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     12016500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets   3424460500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              2770                       # number of cycles access was blocked
@@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  4338.086643
 system.cpu.dcache.avg_blocked_cycles::no_targets 15836.021642                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   408188                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            192301                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           923423                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1115724                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1115724                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          201232                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         254163                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           455395                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          455395                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3562138000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5466740000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   9028878000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   9028878000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001757                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006442                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002958                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002958                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17701.647849                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 21508.795537                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19826.475917                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19826.475917                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       408188                       # number of writebacks
+system.cpu.dcache.writebacks::total            408188                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       192301                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       192301                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       923423                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       923423                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1115724                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1115724                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1115724                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1115724                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3562138000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3562138000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5466740000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5466740000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9028878000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9028878000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9028878000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9028878000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17701.647849                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 21508.795537                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19826.475917                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19826.475917                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 73797                       # number of replacements
 system.cpu.l2cache.tagsinuse             17695.095192                       # Cycle average of tags in use
@@ -248,36 +292,72 @@ system.cpu.l2cache.total_refs                  445688                       # To
 system.cpu.l2cache.sampled_refs                 89683                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.969593                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1638.137841                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16056.957351                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.049992                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.490019                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                170051                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              408188                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              194105                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 364156                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                364156                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32019                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             60075                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                92094                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               92094                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1674917000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3134446000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4809363000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4809363000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            202070                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          408188                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          254180                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             456250                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            456250                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.158455                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.236348                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.201850                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.201850                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52310.097130                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52175.547233                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52222.327187                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52222.327187                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16056.957351                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     28.224139                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1609.913702                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.490019                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000861                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.049131                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.540011                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       170051                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         170051                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       408188                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       408188                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       194105                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       194105                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       364156                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          364156                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       364156                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         364156                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          855                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31164                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32019                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        60075                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        60075                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          855                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91239                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92094                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          855                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91239                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92094                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     44769000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1630148000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1674917000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3134446000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3134446000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     44769000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4764594000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4809363000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     44769000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4764594000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4809363000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          855                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       201215                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       202070                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       408188                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       408188                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254180                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          855                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       455395                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       456250                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          855                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       455395                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       456250                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.154879                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.236348                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200351                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200351                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.403509                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52308.689514                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52175.547233                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.403509                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52221.023904                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.403509                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52221.023904                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs      1295000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs              127                       # number of cycles access was blocked
@@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10196.850394
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59345                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32019                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        60075                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           92094                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          92094                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1281026000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2406899500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3687925500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3687925500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.158455                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.236348                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.201850                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.201850                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40008.307567                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40064.910529                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40045.230960                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40045.230960                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        59345                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59345                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          855                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31164                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32019                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        60075                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        60075                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          855                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91239                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92094                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          855                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91239                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92094                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34345000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1246681000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1281026000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2406899500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2406899500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34345000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3653580500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3687925500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34345000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3653580500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3687925500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.154879                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.236348                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200351                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200351                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40169.590643                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40003.882685                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40064.910529                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40169.590643                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40044.065586                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40169.590643                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40044.065586                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index cc9b0c6836df6eb1dfa455c6f06cbbfd6b66cb35..d5e06addca7bd4d7157d504e8fc6e48bc615450d 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
index ad1c408b1ab32195439b64ddd596215b662f9905..e473c70fdb2c74a977fff4b501ec486bfd7460ac 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:26
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 8681db468c75a7306b642bc68ecff5e7f813a560..6a8942bebaa48d7addaf682877c46281e67a8440 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.144450                       # Nu
 sim_ticks                                144450185500                       # Number of ticks simulated
 final_tick                               144450185500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 205040                       # Simulator instruction rate (inst/s)
-host_tick_rate                               52370107                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208620                       # Number of bytes of host memory used
-host_seconds                                  2758.26                       # Real time elapsed on the host
+host_inst_rate                                 270959                       # Simulator instruction rate (inst/s)
+host_op_rate                                   270959                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69206896                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211048                       # Number of bytes of host memory used
+host_seconds                                  2087.22                       # Real time elapsed on the host
 sim_insts                                   565552443                       # Number of instructions simulated
+sim_ops                                     565552443                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5936768                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  60416                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3797120                       # Number of bytes written to this memory
@@ -272,6 +274,7 @@ system.cpu.iew.wb_rate                       2.107953                       # in
 system.cpu.iew.wb_fanout                     0.790402                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      601856963                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        601856963                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        84796787                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           4132184                       # The number of times a branch was mispredicted
@@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    276422432                       # Number of insts commited each cycle
-system.cpu.commit.count                     601856963                       # Number of instructions committed
+system.cpu.commit.committedInsts            601856963                       # Number of instructions committed
+system.cpu.commit.committedOps              601856963                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      153965363                       # Number of memory references committed
 system.cpu.commit.loads                     114514042                       # Number of loads committed
@@ -308,6 +312,7 @@ system.cpu.rob.rob_writes                  1385724156                       # Th
 system.cpu.timesIdled                            2221                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           68890                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   565552443                       # Number of Instructions Simulated
+system.cpu.committedOps                     565552443                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             565552443                       # Number of Instructions Simulated
 system.cpu.cpi                               0.510829                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         0.510829                       # CPI: Total CPI of All Threads
@@ -325,26 +330,39 @@ system.cpu.icache.total_refs                 70951127                       # To
 system.cpu.icache.sampled_refs                    944                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               75160.092161                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            801.236568                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.391229                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               70951127                       # number of ReadReq hits
-system.cpu.icache.demand_hits                70951127                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               70951127                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1272                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1272                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1272                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       45919500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        45919500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       45919500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           70952399                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            70952399                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           70952399                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000018                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000018                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36100.235849                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36100.235849                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36100.235849                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     801.236568                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.391229                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.391229                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     70951127                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        70951127                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      70951127                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         70951127                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     70951127                       # number of overall hits
+system.cpu.icache.overall_hits::total        70951127                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1272                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1272                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1272                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1272                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1272                       # number of overall misses
+system.cpu.icache.overall_misses::total          1272                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45919500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45919500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45919500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45919500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45919500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45919500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     70952399                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     70952399                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     70952399                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     70952399                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     70952399                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     70952399                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000018                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000018                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000018                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36100.235849                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36100.235849                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36100.235849                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               328                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                328                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               328                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             944                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              944                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             944                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     33676000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     33676000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     33676000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000013                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000013                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000013                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35673.728814                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35673.728814                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35673.728814                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          328                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          328                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          328                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          328                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          944                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          944                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          944                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          944                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          944                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          944                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     33676000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     33676000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     33676000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     33676000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     33676000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     33676000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000013                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000013                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000013                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35673.728814                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35673.728814                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35673.728814                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 470690                       # number of replacements
 system.cpu.dcache.tagsinuse               4093.940031                       # Cycle average of tags in use
@@ -381,34 +402,53 @@ system.cpu.dcache.total_refs                151212527                       # To
 system.cpu.dcache.sampled_refs                 474786                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 318.485648                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              126051000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4093.940031                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999497                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              113064898                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              38147626                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                3                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               151212524                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              151212524                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               732041                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1303695                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2035736                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2035736                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    11783533000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   19632740219                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     31416273219                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    31416273219                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          113796939                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           153248260                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          153248260                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.006433                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.033046                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.013284                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.013284                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 16096.821080                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 15059.304683                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15432.390653                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15432.390653                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4093.940031                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999497                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999497                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    113064898                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       113064898                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     38147626                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       38147626                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            3                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            3                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     151212524                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        151212524                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    151212524                       # number of overall hits
+system.cpu.dcache.overall_hits::total       151212524                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       732041                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        732041                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1303695                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1303695                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2035736                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2035736                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2035736                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2035736                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11783533000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11783533000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  19632740219                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  19632740219                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  31416273219                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  31416273219                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  31416273219                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  31416273219                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    113796939                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    113796939                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    153248260                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    153248260                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    153248260                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    153248260                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006433                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.033046                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.013284                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.013284                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16096.821080                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15059.304683                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15432.390653                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15432.390653                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs       804496                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       236500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs               116                       # number of cycles access was blocked
@@ -417,32 +457,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  6935.310345
 system.cpu.dcache.avg_blocked_cycles::no_targets        21500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   423044                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            513277                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1047673                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1560950                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1560950                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          218764                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         256022                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           474786                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          474786                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1640072500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3027658494                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4667730994                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4667730994                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001922                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006490                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.003098                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.003098                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7496.994478                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 11825.774715                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  9831.231321                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  9831.231321                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       423044                       # number of writebacks
+system.cpu.dcache.writebacks::total            423044                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       513277                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       513277                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1047673                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1047673                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1560950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1560950                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1560950                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1560950                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       218764                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       218764                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       256022                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       256022                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       474786                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       474786                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       474786                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       474786                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1640072500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1640072500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3027658494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3027658494                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4667730994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   4667730994                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4667730994                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   4667730994                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001922                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006490                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003098                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003098                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7496.994478                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 11825.774715                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  9831.231321                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  9831.231321                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 74463                       # number of replacements
 system.cpu.l2cache.tagsinuse             17661.712037                       # Cycle average of tags in use
@@ -450,36 +498,72 @@ system.cpu.l2cache.total_refs                  478021                       # To
 system.cpu.l2cache.sampled_refs                 90363                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  5.290008                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1743.919943                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15917.792095                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.053220                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.485772                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                186750                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              423044                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              196218                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 382968                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                382968                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32958                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             59804                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                92762                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               92762                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1133680000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2065878500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3199558500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3199558500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            219708                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          423044                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          256022                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             475730                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            475730                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.150008                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.233589                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.194989                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.194989                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34397.718308                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34544.152565                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34492.125008                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34492.125008                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15917.792095                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     36.116254                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1707.803688                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.485772                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001102                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.052118                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.538993                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       186750                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         186750                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       423044                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       423044                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       196218                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       196218                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       382968                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          382968                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       382968                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         382968                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          944                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        32014                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32958                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        59804                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        59804                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          944                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91818                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92762                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          944                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91818                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92762                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32444500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1101235500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1133680000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2065878500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2065878500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32444500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3167114000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3199558500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32444500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3167114000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3199558500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          944                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       218764                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       219708                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       423044                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       423044                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       256022                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       256022                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          944                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       474786                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       475730                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          944                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       474786                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       475730                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.146340                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.233589                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.193388                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.193388                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34369.173729                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34398.560005                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34544.152565                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34369.173729                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34493.389096                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34369.173729                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34493.389096                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs       370500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs               72                       # number of cycles access was blocked
@@ -488,30 +572,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5145.833333
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59330                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32958                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        59804                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           92762                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          92762                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1022345000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1877543500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2899888500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2899888500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.150008                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.233589                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.194989                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.194989                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31019.631046                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31394.948498                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31261.599577                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31261.599577                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        59330                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59330                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          944                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        32014                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32958                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        59804                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        59804                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          944                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91818                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92762                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          944                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91818                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92762                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     29409000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    992936000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1022345000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1877543500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1877543500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     29409000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2870479500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2899888500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     29409000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2870479500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2899888500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.146340                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.233589                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193388                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193388                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31153.601695                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31015.680640                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31394.948498                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31153.601695                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31262.709926                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31153.601695                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31262.709926                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 28214177293dbc96e521a367a70b90711ee01f4e..8be56150d7ecb914f2c16779c9b4e9d066a9671e 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
index 1dc40214171a2ce4ba94b58dc56b13fd23f000be..b88c1587511ba6b807fd2d745873d150c59d70ba 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:30
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index ad4f39b85ab8546cccb9f5a4c0445a9b3d5305ee..97a3f27341045a4258c94045ff00349fbb1de4d4 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.300931                       # Nu
 sim_ticks                                300930958000                       # Number of ticks simulated
 final_tick                               300930958000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4527143                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2263589972                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 198960                       # Number of bytes of host memory used
-host_seconds                                   132.94                       # Real time elapsed on the host
+host_inst_rate                                5630967                       # Simulator instruction rate (inst/s)
+host_op_rate                                  5630966                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2815505896                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 200704                       # Number of bytes of host memory used
+host_seconds                                   106.88                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
+sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2782990928                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             2407447588                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                152669504                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                        601861917                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        601856964                       # Number of instructions executed
+system.cpu.committedInsts                   601856964                       # Number of instructions committed
+system.cpu.committedOps                     601856964                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
 system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
index 0bc5277c79aba3ff206ff9c87906a943dc4a1e5f..83c88fa93ecb6514265038a4eba4dec1dd43b564 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
index 36bd68fb714a114d9eaad83089d5cbcb59c2839c..dfe9fcdd25a3d546220ccbc4b970182fe5f6c1fc 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:31
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/00.gzip/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/00.gzip/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 4d7850adf1940d07df8476e4d1f382efeaad0b18..4b454bbcf77186b2b02a0fb5129eada27cec8b98 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.765623                       # Nu
 sim_ticks                                765623032000                       # Number of ticks simulated
 final_tick                               765623032000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2199350                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2797795440                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207676                       # Number of bytes of host memory used
-host_seconds                                   273.65                       # Real time elapsed on the host
+host_inst_rate                                2698243                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2698243                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3432438217                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209572                       # Number of bytes of host memory used
+host_seconds                                   223.06                       # Real time elapsed on the host
 sim_insts                                   601856964                       # Number of instructions simulated
+sim_ops                                     601856964                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5889984                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  50880                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3797824                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                       1531246064                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        601856964                       # Number of instructions executed
+system.cpu.committedInsts                   601856964                       # Number of instructions committed
+system.cpu.committedOps                     601856964                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             563959696                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                   1520                       # Number of float alu accesses
 system.cpu.num_func_calls                     2395217                       # number of times a function call or return occured
@@ -79,26 +82,39 @@ system.cpu.icache.total_refs                601861103                       # To
 system.cpu.icache.sampled_refs                    795                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               757057.991195                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            673.337154                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.328778                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              601861103                       # number of ReadReq hits
-system.cpu.icache.demand_hits               601861103                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              601861103                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  795                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   795                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  795                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       44520000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        44520000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       44520000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          601861898                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           601861898                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          601861898                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     673.337154                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.328778                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.328778                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    601861103                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       601861103                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     601861103                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        601861103                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    601861103                       # number of overall hits
+system.cpu.icache.overall_hits::total       601861103                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          795                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           795                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          795                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            795                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          795                       # number of overall misses
+system.cpu.icache.overall_misses::total           795                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44520000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44520000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44520000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44520000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44520000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44520000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    601861898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    601861898                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    601861898                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    601861898                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    601861898                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    601861898                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             795                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              795                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             795                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     42135000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     42135000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     42135000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          795                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          795                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          795                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          795                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          795                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          795                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42135000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42135000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42135000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42135000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42135000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42135000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 451299                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.170317                       # Cycle average of tags in use
@@ -134,32 +148,49 @@ system.cpu.dcache.total_refs                153509968                       # To
 system.cpu.dcache.sampled_refs                 455395                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 337.091905                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              578392000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.170317                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999553                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              114312810                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              39197158                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               153509968                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              153509968                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               201232                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              254163                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                455395                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               455395                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     4126262000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    6081180000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     10207442000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    10207442000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          114514042                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          39451321                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           153965363                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          153965363                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.001757                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.006442                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.002958                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002958                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 20504.999205                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23926.299265                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 22414.479737                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 22414.479737                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.170317                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999553                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    114312810                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       114312810                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     39197158                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       39197158                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     153509968                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        153509968                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    153509968                       # number of overall hits
+system.cpu.dcache.overall_hits::total       153509968                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       201232                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        201232                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       254163                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       254163                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       455395                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         455395                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       455395                       # number of overall misses
+system.cpu.dcache.overall_misses::total        455395                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4126262000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4126262000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   6081180000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   6081180000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  10207442000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  10207442000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  10207442000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  10207442000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    114514042                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     39451321                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    153965363                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    153965363                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001757                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006442                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002958                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002958                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20504.999205                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23926.299265                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22414.479737                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22414.479737                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   408190                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          201232                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         254163                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           455395                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          455395                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3522566000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5318691000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   8841257000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   8841257000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001757                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006442                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002958                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002958                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17504.999205                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20926.299265                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19414.479737                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       408190                       # number of writebacks
+system.cpu.dcache.writebacks::total            408190                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       201232                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       254163                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       455395                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       455395                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       455395                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3522566000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3522566000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5318691000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5318691000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8841257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8841257000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8841257000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   8841257000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001757                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006442                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002958                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17504.999205                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20926.299265                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19414.479737                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19414.479737                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 73734                       # number of replacements
 system.cpu.l2cache.tagsinuse             17823.514890                       # Cycle average of tags in use
@@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs                  445709                       # To
 system.cpu.l2cache.sampled_refs                 89622                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.973210                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1722.436058                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16101.078831                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.052565                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.491366                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                170065                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              408190                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              194094                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 364159                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                364159                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               31962                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             60069                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                92031                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               92031                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1662024000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3123588000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4785612000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4785612000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            202027                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          408190                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          254163                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             456190                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            456190                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.158207                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.236340                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.201738                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.201738                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16101.078831                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     29.487971                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1692.948088                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.491366                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000900                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.051665                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.543931                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       170065                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         170065                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       408190                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       408190                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       194094                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       194094                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       364159                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          364159                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       364159                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         364159                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          795                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31167                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31962                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        60069                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        60069                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          795                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91236                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92031                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          795                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91236                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92031                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     41340000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1620684000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1662024000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3123588000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3123588000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     41340000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4744272000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4785612000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     41340000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4744272000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4785612000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          795                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       201232                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       202027                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       408190                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       254163                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       254163                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          795                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       455395                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       456190                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          795                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       455395                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       456190                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.154881                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.236340                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200345                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200345                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59341                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          31962                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        60069                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           92031                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          92031                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1278480000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2402760000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3681240000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3681240000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.158207                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.236340                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.201738                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.201738                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        59341                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59341                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          795                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31167                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31962                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        60069                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        60069                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          795                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91236                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92031                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          795                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91236                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92031                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1246680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1278480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2402760000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2402760000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3649440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3681240000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3649440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3681240000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.154881                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.236340                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200345                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200345                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 2c3feadf1878473710fef72a4ab49cb705ec95ee..c24180c55c176e7f1ea83a19c26753c897f8534f 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/gzip
+executable=/dist/m5/cpu2000/binaries/arm/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
index 316fa1ee53d911fb1f9f4b8ecd177960868f4ab4..c2143f70cbad23578242ba761173b5c157a4d474 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:23
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/00.gzip/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:39:44
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index e05b6f9856d747d69e5e8bfa3bf2190975432565..e204ea2b269be86cf055b186e204edd2c2c58cc2 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.177117                       # Nu
 sim_ticks                                177116942500                       # Number of ticks simulated
 final_tick                               177116942500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  89657                       # Simulator instruction rate (inst/s)
-host_tick_rate                               26362655                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256136                       # Number of bytes of host memory used
-host_seconds                                  6718.48                       # Real time elapsed on the host
-sim_insts                                   602359810                       # Number of instructions simulated
+host_inst_rate                                 193712                       # Simulator instruction rate (inst/s)
+host_op_rate                                   204690                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60186856                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223404                       # Number of bytes of host memory used
+host_seconds                                  2942.78                       # Real time elapsed on the host
+sim_insts                                   570051603                       # Number of instructions simulated
+sim_ops                                     602359810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5833792                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  46976                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3720320                       # Number of bytes written to this memory
@@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.835552                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.643966                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      602359861                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      570051654                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        602359861                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       100193357                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            6347                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           4062580                       # The number of times a branch was mispredicted
@@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    339017045                       # Number of insts commited each cycle
-system.cpu.commit.count                     602359861                       # Number of instructions committed
+system.cpu.commit.committedInsts            570051654                       # Number of instructions committed
+system.cpu.commit.committedOps              602359861                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      219173611                       # Number of memory references committed
 system.cpu.commit.loads                     148952596                       # Number of loads committed
@@ -318,12 +322,13 @@ system.cpu.rob.rob_reads                   1023326216                       # Th
 system.cpu.rob.rob_writes                  1419524916                       # The number of ROB writes
 system.cpu.timesIdled                           37353                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          840358                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   602359810                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             602359810                       # Number of Instructions Simulated
-system.cpu.cpi                               0.588077                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.588077                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.700458                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.700458                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   570051603                       # Number of Instructions Simulated
+system.cpu.committedOps                     602359810                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             570051603                       # Number of Instructions Simulated
+system.cpu.cpi                               0.621407                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.621407                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.609252                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.609252                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               3275977261                       # number of integer regfile reads
 system.cpu.int_regfile_writes               676006750                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
@@ -335,26 +340,39 @@ system.cpu.icache.total_refs                 74421550                       # To
 system.cpu.icache.sampled_refs                    765                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               97283.071895                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            657.275674                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.320935                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               74421550                       # number of ReadReq hits
-system.cpu.icache.demand_hits                74421550                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               74421550                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  996                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   996                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  996                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       34937500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        34937500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       34937500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           74422546                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            74422546                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           74422546                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000013                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000013                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35077.811245                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35077.811245                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35077.811245                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     657.275674                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.320935                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.320935                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     74421550                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        74421550                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      74421550                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         74421550                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     74421550                       # number of overall hits
+system.cpu.icache.overall_hits::total        74421550                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          996                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           996                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          996                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            996                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          996                       # number of overall misses
+system.cpu.icache.overall_misses::total           996                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34937500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34937500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34937500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34937500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34937500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34937500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     74422546                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     74422546                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     74422546                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     74422546                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     74422546                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     74422546                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000013                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000013                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000013                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35077.811245                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35077.811245                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35077.811245                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               231                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                231                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               231                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             765                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              765                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             765                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     26235000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     26235000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     26235000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000010                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000010                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34294.117647                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34294.117647                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34294.117647                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          231                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          231                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          231                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          231                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          231                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          231                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          765                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          765                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          765                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          765                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          765                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          765                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     26235000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     26235000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     26235000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     26235000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     26235000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     26235000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000010                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34294.117647                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34294.117647                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34294.117647                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 441200                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.750887                       # Cycle average of tags in use
@@ -391,40 +412,63 @@ system.cpu.dcache.total_refs                205785268                       # To
 system.cpu.dcache.sampled_refs                 445296                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 462.131409                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               87972000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.750887                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999695                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              137930344                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              67852261                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             1334                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              1329                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               205782605                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              205782605                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               248964                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1565270                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              9                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1814234                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1814234                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     3282822000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   27026336525                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       201000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     30309158525                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    30309158525                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          138179308                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         1343                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          1329                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           207596839                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          207596839                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.001802                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.022549                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.006701                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.008739                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.008739                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 13185.930496                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 17266.245775                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 22333.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 16706.311603                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 16706.311603                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.750887                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999695                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999695                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    137930344                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       137930344                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     67852261                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       67852261                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         1334                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         1334                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         1329                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         1329                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     205782605                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        205782605                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    205782605                       # number of overall hits
+system.cpu.dcache.overall_hits::total       205782605                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       248964                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        248964                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1565270                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1565270                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            9                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            9                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1814234                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1814234                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1814234                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1814234                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   3282822000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   3282822000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  27026336525                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  27026336525                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       201000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       201000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  30309158525                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  30309158525                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  30309158525                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  30309158525                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    138179308                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    138179308                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1343                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         1343                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         1329                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         1329                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    207596839                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    207596839                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    207596839                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    207596839                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001802                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.022549                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.006701                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008739                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008739                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13185.930496                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17266.245775                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 22333.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16706.311603                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16706.311603                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs      9583027                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              2185                       # number of cycles access was blocked
@@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  4385.824714
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   395250                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             51046                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1317892                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            9                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1368938                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1368938                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          197918                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         247378                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           445296                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          445296                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1625205500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2544318027                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4169523527                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4169523527                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001432                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003564                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002145                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002145                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8211.509312                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 10285.142684                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  9363.487494                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  9363.487494                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       395250                       # number of writebacks
+system.cpu.dcache.writebacks::total            395250                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        51046                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        51046                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1317892                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1317892                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            9                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            9                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1368938                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1368938                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1368938                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1368938                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197918                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       197918                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247378                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       247378                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       445296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       445296                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       445296                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       445296                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1625205500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1625205500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2544318027                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2544318027                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4169523527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   4169523527                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4169523527                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   4169523527                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001432                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003564                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002145                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002145                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8211.509312                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 10285.142684                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  9363.487494                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  9363.487494                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 72965                       # number of replacements
 system.cpu.l2cache.tagsinuse             17807.300199                       # Cycle average of tags in use
@@ -467,36 +520,75 @@ system.cpu.l2cache.total_refs                  421253                       # To
 system.cpu.l2cache.sampled_refs                 88492                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.760351                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1881.136315                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15926.163884                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.057408                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.486028                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                165871                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              395250                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              189027                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 354898                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                354898                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32808                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58355                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                91163                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               91163                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1126263500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2003081500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3129345000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3129345000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            198679                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          395250                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          247382                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             446061                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            446061                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.165131                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.235890                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.204373                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.204373                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34328.928920                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34325.790421                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34326.919913                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34326.919913                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15926.163884                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     35.771827                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1845.364487                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.486028                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001092                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.056316                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.543436                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           30                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       165841                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         165871                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       395250                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       395250                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       189027                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       189027                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           30                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       354868                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          354898                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           30                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       354868                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         354898                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          735                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        32073                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32808                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        58355                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        58355                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          735                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        90428                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         91163                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          735                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        90428                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        91163                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     25238000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1101025500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1126263500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2003081500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2003081500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     25238000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3104107000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3129345000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     25238000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3104107000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3129345000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          765                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       197914                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       198679                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       395250                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       395250                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247382                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247382                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          765                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       445296                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       446061                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          765                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       445296                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       446061                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.960784                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.162055                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.235890                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.960784                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.203074                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.960784                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.203074                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34337.414966                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34328.734450                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34325.790421                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34337.414966                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34326.834609                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34337.414966                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34326.834609                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs      2057500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs              352                       # number of cycles access was blocked
@@ -505,31 +597,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs  5845.170455
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   58130                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32798                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58355                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           91153                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          91153                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1019340000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1822214500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2841554500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2841554500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165080                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235890                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.204351                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.204351                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31079.334106                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31226.364493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31173.461104                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31173.461104                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        58130                       # number of writebacks
+system.cpu.l2cache.writebacks::total            58130                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           10                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          734                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        32064                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32798                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        58355                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        58355                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          734                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        90419                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        91153                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          734                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        90419                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        91153                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22853000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    996487000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1019340000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1822214500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1822214500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22853000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2818701500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2841554500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22853000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2818701500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2841554500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.959477                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.162010                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.235890                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.959477                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.203054                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.959477                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.203054                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31134.877384                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31078.062625                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31226.364493                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31134.877384                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31173.774317                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31134.877384                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31173.774317                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8c7671d343d70f7f50b34698542c026b22642177..35f1e8fcc77c1b33a7cf4daf5827960bb5b8a30b 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index 95da0efca640eb0f30b1db929addc26baf1c94ce..d3f3c8cc8b011150d74b75c0d113edeb37662cfe 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:36:54
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:43:07
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index f48dc3640b503047724859c2eb54e0bf6d3422a3..80be44c4ed0b5410e6ffa3c6b92e03b030035389 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.301191                       # Nu
 sim_ticks                                301191370000                       # Number of ticks simulated
 final_tick                               301191370000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2998309                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1499211130                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210136                       # Number of bytes of host memory used
-host_seconds                                   200.90                       # Real time elapsed on the host
-sim_insts                                   602359851                       # Number of instructions simulated
+host_inst_rate                                3224710                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3407474                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1703801368                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212692                       # Number of bytes of host memory used
+host_seconds                                   176.78                       # Real time elapsed on the host
+sim_insts                                   570051644                       # Number of instructions simulated
+sim_ops                                     602359851                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2680160157                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             2280298136                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                236359611                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                   48                       # Nu
 system.cpu.numCycles                        602382741                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        602359851                       # Number of instructions executed
+system.cpu.committedInsts                   570051644                       # Number of instructions committed
+system.cpu.committedOps                     602359851                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
index 6a1e2b9700b0bc9eb12c66dcd72aabb486e4595b..ce56af1f45d1572a8fe9dac4a79c8981cc37c161 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 589b038624849bdfff0b8c7f11a460b5a7b1ae0f..eee2e0cb204ae8888bf2aa14f570df456b3705cc 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:40:26
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:45:54
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/00.gzip/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/00.gzip/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 3846f97fb56dfae3ae6718efdc6cccb31dbfb499..4b6f6b4047c803c2f1e70ed1fccd8b99d1ef4c66 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.796763                       # Nu
 sim_ticks                                796762926000                       # Number of ticks simulated
 final_tick                               796762926000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1450316                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1924652930                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219100                       # Number of bytes of host memory used
-host_seconds                                   413.98                       # Real time elapsed on the host
-sim_insts                                   600398281                       # Number of instructions simulated
+host_inst_rate                                1806630                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1907867                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2531848956                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221588                       # Number of bytes of host memory used
+host_seconds                                   314.70                       # Real time elapsed on the host
+sim_insts                                   568539343                       # Number of instructions simulated
+sim_ops                                     600398281                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5759488                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  39424                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3704704                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                   48                       # Nu
 system.cpu.numCycles                       1593525852                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        600398281                       # Number of instructions executed
+system.cpu.committedInsts                   568539343                       # Number of instructions committed
+system.cpu.committedOps                     600398281                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             533522639                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                     1993546                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs                570073892                       # To
 system.cpu.icache.sampled_refs                    643                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               886584.590980                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            577.728532                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.282094                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              570073892                       # number of ReadReq hits
-system.cpu.icache.demand_hits               570073892                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              570073892                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  643                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   643                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  643                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       34874000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        34874000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       34874000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          570074535                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           570074535                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          570074535                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54236.391913                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54236.391913                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54236.391913                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     577.728532                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.282094                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.282094                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    570073892                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       570073892                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     570073892                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        570073892                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    570073892                       # number of overall hits
+system.cpu.icache.overall_hits::total       570073892                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          643                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           643                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          643                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            643                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          643                       # number of overall misses
+system.cpu.icache.overall_misses::total           643                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34874000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34874000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34874000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34874000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34874000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34874000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    570074535                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    570074535                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    570074535                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    570074535                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    570074535                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    570074535                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54236.391913                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54236.391913                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54236.391913                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             643                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              643                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             643                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     32945000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     32945000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     32945000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51236.391913                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51236.391913                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          643                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          643                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          643                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          643                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          643                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          643                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     32945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     32945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32945000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     32945000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51236.391913                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51236.391913                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51236.391913                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 433468                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.222434                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                216774473                       # To
 system.cpu.dcache.sampled_refs                 437564                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 495.412038                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              537031000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.222434                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999566                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              147602036                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              69169783                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             1327                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              1327                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               216771819                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              216771819                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               189816                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              247748                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                437564                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               437564                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     3956274000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    5923414000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency      9879688000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     9879688000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          147791852                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          69417531                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         1327                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          1327                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           217209383                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          217209383                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.001284                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.003569                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.002014                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002014                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 20842.679226                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23909.028529                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 22578.841038                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 22578.841038                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.222434                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999566                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999566                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    147602036                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       147602036                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     69169783                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       69169783                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         1327                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         1327                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         1327                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         1327                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     216771819                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        216771819                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    216771819                       # number of overall hits
+system.cpu.dcache.overall_hits::total       216771819                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       189816                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        189816                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       247748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       247748                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       437564                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         437564                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       437564                       # number of overall misses
+system.cpu.dcache.overall_misses::total        437564                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   3956274000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   3956274000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5923414000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5923414000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   9879688000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   9879688000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   9879688000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   9879688000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    147791852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    147791852                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     69417531                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         1327                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         1327                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         1327                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         1327                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    217209383                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    217209383                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    217209383                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    217209383                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001284                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003569                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002014                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002014                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20842.679226                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23909.028529                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22578.841038                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22578.841038                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   392392                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          189816                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         247748                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           437564                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          437564                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3386826000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5180170000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   8566996000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   8566996000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001284                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003569                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002014                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002014                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17842.679226                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20909.028529                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19578.841038                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       392392                       # number of writebacks
+system.cpu.dcache.writebacks::total            392392                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       189816                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       189816                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       247748                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       247748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       437564                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       437564                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       437564                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       437564                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3386826000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3386826000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5180170000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5180170000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8566996000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8566996000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8566996000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   8566996000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001284                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003569                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002014                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002014                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17842.679226                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20909.028529                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19578.841038                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19578.841038                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 71804                       # number of replacements
 system.cpu.l2cache.tagsinuse             17904.014680                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                  411836                       # To
 system.cpu.l2cache.sampled_refs                 87286                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.718237                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1762.179345                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16141.835335                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.053777                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.492610                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                158918                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              392392                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              189297                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 348215                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                348215                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               31541                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58451                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                89992                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               89992                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1640132000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3039452000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4679584000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4679584000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            190459                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          392392                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          247748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             438207                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            438207                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.165605                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.235929                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.205364                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.205364                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16141.835335                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     24.672100                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1737.507245                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.492610                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000753                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.053025                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.546387                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           27                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       158891                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         158918                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       392392                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       392392                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       189297                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       189297                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           27                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       348188                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          348215                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           27                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       348188                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         348215                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          616                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        30925                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31541                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        58451                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        58451                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          616                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        89376                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         89992                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          616                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        89376                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        89992                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32032000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1608100000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1640132000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3039452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3039452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32032000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4647552000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4679584000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32032000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4647552000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4679584000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          643                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       189816                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       190459                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       392392                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       392392                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       247748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       247748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          643                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       437564                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       438207                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          643                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       437564                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       438207                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.958009                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.162921                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.235929                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.958009                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.204258                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.958009                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.204258                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   57886                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          31541                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58451                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           89992                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          89992                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1261640000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2338040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3599680000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3599680000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165605                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235929                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.205364                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.205364                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        57886                       # number of writebacks
+system.cpu.l2cache.writebacks::total            57886                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          616                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30925                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31541                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        58451                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        58451                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          616                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        89376                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        89992                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        89376                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        89992                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24640000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1237000000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1261640000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2338040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2338040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24640000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3575040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3599680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24640000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3575040000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3599680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.958009                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.162921                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.235929                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.958009                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.204258                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.958009                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.204258                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index dcba73ec2bddb2a301855fc5a1f268f478f0a553..5612e55e72f6081f97f1783b13a41121289409eb 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
+cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
 egid=100
 env=
 errout=cerr
index a835cbd7980303af30e09912e9cf425a0e69183d..337dcecf79e1805cc61136b6a44916e8702d84b9 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:17:40
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:12
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/o3-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index e4d9fca0778a8c8ed5710fa896f83adca759e5da..3c7a99cbd81c73a42b0a8cda5178c7096d2ff132 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.408816                       # Nu
 sim_ticks                                408816360000                       # Number of ticks simulated
 final_tick                               408816360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 175830                       # Simulator instruction rate (inst/s)
-host_tick_rate                               51139829                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215728                       # Number of bytes of host memory used
-host_seconds                                  7994.10                       # Real time elapsed on the host
-sim_insts                                  1405604152                       # Number of instructions simulated
+host_inst_rate                                 218783                       # Simulator instruction rate (inst/s)
+host_op_rate                                   219472                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63832966                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214000                       # Number of bytes of host memory used
+host_seconds                                  6404.47                       # Real time elapsed on the host
+sim_insts                                  1401188958                       # Number of instructions simulated
+sim_ops                                    1405604152                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     6021376                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  81792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3792448                       # Number of bytes written to this memory
@@ -237,7 +239,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.812578                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.959383                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1489523295                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts     1485108101                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1489523295                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       179255835                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         2243671                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           5438120                       # The number of times a branch was mispredicted
@@ -258,7 +261,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    791834306                       # Number of insts commited each cycle
-system.cpu.commit.count                    1489523295                       # Number of instructions committed
+system.cpu.commit.committedInsts           1485108101                       # Number of instructions committed
+system.cpu.commit.committedOps             1489523295                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      569360986                       # Number of memory references committed
 system.cpu.commit.loads                     402512844                       # Number of loads committed
@@ -273,12 +277,13 @@ system.cpu.rob.rob_reads                   2392297077                       # Th
 system.cpu.rob.rob_writes                  3363039880                       # The number of ROB writes
 system.cpu.timesIdled                           11286                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          357787                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1405604152                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1405604152                       # Number of Instructions Simulated
-system.cpu.cpi                               0.581695                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.581695                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.719114                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.719114                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                  1401188958                       # Number of Instructions Simulated
+system.cpu.committedOps                    1405604152                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total            1401188958                       # Number of Instructions Simulated
+system.cpu.cpi                               0.583528                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.583528                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.713714                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.713714                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               2016058791                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1303867666                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                  16986540                       # number of floating regfile reads
@@ -291,26 +296,39 @@ system.cpu.icache.total_refs                170772098                       # To
 system.cpu.icache.sampled_refs                   1298                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               131565.560863                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1031.400456                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.503614                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              170772098                       # number of ReadReq hits
-system.cpu.icache.demand_hits               170772098                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              170772098                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1798                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1798                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1798                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       62741500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        62741500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       62741500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          170773896                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           170773896                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          170773896                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000011                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000011                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000011                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34895.161290                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34895.161290                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34895.161290                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1031.400456                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.503614                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.503614                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    170772098                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       170772098                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     170772098                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        170772098                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    170772098                       # number of overall hits
+system.cpu.icache.overall_hits::total       170772098                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1798                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1798                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1798                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1798                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1798                       # number of overall misses
+system.cpu.icache.overall_misses::total          1798                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     62741500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     62741500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     62741500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     62741500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     62741500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     62741500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    170773896                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    170773896                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    170773896                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    170773896                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    170773896                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    170773896                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000011                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000011                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000011                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34895.161290                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34895.161290                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34895.161290                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -319,27 +337,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               499                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                499                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               499                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            1299                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             1299                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            1299                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     45206000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     45206000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     45206000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000008                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000008                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34800.615858                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34800.615858                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34800.615858                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          499                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          499                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          499                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          499                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          499                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          499                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1299                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1299                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1299                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1299                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1299                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1299                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     45206000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     45206000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     45206000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     45206000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     45206000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     45206000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000008                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34800.615858                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34800.615858                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34800.615858                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 475353                       # number of replacements
 system.cpu.dcache.tagsinuse               4095.165283                       # Cycle average of tags in use
@@ -347,38 +368,59 @@ system.cpu.dcache.total_refs                385593109                       # To
 system.cpu.dcache.sampled_refs                 479449                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 804.242180                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              131001000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.165283                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999796                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              220654856                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             164936934                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
-system.cpu.dcache.demand_hits               385591790                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              385591790                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               815916                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1909882                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
-system.cpu.dcache.demand_misses               2725798                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2725798                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    11966603000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   29861651909                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency         268000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency     41828254909                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    41828254909                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          221470772                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           388317588                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          388317588                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.003684                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.011447                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.007020                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.007020                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14666.464440                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 15635.338680                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency 38285.714286                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15345.324528                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15345.324528                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4095.165283                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999796                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999796                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    220654856                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       220654856                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    164936934                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      164936934                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data         1319                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total            1319                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data     385591790                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        385591790                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    385591790                       # number of overall hits
+system.cpu.dcache.overall_hits::total       385591790                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       815916                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        815916                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1909882                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1909882                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data            7                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total             7                       # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data      2725798                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2725798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2725798                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2725798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  11966603000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  11966603000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  29861651909                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  29861651909                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       268000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       268000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  41828254909                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  41828254909                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  41828254909                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  41828254909                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    221470772                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    221470772                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data         1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total         1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    388317588                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    388317588                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    388317588                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    388317588                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003684                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.011447                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.007020                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.007020                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14666.464440                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 15635.338680                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data 38285.714286                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15345.324528                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15345.324528                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs        28000                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets         3000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                13                       # number of cycles access was blocked
@@ -387,36 +429,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  2153.846154
 system.cpu.dcache.avg_blocked_cycles::no_targets         3000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   426654                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            603731                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1642625                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            2246356                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           2246356                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          212185                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         267257                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           479442                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          479442                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1589383500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3625603341                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency       247000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   5214986841                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   5214986841                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000958                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001602                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001235                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001235                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7490.555412                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 13565.980839                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency 35285.714286                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 10877.200665                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 10877.200665                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       426654                       # number of writebacks
+system.cpu.dcache.writebacks::total            426654                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       603731                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       603731                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1642625                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1642625                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      2246356                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      2246356                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      2246356                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      2246356                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       212185                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       212185                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       267257                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       267257                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data            7                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total            7                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       479442                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       479442                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       479442                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       479442                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1589383500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1589383500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3625603341                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3625603341                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       247000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total       247000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   5214986841                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   5214986841                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   5214986841                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   5214986841                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000958                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001602                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001235                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001235                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7490.555412                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 13565.980839                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data 35285.714286                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10877.200665                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10877.200665                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 75859                       # number of replacements
 system.cpu.l2cache.tagsinuse             17814.801426                       # Cycle average of tags in use
@@ -424,36 +476,75 @@ system.cpu.l2cache.total_refs                  464590                       # To
 system.cpu.l2cache.sampled_refs                 91380                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  5.084154                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2079.678027                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15735.123399                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.063467                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.480198                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                179822                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              426654                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              206842                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 386664                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                386664                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               33662                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             60422                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                94084                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               94084                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1145731000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2079178500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3224909500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3224909500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            213484                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          426654                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          267264                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             480748                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            480748                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.157679                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.226076                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.195703                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.195703                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34036.331769                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34410.951309                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34276.917435                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34276.917435                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15735.123399                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     94.212469                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1985.465558                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.480198                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.002875                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.060592                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.543665                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       179801                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         179822                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       426654                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       426654                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       206842                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       206842                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           21                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       386643                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          386664                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           21                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       386643                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         386664                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1278                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        32384                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        33662                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        60422                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        60422                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1278                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        92806                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         94084                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1278                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        92806                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        94084                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     43747500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1101983500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1145731000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2079178500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2079178500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     43747500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3181162000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3224909500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     43747500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3181162000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3224909500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1299                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       212185                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       213484                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       426654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       426654                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       267264                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       267264                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1299                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       479449                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       480748                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1299                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       479449                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       480748                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.983834                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.152622                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.226076                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.983834                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.193568                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.983834                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.193568                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34231.220657                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34028.640687                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34410.951309                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34231.220657                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34277.546710                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34231.220657                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34277.546710                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -462,30 +553,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59257                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          33662                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        60422                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           94084                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          94084                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1043686000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1892150500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2935836500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2935836500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157679                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.226076                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.195703                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.195703                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.871962                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.588693                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31204.418392                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31204.418392                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        59257                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59257                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1278                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        32384                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        33662                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        60422                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        60422                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1278                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        92806                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        94084                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1278                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        92806                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        94084                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     39610000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1004076000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1043686000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1892150500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1892150500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     39610000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2896226500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2935836500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     39610000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2896226500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2935836500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.983834                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.152622                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.226076                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.983834                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.193568                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.983834                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.193568                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30993.740219                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31005.311265                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.588693                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30993.740219                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31207.319570                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30993.740219                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31207.319570                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b52495d06b696f97fd490796f1662e22cf4230de..12208533c5b26069d17113a9cb7806d96840edf7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
index d2df5cc0947cfc85b0b9265c2849f2b52934c3b6..dd6f18f54b13af0546cf37f6d6f49f71ed3a8981 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:18:03
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:17
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index afe2bae4fbd47a3fbb2b091a9c89fc2e1161a640..317e7593899d9168645026e596478fb1b55a21fe 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.744764                       # Nu
 sim_ticks                                744764119000                       # Number of ticks simulated
 final_tick                               744764119000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3773289                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1886650577                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205844                       # Number of bytes of host memory used
-host_seconds                                   394.75                       # Real time elapsed on the host
-sim_insts                                  1489523295                       # Number of instructions simulated
+host_inst_rate                                4631105                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4644873                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2322443893                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 203508                       # Number of bytes of host memory used
+host_seconds                                   320.68                       # Real time elapsed on the host
+sim_insts                                  1485108101                       # Number of instructions simulated
+sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  7326269637                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             5940452044                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                614672063                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   49                       # Nu
 system.cpu.numCycles                       1489528239                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1489523295                       # Number of instructions executed
+system.cpu.committedInsts                  1485108101                       # Number of instructions committed
+system.cpu.committedOps                    1489523295                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
 system.cpu.num_func_calls                     1207835                       # number of times a function call or return occured
index ea98a23a14c944e7a06cf862a9d13400d982257f..8f915a65c6c2fc61046abbf9cf3e9a77be9ba263 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
index b26fb3f410876bbb092a57e251134c295c5342b6..31dd55bac6fc9bc0690ea0ced1be872bd21a5305 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:19:05
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:19
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/00.gzip/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/00.gzip/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 05931292660a073c9cbab5a679a7756b6970c5ad..91253ef899405636a22306570a2d27baacf20ce7 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.064259                       # Nu
 sim_ticks                                2064258667000                       # Number of ticks simulated
 final_tick                               2064258667000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1766930                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2448703239                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214556                       # Number of bytes of host memory used
-host_seconds                                   843.00                       # Real time elapsed on the host
-sim_insts                                  1489523295                       # Number of instructions simulated
+host_inst_rate                                2132645                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2138986                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2964317062                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212372                       # Number of bytes of host memory used
+host_seconds                                   696.37                       # Real time elapsed on the host
+sim_insts                                  1485108101                       # Number of instructions simulated
+sim_ops                                    1489523295                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5909952                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  70592                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3778240                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   49                       # Nu
 system.cpu.numCycles                       4128517334                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1489523295                       # Number of instructions executed
+system.cpu.committedInsts                  1485108101                       # Number of instructions committed
+system.cpu.committedOps                    1489523295                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1319481298                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                8454127                       # Number of float alu accesses
 system.cpu.num_func_calls                     1207835                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs               1485111905                       # To
 system.cpu.icache.sampled_refs                   1107                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               1341564.503162                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            906.450625                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.442603                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1485111905                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1485111905                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1485111905                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1107                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1107                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1107                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       61824000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        61824000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       61824000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1485113012                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1485113012                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1485113012                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55848.238482                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55848.238482                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55848.238482                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     906.450625                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.442603                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.442603                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1485111905                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1485111905                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1485111905                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1485111905                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1485111905                       # number of overall hits
+system.cpu.icache.overall_hits::total      1485111905                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1107                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1107                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1107                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1107                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1107                       # number of overall misses
+system.cpu.icache.overall_misses::total          1107                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     61824000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     61824000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     61824000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     61824000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     61824000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     61824000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1485113012                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1485113012                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1485113012                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1485113012                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1485113012                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1485113012                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55848.238482                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55848.238482                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55848.238482                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            1107                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             1107                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            1107                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     58503000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     58503000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     58503000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52848.238482                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52848.238482                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1107                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1107                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1107                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1107                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1107                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1107                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     58503000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     58503000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     58503000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     58503000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     58503000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     58503000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52848.238482                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52848.238482                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52848.238482                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 449125                       # number of replacements
 system.cpu.dcache.tagsinuse               4095.226955                       # Cycle average of tags in use
@@ -102,38 +116,59 @@ system.cpu.dcache.total_refs                568907765                       # To
 system.cpu.dcache.sampled_refs                 453221                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                1255.254644                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              566994000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.226955                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999811                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              402319358                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             166587088                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                   1319                       # number of SwapReq hits
-system.cpu.dcache.demand_hits               568906446                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              568906446                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               193486                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              259728                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses                    7                       # number of SwapReq misses
-system.cpu.dcache.demand_misses                453214                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               453214                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     4019834000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    6156948000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency         392000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency     10176782000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    10176782000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          402512844                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         166846816                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses               1326                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           569359660                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          569359660                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000481                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.001557                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate          0.005279                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.000796                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000796                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 20775.839079                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23705.368693                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 22454.694692                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 22454.694692                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4095.226955                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999811                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999811                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    402319358                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       402319358                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    166587088                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      166587088                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data         1319                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total            1319                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data     568906446                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        568906446                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    568906446                       # number of overall hits
+system.cpu.dcache.overall_hits::total       568906446                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       193486                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        193486                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       259728                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       259728                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data            7                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total             7                       # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data       453214                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         453214                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       453214                       # number of overall misses
+system.cpu.dcache.overall_misses::total        453214                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4019834000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4019834000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   6156948000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   6156948000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       392000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       392000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  10176782000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  10176782000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  10176782000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  10176782000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    402512844                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    402512844                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    166846816                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data         1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total         1326                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    569359660                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    569359660                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    569359660                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    569359660                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000481                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001557                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.005279                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000796                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000796                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20775.839079                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23705.368693                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        56000                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22454.694692                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22454.694692                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   407009                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          193486                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         259728                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses               7                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           453214                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          453214                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3439376000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5377764000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency       371000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   8817140000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   8817140000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000481                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001557                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.005279                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000796                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000796                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17775.839079                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20705.368693                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19454.694692                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       407009                       # number of writebacks
+system.cpu.dcache.writebacks::total            407009                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       193486                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       193486                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       259728                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       259728                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data            7                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total            7                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       453214                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       453214                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       453214                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       453214                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3439376000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3439376000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5377764000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5377764000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       371000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total       371000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8817140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8817140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8817140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   8817140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000481                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001557                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.005279                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000796                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000796                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17775.839079                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20705.368693                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        53000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19454.694692                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19454.694692                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 74112                       # number of replacements
 system.cpu.l2cache.tagsinuse             17723.305524                       # Cycle average of tags in use
@@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs                  427085                       # To
 system.cpu.l2cache.sampled_refs                 89611                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.765989                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1873.919591                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15849.385934                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.057187                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.483685                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                162275                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              407009                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              199710                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 361985                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                361985                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32318                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             60025                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                92343                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               92343                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1680536000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3121300000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4801836000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4801836000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            194593                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          407009                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          259735                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             454328                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            454328                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.166080                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.231101                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.203252                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.203252                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15849.385934                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     72.801131                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1801.118460                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.483685                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.002222                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.054966                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.540872                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            4                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       162271                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         162275                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       407009                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       407009                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       199710                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       199710                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            4                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       361981                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          361985                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            4                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       361981                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         361985                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1103                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        31215                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32318                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        60025                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        60025                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1103                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        91240                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         92343                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1103                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        91240                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        92343                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     57356000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1623180000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1680536000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3121300000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3121300000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     57356000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4744480000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4801836000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     57356000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4744480000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4801836000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1107                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       193486                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       194593                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       407009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       407009                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       259735                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       259735                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1107                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       453221                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       454328                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1107                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       453221                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       454328                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996387                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.161330                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.231101                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996387                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.201315                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996387                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.201315                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   59035                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32318                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        60025                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           92343                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          92343                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1292720000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2401000000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3693720000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3693720000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.166080                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.231101                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.203252                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.203252                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        59035                       # number of writebacks
+system.cpu.l2cache.writebacks::total            59035                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1103                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        31215                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32318                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        60025                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        60025                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1103                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        91240                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        92343                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1103                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        91240                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        92343                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     44120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1248600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1292720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2401000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2401000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     44120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3649600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3693720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     44120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3649600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3693720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996387                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.161330                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.231101                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996387                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.201315                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996387                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.201315                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 3b035cefe05e8da8ac0de41b0209d82451b7eca4..5b4602be41e40c4511029bf935029693a90bc915 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -442,20 +435,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -494,20 +480,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -531,12 +510,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/gzip
+executable=/dist/m5/cpu2000/binaries/x86/linux/gzip
 gid=100
 input=cin
 max_stack_size=67108864
index 774f2864e11e2b3ed96c951f4037da951c019ef6..dd2c66002bbc53fce4778afb4793c8cdcafd9f4d 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  9 2012 12:45:55
-gem5 started Feb  9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/00.gzip/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:08:06
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 1e49192440cccd01d5f2cac4c4839d5427aeda29..db3272b032b32b609e2b00111ca420906abbd77b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.586835                       # Nu
 sim_ticks                                586834596000                       # Number of ticks simulated
 final_tick                               586834596000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  99458                       # Simulator instruction rate (inst/s)
-host_tick_rate                               35994653                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 253740                       # Number of bytes of host memory used
-host_seconds                                 16303.38                       # Real time elapsed on the host
-sim_insts                                  1621493982                       # Number of instructions simulated
+host_inst_rate                                 106927                       # Simulator instruction rate (inst/s)
+host_op_rate                                   197018                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71302744                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220908                       # Number of bytes of host memory used
+host_seconds                                  8230.18                       # Real time elapsed on the host
+sim_insts                                   880025312                       # Number of instructions simulated
+sim_ops                                    1621493982                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5879616                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  57024                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3743488                       # Number of bytes written to this memory
@@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.495458                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.672132                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1621493982                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      880025312                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1621493982                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       350742946                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              50                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           7896364                       # The number of times a branch was mispredicted
@@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total   1125303290                       # Number of insts commited each cycle
-system.cpu.commit.count                    1621493982                       # Number of instructions committed
+system.cpu.commit.committedInsts            880025312                       # Number of instructions committed
+system.cpu.commit.committedOps             1621493982                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      607228182                       # Number of memory references committed
 system.cpu.commit.loads                     419042125                       # Number of loads committed
@@ -272,12 +276,13 @@ system.cpu.rob.rob_reads                   3082456564                       # Th
 system.cpu.rob.rob_writes                  3992764754                       # The number of ROB writes
 system.cpu.timesIdled                           21723                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           94408                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1621493982                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1621493982                       # Number of Instructions Simulated
-system.cpu.cpi                               0.723820                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.723820                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.381560                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.381560                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   880025312                       # Number of Instructions Simulated
+system.cpu.committedOps                    1621493982                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             880025312                       # Number of Instructions Simulated
+system.cpu.cpi                               1.333677                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.333677                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.749807                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.749807                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               3268959976                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1746565098                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        12                       # number of floating regfile reads
@@ -288,26 +293,39 @@ system.cpu.icache.total_refs                136532946                       # To
 system.cpu.icache.sampled_refs                    894                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               152721.416107                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            807.278486                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.394179                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              136532946                       # number of ReadReq hits
-system.cpu.icache.demand_hits               136532946                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              136532946                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1228                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1228                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1228                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       43195500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        43195500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       43195500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          136534174                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           136534174                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          136534174                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35175.488599                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35175.488599                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35175.488599                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     807.278486                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.394179                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.394179                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    136532946                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       136532946                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     136532946                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        136532946                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    136532946                       # number of overall hits
+system.cpu.icache.overall_hits::total       136532946                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1228                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1228                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1228                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1228                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1228                       # number of overall misses
+system.cpu.icache.overall_misses::total          1228                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     43195500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     43195500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     43195500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     43195500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     43195500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     43195500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    136534174                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    136534174                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    136534174                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    136534174                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    136534174                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    136534174                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000009                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000009                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35175.488599                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35175.488599                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35175.488599                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -316,27 +334,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               334                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                334                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               334                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             894                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              894                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             894                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     31569000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     31569000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     31569000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000007                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000007                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000007                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35312.080537                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35312.080537                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35312.080537                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          334                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          334                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          334                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          334                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          334                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          334                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          894                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          894                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          894                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          894                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          894                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          894                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     31569000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     31569000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     31569000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     31569000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     31569000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     31569000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000007                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35312.080537                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35312.080537                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35312.080537                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 459037                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.269422                       # Cycle average of tags in use
@@ -344,32 +365,49 @@ system.cpu.dcache.total_refs                430357004                       # To
 system.cpu.dcache.sampled_refs                 463133                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 929.229841                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              414463000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.269422                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999577                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              242420503                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             187936501                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               430357004                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              430357004                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               217102                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              249556                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                466658                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               466658                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     2192767500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3219007000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency      5411774500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     5411774500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          242637605                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           430823662                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          430823662                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000895                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.001326                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.001083                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.001083                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 10100.171809                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 12898.936511                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 11596.875013                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 11596.875013                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.269422                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999577                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999577                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    242420503                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       242420503                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    187936501                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      187936501                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     430357004                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        430357004                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    430357004                       # number of overall hits
+system.cpu.dcache.overall_hits::total       430357004                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       217102                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        217102                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       249556                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       249556                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       466658                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         466658                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       466658                       # number of overall misses
+system.cpu.dcache.overall_misses::total        466658                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2192767500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2192767500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3219007000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3219007000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   5411774500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   5411774500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   5411774500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   5411774500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    242637605                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    242637605                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    430823662                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    430823662                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    430823662                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    430823662                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000895                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001326                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.001083                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.001083                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 10100.171809                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 12898.936511                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 11596.875013                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 11596.875013                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -378,32 +416,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   409999                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              3488                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits               35                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               3523                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              3523                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          213614                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         249521                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           463135                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          463135                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1523998500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2469759000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   3993757500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   3993757500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000880                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001326                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001075                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001075                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7134.356831                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  9898.000569                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8623.311777                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8623.311777                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       409999                       # number of writebacks
+system.cpu.dcache.writebacks::total            409999                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         3488                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         3488                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           35                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           35                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         3523                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         3523                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         3523                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         3523                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       213614                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       213614                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       249521                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       249521                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       463135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       463135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       463135                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       463135                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1523998500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1523998500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2469759000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2469759000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   3993757500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   3993757500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   3993757500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   3993757500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000880                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001326                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001075                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001075                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7134.356831                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9898.000569                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8623.311777                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8623.311777                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 73601                       # number of replacements
 system.cpu.l2cache.tagsinuse             17971.586292                       # Cycle average of tags in use
@@ -411,36 +457,75 @@ system.cpu.l2cache.total_refs                  452847                       # To
 system.cpu.l2cache.sampled_refs                 89223                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  5.075451                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1981.498209                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15990.088083                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.060471                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.487979                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                181345                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              409999                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              190815                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 372160                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                372160                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               33162                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58707                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                91869                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               91869                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1129684500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2008512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3138196500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3138196500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            214507                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          409999                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          249522                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             464029                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            464029                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.154596                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.235278                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.197981                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.197981                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34065.632350                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34212.478921                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34159.471639                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34159.471639                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15990.088083                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     59.987883                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1921.510326                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.487979                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001831                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.058640                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.548449                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       181342                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         181345                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       409999                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       409999                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       190815                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       190815                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       372157                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          372160                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       372157                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         372160                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          891                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        32271                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        33162                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        58707                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        58707                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          891                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        90978                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         91869                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          891                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        90978                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        91869                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30543500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1099141000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1129684500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2008512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2008512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     30543500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3107653000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3138196500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     30543500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3107653000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3138196500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          894                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       213613                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       214507                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       409999                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       409999                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       249522                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       249522                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          894                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       463135                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       464029                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          894                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       463135                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       464029                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996644                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.151072                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.235278                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996644                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.196439                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996644                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.196439                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34280.022447                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34059.713055                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34212.478921                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34280.022447                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34158.291015                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34280.022447                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34158.291015                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -449,30 +534,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   58492                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          33162                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58707                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           91869                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          91869                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1028173500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1819949000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   2848122500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   2848122500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.154596                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.235278                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.197981                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.197981                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31004.568482                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.545080                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31001.997409                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31001.997409                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        58492                       # number of writebacks
+system.cpu.l2cache.writebacks::total            58492                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          891                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        32271                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        33162                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        58707                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        58707                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          891                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        90978                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        91869                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          891                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        90978                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        91869                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     27674500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1000499000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1028173500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1819949000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1819949000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     27674500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   2820448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   2848122500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     27674500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   2820448000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   2848122500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996644                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.151072                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.235278                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996644                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.196439                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996644                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.196439                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31060.044893                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31003.036782                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.545080                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31060.044893                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31001.428917                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31060.044893                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31001.428917                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 393d713652ee98af1e7cdbe695766a04f5a5ad0d..6904b6f42fd9ce53ad9f9a8e3ece6f965cfcf6cc 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +97,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +121,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index 3da3c7641f01d2eec7af21e21154f8a8260e7270..061803200ac3802682876dd1ac51b88c265fc1b9 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:33:19
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:08:56
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 3a54bb2c87f0e9fa462ab7523d02b3c49fff18f0..2bdb7b9df3984f88ab3a055a34088e3d0f019793 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.963993                       # Nu
 sim_ticks                                963992704000                       # Number of ticks simulated
 final_tick                               963992704000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2202720                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1309536712                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204800                       # Number of bytes of host memory used
-host_seconds                                   736.13                       # Real time elapsed on the host
-sim_insts                                  1621493983                       # Number of instructions simulated
+host_inst_rate                                1632386                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3007760                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1788140018                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210284                       # Number of bytes of host memory used
+host_seconds                                   539.10                       # Real time elapsed on the host
+sim_insts                                   880025313                       # Number of instructions simulated
+sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 11334586825                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             9492133912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                864451000                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   48                       # Nu
 system.cpu.numCycles                       1927985409                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1621493983                       # Number of instructions executed
+system.cpu.committedInsts                   880025313                       # Number of instructions committed
+system.cpu.committedOps                    1621493983                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index f841786ecdc67f1e83a7b3ccda109d0ea9ca6597..9097a5047aa9b22fa4836850306edf6e71227e8d 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +104,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +118,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +149,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +171,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=gzip input.log 1
-cwd=build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -191,7 +203,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index c3d33da65242d29d28ca04c6346cc3f25082dcdf..527d3d1729993a6fb6e577152a0a00e46eff93e3 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:37:10
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:11:10
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/00.gzip/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/00.gzip/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 8e512b7b9d8a381e3955db8d39513d2d3ccbf52e..308cb734c20bd709b68050777e667670afa1e611 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.803259                       # Nu
 sim_ticks                                1803258587000                       # Number of ticks simulated
 final_tick                               1803258587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1279975                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1423455894                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213784                       # Number of bytes of host memory used
-host_seconds                                  1266.82                       # Real time elapsed on the host
-sim_insts                                  1621493983                       # Number of instructions simulated
+host_inst_rate                                 972144                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1791227                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1992018099                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219200                       # Number of bytes of host memory used
+host_seconds                                   905.24                       # Real time elapsed on the host
+sim_insts                                   880025313                       # Number of instructions simulated
+sim_ops                                    1621493983                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     5725952                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  46208                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  3712448                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   48                       # Nu
 system.cpu.numCycles                       3606517174                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1621493983                       # Number of instructions executed
+system.cpu.committedInsts                   880025313                       # Number of instructions committed
+system.cpu.committedOps                    1621493983                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1621354493                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs               1186516018                       # To
 system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               1643373.986150                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            660.186297                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.322357                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1186516018                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1186516018                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1186516018                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  722                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   722                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  722                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       40432000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        40432000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       40432000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1186516740                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1186516740                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1186516740                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000001                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000001                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000001                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     660.186297                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.322357                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.322357                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1186516018                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1186516018                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1186516018                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1186516018                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1186516018                       # number of overall hits
+system.cpu.icache.overall_hits::total      1186516018                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           722                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            722                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          722                       # number of overall misses
+system.cpu.icache.overall_misses::total           722                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     40432000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     40432000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     40432000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     40432000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     40432000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     40432000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1186516740                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1186516740                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1186516740                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1186516740                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1186516740                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1186516740                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000001                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000001                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000001                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             722                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              722                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             722                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     38266000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     38266000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     38266000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000001                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000001                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000001                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          722                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          722                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          722                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          722                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     38266000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     38266000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     38266000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     38266000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     38266000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     38266000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000001                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 437952                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.896939                       # Cycle average of tags in use
@@ -102,32 +116,49 @@ system.cpu.dcache.total_refs                606786134                       # To
 system.cpu.dcache.sampled_refs                 442048                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                1372.670239                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              778540000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.896939                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999731                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              418844799                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             187941335                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               606786134                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              606786134                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               197326                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              244722                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                442048                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               442048                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     4043270000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    5872734000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency      9916004000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     9916004000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          419042125                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         188186057                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           607228182                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          607228182                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000471                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.001300                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000728                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000728                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 20490.305383                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 23997.572756                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 22431.962140                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 22431.962140                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.896939                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999731                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999731                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    418844799                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       418844799                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    187941335                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      187941335                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     606786134                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        606786134                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    606786134                       # number of overall hits
+system.cpu.dcache.overall_hits::total       606786134                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       197326                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        197326                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       244722                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       244722                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       442048                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         442048                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       442048                       # number of overall misses
+system.cpu.dcache.overall_misses::total        442048                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4043270000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4043270000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5872734000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5872734000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   9916004000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   9916004000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   9916004000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   9916004000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    419042125                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    419042125                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    188186057                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    607228182                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    607228182                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    607228182                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    607228182                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000471                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001300                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000728                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000728                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 20490.305383                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 23997.572756                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22431.962140                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22431.962140                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   396372                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          197326                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         244722                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           442048                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          442048                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3451292000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5138568000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   8589860000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   8589860000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000471                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.001300                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000728                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000728                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 17490.305383                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20997.572756                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19431.962140                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       396372                       # number of writebacks
+system.cpu.dcache.writebacks::total            396372                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       197326                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       197326                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       244722                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       244722                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       442048                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       442048                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       442048                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       442048                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   3451292000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   3451292000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5138568000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5138568000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   8589860000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   8589860000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   8589860000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   8589860000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000471                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.001300                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000728                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000728                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 17490.305383                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20997.572756                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19431.962140                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19431.962140                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 71208                       # number of replacements
 system.cpu.l2cache.tagsinuse             18056.923092                       # Cycle average of tags in use
@@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs                  423014                       # To
 system.cpu.l2cache.sampled_refs                 86793                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  4.873826                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1869.199731                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16187.723361                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.057043                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.494010                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                166833                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              396372                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              186469                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 353302                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                353302                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               31215                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             58253                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                89468                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               89468                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1623180000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3029156000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4652336000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4652336000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            198048                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          396372                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          244722                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             442770                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            442770                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.157613                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.238037                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.202064                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.202064                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16187.723361                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     48.180025                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1821.019706                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.494010                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001470                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.055573                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.551054                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data       166833                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         166833                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       396372                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       396372                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       186469                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       186469                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data       353302                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          353302                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data       353302                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         353302                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          722                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        30493                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31215                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        58253                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        58253                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          722                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        88746                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         89468                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          722                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        88746                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        89468                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     37544000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1585636000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1623180000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3029156000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3029156000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     37544000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4614792000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4652336000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     37544000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4614792000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4652336000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          722                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       197326                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       198048                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       396372                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       396372                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       244722                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       244722                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          722                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       442048                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       442770                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          722                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       442048                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       442770                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.154531                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.238037                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200761                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200761                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   58007                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          31215                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        58253                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           89468                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          89468                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1248600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2330120000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3578720000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3578720000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.157613                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.238037                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.202064                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.202064                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        58007                       # number of writebacks
+system.cpu.l2cache.writebacks::total            58007                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          722                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30493                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31215                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        58253                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        58253                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          722                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        88746                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        89468                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          722                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        88746                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        89468                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     28880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1219720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1248600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2330120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2330120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     28880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3549840000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3578720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     28880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3549840000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3578720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.154531                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.238037                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200761                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200761                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index cbe07964798157870d3f4f07ce976517e4baacd4..ae17312a7b482be848a328a553b3b2f65b700088 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,14 +508,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
index 3ae44ae93d57e3b3c14b8e94c509319a94eddec0..bc658a4d7528443be8e7edc039176e8fbb3fa82b 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:46:15
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 833e2ce53fea3b3ff5de9ee96d89ea15d4def1f0..0264f97d4e9cd0d301f33dd70883db2ce4b5cd4e 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.033081                       # Nu
 sim_ticks                                 33080570000                       # Number of ticks simulated
 final_tick                                33080570000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  45520                       # Simulator instruction rate (inst/s)
-host_tick_rate                               16502276                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388968                       # Number of bytes of host memory used
-host_seconds                                  2004.61                       # Real time elapsed on the host
-sim_insts                                    91249885                       # Number of instructions simulated
+host_inst_rate                                 183696                       # Simulator instruction rate (inst/s)
+host_op_rate                                   185015                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               67072888                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 356156                       # Number of bytes of host memory used
+host_seconds                                   493.20                       # Real time elapsed on the host
+sim_insts                                    90599331                       # Number of instructions simulated
+sim_ops                                      91249885                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      997440                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  44864                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
@@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.549573                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.621804                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts       91262494                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts       90611940                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         91262494                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        26696996                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls          554844                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           1392644                       # The number of times a branch was mispredicted
@@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total     62124345                       # Number of insts commited each cycle
-system.cpu.commit.count                      91262494                       # Number of instructions committed
+system.cpu.commit.committedInsts             90611940                       # Number of instructions committed
+system.cpu.commit.committedOps               91262494                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       27322621                       # Number of memory references committed
 system.cpu.commit.loads                      22575872                       # Number of loads committed
@@ -318,12 +322,13 @@ system.cpu.rob.rob_reads                    175546960                       # Th
 system.cpu.rob.rob_writes                   239939856                       # The number of ROB writes
 system.cpu.timesIdled                            1543                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           29796                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                    91249885                       # Number of Instructions Simulated
-system.cpu.committedInsts_total              91249885                       # Number of Instructions Simulated
-system.cpu.cpi                               0.725055                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.725055                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.379207                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.379207                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                    90599331                       # Number of Instructions Simulated
+system.cpu.committedOps                      91249885                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              90599331                       # Number of Instructions Simulated
+system.cpu.cpi                               0.730261                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.730261                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.369374                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.369374                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                496902735                       # number of integer regfile reads
 system.cpu.int_regfile_writes               120936098                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       197                       # number of floating regfile reads
@@ -336,26 +341,39 @@ system.cpu.icache.total_refs                 14743811                       # To
 system.cpu.icache.sampled_refs                    722                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               20420.790859                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            611.587679                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.298627                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               14743811                       # number of ReadReq hits
-system.cpu.icache.demand_hits                14743811                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               14743811                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  916                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   916                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  916                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       32376000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        32376000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       32376000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           14744727                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            14744727                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           14744727                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000062                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000062                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000062                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35344.978166                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35344.978166                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35344.978166                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     611.587679                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.298627                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.298627                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     14743811                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        14743811                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      14743811                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         14743811                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     14743811                       # number of overall hits
+system.cpu.icache.overall_hits::total        14743811                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          916                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           916                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          916                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            916                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          916                       # number of overall misses
+system.cpu.icache.overall_misses::total           916                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32376000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32376000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32376000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32376000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32376000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32376000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     14744727                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     14744727                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     14744727                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     14744727                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     14744727                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     14744727                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000062                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000062                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000062                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35344.978166                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35344.978166                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35344.978166                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               194                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                194                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               194                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             722                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              722                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             722                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     24887000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     24887000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     24887000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000049                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000049                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34469.529086                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34469.529086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34469.529086                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          194                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          194                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          194                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          194                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          194                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          194                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          722                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          722                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          722                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          722                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          722                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     24887000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     24887000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     24887000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     24887000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     24887000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     24887000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000049                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000049                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000049                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34469.529086                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34469.529086                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34469.529086                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 943456                       # number of replacements
 system.cpu.dcache.tagsinuse               3558.808733                       # Cycle average of tags in use
@@ -392,40 +413,63 @@ system.cpu.dcache.total_refs                 28819271                       # To
 system.cpu.dcache.sampled_refs                 947552                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  30.414448                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            12353041000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3558.808733                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.868850                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               24247440                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               4559242                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             6797                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              5792                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                28806682                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               28806682                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               989267                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              175739                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              7                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1165006                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1165006                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     5475545000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    4498707428                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       124500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency      9974252428                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     9974252428                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           25236707                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         6804                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          5792                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            29971688                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           29971688                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.039200                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.037115                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001029                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.038870                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.038870                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  5534.951636                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 25598.799515                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 17785.714286                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  8561.545973                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  8561.545973                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3558.808733                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.868850                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.868850                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     24247440                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        24247440                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4559242                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4559242                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         6797                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         6797                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         5792                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         5792                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      28806682                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         28806682                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     28806682                       # number of overall hits
+system.cpu.dcache.overall_hits::total        28806682                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       989267                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        989267                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       175739                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       175739                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            7                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            7                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1165006                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1165006                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1165006                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1165006                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5475545000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5475545000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   4498707428                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   4498707428                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       124500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       124500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   9974252428                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   9974252428                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   9974252428                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   9974252428                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     25236707                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     25236707                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         6804                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         6804                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         5792                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         5792                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     29971688                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     29971688                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     29971688                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     29971688                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.039200                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037115                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001029                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.038870                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.038870                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  5534.951636                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 25598.799515                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 17785.714286                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  8561.545973                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  8561.545973                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     23239503                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              8123                       # number of cycles access was blocked
@@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  2860.950757
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   942907                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             86240                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           131213                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            7                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             217453                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            217453                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          903027                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          44526                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           947553                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          947553                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2253076500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1081063056                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   3334139556                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   3334139556                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.035782                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009404                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.031615                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.031615                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2495.026727                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24279.366123                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3518.683974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3518.683974                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       942907                       # number of writebacks
+system.cpu.dcache.writebacks::total            942907                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        86240                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        86240                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       131213                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       131213                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            7                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            7                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       217453                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       217453                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       217453                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       217453                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       903027                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       903027                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        44526                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        44526                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       947553                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       947553                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       947553                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       947553                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2253076500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2253076500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1081063056                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1081063056                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   3334139556                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   3334139556                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   3334139556                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   3334139556                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.035782                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009404                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.031615                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.031615                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2495.026727                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24279.366123                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3518.683974                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3518.683974                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                   744                       # number of replacements
 system.cpu.l2cache.tagsinuse              9229.669691                       # Cycle average of tags in use
@@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs                 1596774                       # To
 system.cpu.l2cache.sampled_refs                 15569                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                102.561115                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           392.792276                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8836.877415                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.011987                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.269680                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                901413                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              942907                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               31267                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 932680                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                932680                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                1057                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14538                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15595                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15595                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      36209000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    498763000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      534972000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     534972000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            902470                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          942907                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           45805                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             948275                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            948275                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.001171                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.317389                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016446                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016446                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34256.385998                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34307.538864                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34304.071818                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34304.071818                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  8836.877415                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    199.760007                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    193.032269                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.269680                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006096                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.005891                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.281667                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           20                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       901393                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         901413                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942907                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942907                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        31267                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        31267                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           20                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       932660                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          932680                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           20                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       932660                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         932680                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          702                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          355                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1057                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14538                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14538                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          702                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14893                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15595                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          702                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14893                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15595                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24071000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     12138000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     36209000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    498763000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    498763000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24071000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    510901000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    534972000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24071000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    510901000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    534972000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          722                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       901748                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       902470                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942907                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942907                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        45805                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        45805                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          722                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       947553                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       948275                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          722                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       947553                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       948275                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.972299                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000394                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.317389                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.972299                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015717                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.972299                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015717                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.173789                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34191.549296                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34307.538864                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.173789                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34304.774055                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.173789                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34304.774055                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               10                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                10                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               10                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           1047                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14538                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15585                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15585                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     32560500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    451777500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    484338000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    484338000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001160                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.317389                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016435                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016435                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31098.853868                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31075.629385                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31077.189605                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31077.189605                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
+system.cpu.l2cache.writebacks::total               32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            9                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            9                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            9                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           10                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          701                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          346                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1047                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14538                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14538                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          701                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14884                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15585                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          701                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14884                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15585                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     21793500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     10767000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     32560500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    451777500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    451777500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     21793500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    462544500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    484338000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     21793500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    462544500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    484338000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.970914                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000384                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.317389                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.970914                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015708                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.970914                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015708                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31089.158345                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31118.497110                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31075.629385                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31089.158345                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31076.625907                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31089.158345                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31076.625907                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 67a5d19a58be9461ba840285966c229cb0d184d0..75c90b82c597aa7b1efa0cfeb68540b8d7713739 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index 902784594f97148af604f2db8c783dc6ae5058d1..f67da13a2c699e0e562fbda5ff2254d1b83ae781 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:47:31
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:51:19
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 66ab48bd5a7e26135206de4200df17dabb2479a2..393a58e498dde7a6e5e245da72242cba13488e3a 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.054241                       # Nu
 sim_ticks                                 54240666000                       # Number of ticks simulated
 final_tick                                54240666000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2777644                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1651027932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 342980                       # Number of bytes of host memory used
-host_seconds                                    32.85                       # Real time elapsed on the host
-sim_insts                                    91252969                       # Number of instructions simulated
+host_inst_rate                                3177444                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3200257                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1902228216                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 345536                       # Number of bytes of host memory used
+host_seconds                                    28.51                       # Real time elapsed on the host
+sim_insts                                    90602415                       # Number of instructions simulated
+sim_ops                                      91252969                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   521339715                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              431323116                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 18908138                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  442                       # Nu
 system.cpu.numCycles                        108481333                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91252969                       # Number of instructions executed
+system.cpu.committedInsts                    90602415                       # Number of instructions committed
+system.cpu.committedOps                      91252969                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
index 2f73411a5b30664eb82bfcab5f7e578584ad23b6..14eb2c781ff35b7803b386e5182897f99ab0600e 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 959967602758d8bb594950384012bb10feb79dd0..d749257854544b7ce05d4dee9b0b33c613630760 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:48:15
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:51:58
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/10.mcf/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index d6f3be23441d9b951c22554dedf68e3084b06128..27b93150eeeae366b682f8496266ac18acfa8016 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.148086                       # Nu
 sim_ticks                                148086239000                       # Number of ticks simulated
 final_tick                               148086239000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1300672                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2111359212                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 351948                       # Number of bytes of host memory used
-host_seconds                                    70.14                       # Real time elapsed on the host
-sim_insts                                    91226321                       # Number of instructions simulated
+host_inst_rate                                1696896                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1709063                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2774293546                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 354444                       # Number of bytes of host memory used
+host_seconds                                    53.38                       # Real time elapsed on the host
+sim_insts                                    90576869                       # Number of instructions simulated
+sim_ops                                      91226321                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      986112                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  36992                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2048                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  442                       # Nu
 system.cpu.numCycles                        296172478                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91226321                       # Number of instructions executed
+system.cpu.committedInsts                    90576869                       # Number of instructions committed
+system.cpu.committedOps                      91226321                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              72525682                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     48                       # Number of float alu accesses
 system.cpu.num_func_calls                       96832                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs                107830181                       # To
 system.cpu.icache.sampled_refs                    599                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               180016.996661                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.335448                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.249187                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              107830181                       # number of ReadReq hits
-system.cpu.icache.demand_hits               107830181                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              107830181                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  599                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   599                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  599                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       32662000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        32662000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       32662000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          107830780                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           107830780                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          107830780                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000006                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000006                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54527.545910                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54527.545910                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54527.545910                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     510.335448                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.249187                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    107830181                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       107830181                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     107830181                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        107830181                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    107830181                       # number of overall hits
+system.cpu.icache.overall_hits::total       107830181                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          599                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           599                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          599                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            599                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          599                       # number of overall misses
+system.cpu.icache.overall_misses::total           599                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     32662000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     32662000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     32662000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     32662000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     32662000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    107830780                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    107830780                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    107830780                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    107830780                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    107830780                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000006                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000006                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000006                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54527.545910                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54527.545910                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             599                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              599                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             599                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     30865000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     30865000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     30865000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000006                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000006                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51527.545910                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51527.545910                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          599                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          599                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          599                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          599                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          599                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     30865000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     30865000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     30865000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000006                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51527.545910                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 942702                       # number of replacements
 system.cpu.dcache.tagsinuse               3568.549501                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                 26345365                       # To
 system.cpu.dcache.sampled_refs                 946798                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  27.825751                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            54479156000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3568.549501                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.871228                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               21649219                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               4688372                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             3887                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              3887                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                26337591                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               26337591                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               900189                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               46609                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                946798                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               946798                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    12614490000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    1263542000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     13878032000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    13878032000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           22549408                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           4734981                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         3887                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          3887                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            27284389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           27284389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.039921                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.009844                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.034701                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.034701                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14013.157237                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27109.399472                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14657.859438                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14657.859438                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3568.549501                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.871228                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     21649219                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        21649219                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      4688372                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        4688372                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         3887                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         3887                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         3887                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      26337591                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26337591                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26337591                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26337591                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       900189                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        900189                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        46609                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        46609                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       946798                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         946798                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       946798                       # number of overall misses
+system.cpu.dcache.overall_misses::total        946798                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12614490000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1263542000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13878032000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13878032000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13878032000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     22549408                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      4734981                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         3887                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         3887                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     27284389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     27284389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.039921                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009844                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.034701                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.034701                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14013.157237                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27109.399472                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14657.859438                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14657.859438                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   942309                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          900189                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          46609                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           946798                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          946798                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9913923000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1123715000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  11037638000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  11037638000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.039921                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009844                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.034701                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.034701                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11013.157237                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24109.399472                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11657.859438                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       942309                       # number of writebacks
+system.cpu.dcache.writebacks::total            942309                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       900189                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46609                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       946798                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       946798                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       946798                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9913923000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1123715000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  11037638000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  11037638000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.039921                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009844                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034701                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11013.157237                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24109.399472                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11657.859438                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11657.859438                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                   634                       # number of replacements
 system.cpu.l2cache.tagsinuse              9235.307693                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                 1594542                       # To
 system.cpu.l2cache.sampled_refs                 15392                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                103.595504                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           325.097811                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8910.209882                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.009921                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.271918                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                899928                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              942309                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               32061                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 931989                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                931989                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 860                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14548                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15408                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15408                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      44720000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    756496000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      801216000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     801216000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            900788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          942309                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           46609                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             947397                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            947397                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.000955                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.312129                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016264                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016264                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  8910.209882                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    165.071875                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    160.025936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.271918                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.005038                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.004884                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.281839                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           21                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       899907                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         899928                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       942309                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       942309                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32061                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32061                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           21                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       931968                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          931989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           21                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       931968                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         931989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          578                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          282                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          860                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14548                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14548                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          578                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14830                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15408                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          578                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14830                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15408                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     30056000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     14664000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     44720000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    756496000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     30056000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    771160000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    801216000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     30056000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    771160000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    801216000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          599                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       900189                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       900788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       942309                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46609                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          599                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       946798                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       947397                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          599                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       946798                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       947397                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.964942                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000313                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.312129                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.964942                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015663                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.964942                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015663                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      32                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            860                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14548                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15408                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15408                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     34400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    581920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    616320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    616320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.000955                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.312129                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016264                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016264                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks           32                       # number of writebacks
+system.cpu.l2cache.writebacks::total               32                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          578                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          282                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          860                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14548                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          578                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14830                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15408                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          578                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14830                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15408                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     23120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     11280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     34400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    581920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     23120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    593200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    616320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     23120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    593200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    616320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000313                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.312129                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015663                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.964942                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015663                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 77055bd16933f4d8d036a1b9c2a4b3e875487198..5d8a4468f86cca149517339d359591a87221939b 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
index 18a19b6d72957cdef41fb131d38fc68239b630f9..019979259a507df9e490152c3d56bf5b34b0772c 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:20:13
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:49
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index e3ffceab4e8ba4574df53cced0ab0f9a4343730f..fc2e528562625175e93382cc835f7dd470cfca07 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.122216                       # Nu
 sim_ticks                                122215830000                       # Number of ticks simulated
 final_tick                               122215830000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3409932                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1709135687                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 338176                       # Number of bytes of host memory used
-host_seconds                                    71.51                       # Real time elapsed on the host
-sim_insts                                   243835278                       # Number of instructions simulated
+host_inst_rate                                4048457                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4048623                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2029262264                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 335836                       # Number of bytes of host memory used
+host_seconds                                    60.23                       # Real time elapsed on the host
+sim_insts                                   243825163                       # Number of instructions simulated
+sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1306360053                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              977686044                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 91606089                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  443                       # Nu
 system.cpu.numCycles                        244431661                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        243835278                       # Number of instructions executed
+system.cpu.committedInsts                   243825163                       # Number of instructions committed
+system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
 system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
index acd41b2d5b01bedd92f4cbd37dee04b267624e78..ad77524dc84f967a9d6ed7c0095800a968dcddae 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
index ca44a686d345531d9de4e992a35ccd709eb931e4..0301a7a935eff056cf66ff737d7535746615f221 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:21:35
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:58:00
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/10.mcf/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 7dc591cfed274926a7319a8dc7f7d72b358fa524..14199b22715f3442748153aafa79e63307e41403 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.362431                       # Nu
 sim_ticks                                362430887000                       # Number of ticks simulated
 final_tick                               362430887000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1587659                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2359857170                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 346888                       # Number of bytes of host memory used
-host_seconds                                   153.58                       # Real time elapsed on the host
-sim_insts                                   243835278                       # Number of instructions simulated
+host_inst_rate                                1947938                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1948018                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2895487158                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 344700                       # Number of bytes of host memory used
+host_seconds                                   125.17                       # Real time elapsed on the host
+sim_insts                                   243825163                       # Number of instructions simulated
+sim_ops                                     243835278                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     1001472                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  56256                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2560                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  443                       # Nu
 system.cpu.numCycles                        724861774                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        243835278                       # Number of instructions executed
+system.cpu.committedInsts                   243825163                       # Number of instructions committed
+system.cpu.committedOps                     243835278                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             194726506                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  11630                       # Number of float alu accesses
 system.cpu.num_func_calls                     4252956                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs                244420630                       # To
 system.cpu.icache.sampled_refs                    882                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               277120.895692                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            725.567632                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.354281                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              244420630                       # number of ReadReq hits
-system.cpu.icache.demand_hits               244420630                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              244420630                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  882                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   882                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  882                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       49266000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        49266000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       49266000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          244421512                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           244421512                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          244421512                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55857.142857                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55857.142857                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55857.142857                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     725.567632                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.354281                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    244420630                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       244420630                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     244420630                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        244420630                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    244420630                       # number of overall hits
+system.cpu.icache.overall_hits::total       244420630                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          882                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           882                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          882                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            882                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          882                       # number of overall misses
+system.cpu.icache.overall_misses::total           882                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     49266000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     49266000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     49266000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     49266000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     49266000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     49266000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    244421512                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    244421512                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    244421512                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    244421512                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244421512                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    244421512                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55857.142857                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55857.142857                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             882                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              882                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             882                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     46620000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     46620000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     46620000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52857.142857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52857.142857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          882                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          882                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          882                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          882                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          882                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          882                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     46620000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     46620000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     46620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     46620000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     46620000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52857.142857                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 935475                       # number of replacements
 system.cpu.dcache.tagsinuse               3563.824259                       # Cycle average of tags in use
@@ -102,38 +116,59 @@ system.cpu.dcache.total_refs                104186700                       # To
 system.cpu.dcache.sampled_refs                 939571                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 110.887522                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle           134373316000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3563.824259                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.870074                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               81327577                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              22855241                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                   3882                       # number of SwapReq hits
-system.cpu.dcache.demand_hits               104182818                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              104182818                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               892857                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               46710                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses                    4                       # number of SwapReq misses
-system.cpu.dcache.demand_misses                939567                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               939567                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    12508482000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    1265712000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency          98000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency     13774194000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    13774194000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           82220434                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          22901951                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses               3886                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           105122385                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          105122385                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.010859                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.002040                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate          0.001029                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.008938                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.008938                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14009.502082                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27097.238279                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency        24500                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14660.150899                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14660.150899                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3563.824259                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.870074                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     81327577                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        81327577                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     22855241                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       22855241                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data         3882                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total            3882                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data     104182818                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        104182818                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    104182818                       # number of overall hits
+system.cpu.dcache.overall_hits::total       104182818                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       892857                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        892857                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        46710                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        46710                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data            4                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total             4                       # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data       939567                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         939567                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       939567                       # number of overall misses
+system.cpu.dcache.overall_misses::total        939567                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  12508482000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  12508482000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1265712000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1265712000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data        98000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total        98000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  13774194000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  13774194000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  13774194000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  13774194000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     82220434                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     22901951                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     22901951                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data         3886                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total         3886                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    105122385                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    105122385                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    105122385                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.010859                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002040                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.001029                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008938                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008938                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14009.502082                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27097.238279                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        24500                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14660.150899                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14660.150899                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   935237                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          892857                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          46710                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses               4                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           939567                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          939567                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   9829911000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1125582000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency        86000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  10955493000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  10955493000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.010859                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.002040                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.001029                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.008938                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.008938                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11009.502082                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24097.238279                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        21500                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11660.150899                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       935237                       # number of writebacks
+system.cpu.dcache.writebacks::total            935237                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       892857                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       892857                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        46710                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        46710                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data            4                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total            4                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       939567                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       939567                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       939567                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       939567                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   9829911000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   9829911000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1125582000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1125582000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        86000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        86000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10955493000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10955493000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10955493000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10955493000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.010859                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.001029                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.008938                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11009.502082                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24097.238279                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        21500                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11660.150899                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11660.150899                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                   865                       # number of replacements
 system.cpu.l2cache.tagsinuse              9236.752232                       # Cycle average of tags in use
@@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs                 1585884                       # To
 system.cpu.l2cache.sampled_refs                 15631                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                101.457616                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           375.506440                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          8861.245791                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.011460                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.270424                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                892658                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              935237                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               32147                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 924805                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                924805                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                1081                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             14567                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                15648                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               15648                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      56212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    757484000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      813696000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     813696000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            893739                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          935237                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           46714                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             940453                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            940453                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.001210                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.311834                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.016639                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.016639                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  8861.245791                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    244.574580                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    130.931861                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.270424                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.007464                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.003996                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.281883                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       892655                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         892658                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       935237                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       935237                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        32147                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        32147                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       924802                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          924805                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       924802                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         924805                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          879                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          202                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         1081                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        14567                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        14567                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          879                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        14769                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         15648                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          879                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        14769                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        15648                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     45708000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     10504000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     56212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    757484000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    757484000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     45708000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    767988000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    813696000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     45708000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    767988000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    813696000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          882                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       892857                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       893739                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       935237                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       935237                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        46714                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        46714                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          882                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       939571                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       940453                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          882                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       939571                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       940453                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996599                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.000226                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.311834                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996599                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.015719                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996599                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.015719                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                      40                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           1081                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        14567                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           15648                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          15648                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     43240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    582680000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    625920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    625920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.001210                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.311834                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.016639                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.016639                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks           40                       # number of writebacks
+system.cpu.l2cache.writebacks::total               40                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          879                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          202                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         1081                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        14567                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        14567                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          879                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        14769                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        15648                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          879                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        14769                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        15648                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     35160000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      8080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     43240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    582680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    582680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     35160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    590760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    625920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     35160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    590760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    625920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.000226                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.311834                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.015719                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996599                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.015719                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 546611c4c18aa3a36c0810e1c97069282f1d6473..f9591bc5ca7b76fd8bf6d01acecad65920a4d2d3 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -442,20 +435,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -494,20 +480,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -531,14 +510,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
index 1c8484fc7e0291ae458928840293a2f7e04cdf13..90035090e9fd39c4fb1465ab58fa32bbc2d8a66c 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  9 2012 12:45:55
-gem5 started Feb  9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:13:01
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 0040f922ce9db3fc36dbbc9e1eb1c8297c27c61f..1bd6324e311898e6db9584498f19ffbec15d51b2 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.070047                       # Nu
 sim_ticks                                 70046988500                       # Number of ticks simulated
 final_tick                                70046988500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  78701                       # Simulator instruction rate (inst/s)
-host_tick_rate                               19816485                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 388420                       # Number of bytes of host memory used
-host_seconds                                  3534.78                       # Real time elapsed on the host
-sim_insts                                   278192519                       # Number of instructions simulated
+host_inst_rate                                 120922                       # Simulator instruction rate (inst/s)
+host_op_rate                                   212925                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               53613076                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 355612                       # Number of bytes of host memory used
+host_seconds                                  1306.53                       # Real time elapsed on the host
+sim_insts                                   157988582                       # Number of instructions simulated
+sim_ops                                     278192519                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     3895936                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  65216                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                   892288                       # Number of bytes written to this memory
@@ -236,7 +238,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       2.229177                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.730584                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      278192519                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      157988582                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        278192519                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        65103374                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             446                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           1332005                       # The number of times a branch was mispredicted
@@ -257,7 +260,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    130436298                       # Number of insts commited each cycle
-system.cpu.commit.count                     278192519                       # Number of instructions committed
+system.cpu.commit.committedInsts            157988582                       # Number of instructions committed
+system.cpu.commit.committedOps              278192519                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      122219139                       # Number of memory references committed
 system.cpu.commit.loads                      90779388                       # Number of loads committed
@@ -272,12 +276,13 @@ system.cpu.rob.rob_reads                    457952368                       # Th
 system.cpu.rob.rob_writes                   695479183                       # The number of ROB writes
 system.cpu.timesIdled                           23894                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          787486                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   278192519                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             278192519                       # Number of Instructions Simulated
-system.cpu.cpi                               0.503586                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.503586                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.985756                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.985756                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   157988582                       # Number of Instructions Simulated
+system.cpu.committedOps                     278192519                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             157988582                       # Number of Instructions Simulated
+system.cpu.cpi                               0.886735                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.886735                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.127733                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.127733                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                554395898                       # number of integer regfile reads
 system.cpu.int_regfile_writes               279799467                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       352                       # number of floating regfile reads
@@ -289,26 +294,39 @@ system.cpu.icache.total_refs                 28212585                       # To
 system.cpu.icache.sampled_refs                   1024                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               27551.352539                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            822.534021                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.401628                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28212585                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28212585                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28212585                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1300                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1300                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1300                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       46952500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        46952500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       46952500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28213885                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28213885                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28213885                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000046                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000046                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000046                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36117.307692                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36117.307692                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36117.307692                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     822.534021                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.401628                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.401628                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     28212585                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        28212585                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      28212585                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         28212585                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     28212585                       # number of overall hits
+system.cpu.icache.overall_hits::total        28212585                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1300                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1300                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1300                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1300                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1300                       # number of overall misses
+system.cpu.icache.overall_misses::total          1300                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     46952500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     46952500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     46952500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     46952500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     46952500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     46952500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     28213885                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     28213885                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     28213885                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     28213885                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     28213885                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     28213885                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000046                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000046                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000046                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36117.307692                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36117.307692                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36117.307692                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               275                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                275                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               275                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            1025                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             1025                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            1025                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     36071500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     36071500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     36071500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000036                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000036                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000036                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35191.707317                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35191.707317                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35191.707317                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          275                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          275                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          275                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          275                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          275                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          275                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         1025                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         1025                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         1025                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         1025                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         1025                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         1025                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     36071500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     36071500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     36071500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     36071500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     36071500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     36071500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000036                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000036                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000036                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35191.707317                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35191.707317                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35191.707317                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2072906                       # number of replacements
 system.cpu.dcache.tagsinuse               4073.029614                       # Cycle average of tags in use
@@ -345,32 +366,49 @@ system.cpu.dcache.total_refs                 77489413                       # To
 system.cpu.dcache.sampled_refs                2077002                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  37.308300                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            23588256000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4073.029614                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.994392                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               46135653                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31353751                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                77489404                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               77489404                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              2289012                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               86000                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2375012                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2375012                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    13766771000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    1501245288                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     15268016288                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    15268016288                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           48424665                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            79864416                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           79864416                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.047270                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.002735                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.029738                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.029738                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency  6014.285203                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 17456.340558                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency  6428.605956                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency  6428.605956                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4073.029614                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994392                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994392                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     46135653                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        46135653                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31353751                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31353751                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      77489404                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         77489404                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     77489404                       # number of overall hits
+system.cpu.dcache.overall_hits::total        77489404                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2289012                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2289012                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        86000                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        86000                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2375012                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2375012                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2375012                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2375012                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  13766771000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  13766771000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   1501245288                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   1501245288                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  15268016288                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  15268016288                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  15268016288                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  15268016288                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     48424665                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     48424665                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     79864416                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     79864416                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     79864416                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     79864416                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.047270                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002735                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.029738                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.029738                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data  6014.285203                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17456.340558                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data  6428.605956                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data  6428.605956                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1880780                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            294089                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             3918                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             298007                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            298007                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1994923                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          82082                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2077005                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2077005                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   5565133500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   1157645788                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   6722779288                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   6722779288                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.041196                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.002611                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.026007                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.026007                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2789.648272                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 14103.528033                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  3236.766059                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  3236.766059                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1880780                       # number of writebacks
+system.cpu.dcache.writebacks::total           1880780                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       294089                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       294089                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3918                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3918                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       298007                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       298007                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       298007                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       298007                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1994923                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1994923                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        82082                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        82082                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2077005                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2077005                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2077005                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2077005                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   5565133500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   5565133500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   1157645788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   1157645788                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6722779288                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6722779288                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6722779288                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6722779288                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.041196                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.002611                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026007                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026007                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  2789.648272                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 14103.528033                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  3236.766059                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  3236.766059                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 33246                       # number of replacements
 system.cpu.l2cache.tagsinuse             18964.988080                       # Cycle average of tags in use
@@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs                 3764517                       # To
 system.cpu.l2cache.sampled_refs                 61253                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 61.458492                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6037.038666                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12927.949414                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.184236                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.394530                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1964445                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1880780                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               52709                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                2017154                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               2017154                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               31361                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses                1                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses             29513                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                60874                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               60874                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1071202500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   1006190000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     2077392500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    2077392500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1995806                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1880780                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses              1                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           82222                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2078028                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2078028                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.015713                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.358943                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.029294                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.029294                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34157.153790                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34093.111510                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34126.104741                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34126.104741                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 12927.949414                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    243.086422                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   5793.952244                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.394530                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.007418                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.176817                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.578766                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            5                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1964440                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1964445                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1880780                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1880780                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        52709                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        52709                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            5                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      2017149                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         2017154                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            5                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      2017149                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        2017154                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1019                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        30342                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31361                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data            1                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total            1                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        29513                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        29513                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1019                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        59855                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         60874                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1019                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        59855                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        60874                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     34913500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1036289000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1071202500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   1006190000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   1006190000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     34913500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   2042479000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   2077392500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     34913500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   2042479000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   2077392500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         1024                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1994782                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1995806                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1880780                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1880780                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total            1                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        82222                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        82222                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         1024                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2077004                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2078028                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         1024                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2077004                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2078028                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.995117                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.015211                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.358943                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995117                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.028818                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995117                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.028818                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34262.512267                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34153.615451                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34093.111510                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34262.512267                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34123.782474                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34262.512267                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34123.782474                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -453,34 +540,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   13942                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          31361                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses            1                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        29513                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           60874                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          60874                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    972854000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency        31000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    914925500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   1887779500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   1887779500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.015713                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.358943                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.029294                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.029294                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31021.140907                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.762376                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31011.260965                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31011.260965                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        13942                       # number of writebacks
+system.cpu.l2cache.writebacks::total            13942                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1019                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        30342                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31361                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total            1                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        29513                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        29513                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1019                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        59855                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        60874                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1019                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        59855                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        60874                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     31643000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    941211000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    972854000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total        31000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    914925500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    914925500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     31643000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   1856136500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   1887779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     31643000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   1856136500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   1887779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.995117                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.015211                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.358943                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995117                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028818                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995117                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028818                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.993131                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.071188                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.762376                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.993131                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.550497                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.993131                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.550497                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 96706c5cc686282ec38d6195fa209ccc6879f53a..15b801d935a7c3740d119e8fecba5cd1639bee1c 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +97,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +121,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index eb189c10aa0cd204087b7a1dc8c87099bbd255db..a3234c8311f9b6792a00b70bf221e8f0708c47f1 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:52:52
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:18:06
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index e99e16cd0551b857c1b050e9afee7db604f7c9c0..e6ec29e4aeacd5950b4e369c05b032f9f915c2e9 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.168950                       # Nu
 sim_ticks                                168950072000                       # Number of ticks simulated
 final_tick                               168950072000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2042288                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1240309006                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 339312                       # Number of bytes of host memory used
-host_seconds                                   136.22                       # Real time elapsed on the host
-sim_insts                                   278192520                       # Number of instructions simulated
+host_inst_rate                                1605694                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2827368                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1717098424                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 344660                       # Number of bytes of host memory used
+host_seconds                                    98.39                       # Real time elapsed on the host
+sim_insts                                   157988583                       # Number of instructions simulated
+sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2458815679                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             1741569664                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                243173115                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  444                       # Nu
 system.cpu.numCycles                        337900145                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        278192520                       # Number of instructions executed
+system.cpu.committedInsts                   157988583                       # Number of instructions committed
+system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index 008adeebb67db012112b11653b1f1eb7f6d751e9..426472e17e7eed3d06798875af5bfafaa9939b3d 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +104,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +118,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +149,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +171,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=mcf mcf.in
-cwd=build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -191,7 +203,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index e89b51a20b806c2db23d9249563f03dd942535b7..064d05227cc8da742aad8fcd766b13af7e5bbc89 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:55:19
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:19:55
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/10.mcf/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 59ae818d2bb05a23b6e94b448474b75c3ec7c02e..a57ebe25878cf393d6bdd7a5d65750b19b32a824 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.370011                       # Nu
 sim_ticks                                370010840000                       # Number of ticks simulated
 final_tick                               370010840000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1163147                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1547047043                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 348152                       # Number of bytes of host memory used
-host_seconds                                   239.17                       # Real time elapsed on the host
-sim_insts                                   278192520                       # Number of instructions simulated
+host_inst_rate                                 912216                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1606265                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2136418129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 353708                       # Number of bytes of host memory used
+host_seconds                                   173.19                       # Real time elapsed on the host
+sim_insts                                   157988583                       # Number of instructions simulated
+sim_ops                                     278192520                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     4900800                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  51712                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  1885440                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  444                       # Nu
 system.cpu.numCycles                        740021680                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        278192520                       # Number of instructions executed
+system.cpu.committedInsts                   157988583                       # Number of instructions committed
+system.cpu.committedOps                     278192520                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             278186228                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     40                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs                217695401                       # To
 system.cpu.icache.sampled_refs                    808                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               269425.001238                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            666.191948                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.325289                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              217695401                       # number of ReadReq hits
-system.cpu.icache.demand_hits               217695401                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              217695401                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  808                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   808                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  808                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       45248000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        45248000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       45248000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          217696209                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           217696209                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          217696209                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     666.191948                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.325289                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    217695401                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       217695401                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     217695401                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        217695401                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    217695401                       # number of overall hits
+system.cpu.icache.overall_hits::total       217695401                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           808                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            808                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          808                       # number of overall misses
+system.cpu.icache.overall_misses::total           808                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     45248000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     45248000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     45248000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     45248000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     45248000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    217696209                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    217696209                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    217696209                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    217696209                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             808                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              808                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             808                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     42824000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     42824000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     42824000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          808                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          808                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          808                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42824000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42824000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42824000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2062733                       # number of replacements
 system.cpu.dcache.tagsinuse               4076.661903                       # Cycle average of tags in use
@@ -102,32 +116,49 @@ system.cpu.dcache.total_refs                120152372                       # To
 system.cpu.dcache.sampled_refs                2066829                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  58.133678                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle           126200130000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.661903                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995279                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               88818730                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              31333642                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               120152372                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              120152372                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1960720                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              106109                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2066829                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2066829                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    28849058000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3268793000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     32117851000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    32117851000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           90779450                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          31439751                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           122219201                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          122219201                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.021599                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.003375                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.016911                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.016911                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14713.502183                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 30805.991952                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 15539.675029                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 15539.675029                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4076.661903                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995279                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     88818730                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        88818730                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     31333642                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       31333642                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     120152372                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        120152372                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    120152372                       # number of overall hits
+system.cpu.dcache.overall_hits::total       120152372                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1960720                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1960720                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       106109                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       106109                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2066829                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2066829                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2066829                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2066829                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  28849058000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3268793000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  32117851000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  32117851000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  32117851000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     90779450                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     31439751                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    122219201                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    122219201                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021599                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.003375                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016911                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016911                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14713.502183                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30805.991952                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 15539.675029                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 15539.675029                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1437080                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1960720                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         106109                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2066829                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2066829                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  22966898000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2950464500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  25917362500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  25917362500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.021599                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.003375                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.016911                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.016911                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11713.502183                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27805.977815                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 12539.674303                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1437080                       # number of writebacks
+system.cpu.dcache.writebacks::total           1437080                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1960720                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       106109                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2066829                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2066829                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2066829                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  22966898000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2950464500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  25917362500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  25917362500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.021599                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.003375                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.016911                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11713.502183                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27805.977815                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12539.674303                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12539.674303                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                 49212                       # number of replacements
 system.cpu.l2cache.tagsinuse             18614.603260                       # Cycle average of tags in use
@@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs                 3296079                       # To
 system.cpu.l2cache.sampled_refs                 77127                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                 42.735735                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          6551.798271                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         12062.804989                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.199945                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.368128                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1927411                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1437080                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               63651                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1991062                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1991062                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               34117                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             42458                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                76575                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses               76575                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1774084000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2207845500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     3981929500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    3981929500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1961528                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1437080                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          106109                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2067637                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2067637                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.017393                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.400136                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.037035                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.037035                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.694804                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000.385243                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000.385243                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 12062.804989                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    196.794797                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   6355.003474                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.368128                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.006006                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.193939                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.568073                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      1927411                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1927411                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1437080                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1437080                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        63651                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        63651                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1991062                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      1991062                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1991062                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          808                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        33309                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        34117                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        42458                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        42458                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          808                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data        75767                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total         76575                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          808                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data        75767                       # number of overall misses
+system.cpu.l2cache.overall_misses::total        76575                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     42016000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1732068000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1774084000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2207845500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     42016000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   3939913500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   3981929500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     42016000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   3939913500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   3981929500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          808                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1960720                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1961528                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1437080                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       106109                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          808                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2066829                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2067637                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          808                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2066829                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2067637                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.016988                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.400136                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.036659                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.036659                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.694804                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.389352                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.389352                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   29460                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          34117                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        42458                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses           76575                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses          76575                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1364680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   1698320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   3063000000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   3063000000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.017393                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.400136                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.037035                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.037035                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        29460                       # number of writebacks
+system.cpu.l2cache.writebacks::total            29460                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          808                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        33309                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        34117                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        42458                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          808                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data        75767                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total        76575                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          808                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data        75767                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total        76575                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32320000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1332360000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1364680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   1698320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   3030680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   3063000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   3030680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   3063000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.016988                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.400136                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.036659                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.036659                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 0436eab5357109e985afcbe70e4e8792fa430bd4..0afad448e75143127d8816041f1de4d95434f3bf 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,14 +508,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
index cc61bb6b62b38e00415f188669c0b342708bed96..f2e7dd662f3c57bf46a7f7234b408e9318941570 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:53:02
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index c0ee61c5b5620db639088a54975f6ba7c85c98e1..de8607854a6f0ff85ed933995f95b144175e80a8 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.274128                       # Nu
 sim_ticks                                274128411000                       # Number of ticks simulated
 final_tick                               274128411000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  67477                       # Simulator instruction rate (inst/s)
-host_tick_rate                               32262353                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 260864                       # Number of bytes of host memory used
-host_seconds                                  8496.85                       # Real time elapsed on the host
-sim_insts                                   573341187                       # Number of instructions simulated
+host_inst_rate                                 133293                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150155                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               71792865                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228092                       # Number of bytes of host memory used
+host_seconds                                  3818.32                       # Real time elapsed on the host
+sim_insts                                   508954626                       # Number of instructions simulated
+sim_ops                                     573341187                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    15240192                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 229568                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10959680                       # Number of bytes written to this memory
@@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.265299                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.595401                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      574685071                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      510298510                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        574685071                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       312438031                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         3878199                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts          20478103                       # The number of times a branch was mispredicted
@@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    495250570                       # Number of insts commited each cycle
-system.cpu.commit.count                     574685071                       # Number of instructions committed
+system.cpu.commit.committedInsts            510298510                       # Number of instructions committed
+system.cpu.commit.committedOps              574685071                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      184376791                       # Number of memory references committed
 system.cpu.commit.loads                     126772935                       # Number of loads committed
@@ -318,12 +322,13 @@ system.cpu.rob.rob_reads                   1367535962                       # Th
 system.cpu.rob.rob_writes                  1823647630                       # The number of ROB writes
 system.cpu.timesIdled                           94158                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                         3785113                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   573341187                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             573341187                       # Number of Instructions Simulated
-system.cpu.cpi                               0.956249                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.956249                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.045753                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.045753                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   508954626                       # Number of Instructions Simulated
+system.cpu.committedOps                     573341187                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             508954626                       # Number of Instructions Simulated
+system.cpu.cpi                               1.077221                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.077221                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.928314                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.928314                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               3289345591                       # number of integer regfile reads
 system.cpu.int_regfile_writes               815117578                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
@@ -335,26 +340,39 @@ system.cpu.icache.total_refs                141602716                       # To
 system.cpu.icache.sampled_refs                  14723                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                9617.789581                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1062.179544                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.518642                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              141602717                       # number of ReadReq hits
-system.cpu.icache.demand_hits               141602717                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              141602717                       # number of overall hits
-system.cpu.icache.ReadReq_misses                16509                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 16509                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                16509                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      235489500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       235489500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      235489500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          141619226                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           141619226                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          141619226                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000117                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000117                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000117                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 14264.310376                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 14264.310376                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 14264.310376                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1062.179544                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.518642                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.518642                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    141602717                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       141602717                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     141602717                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        141602717                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    141602717                       # number of overall hits
+system.cpu.icache.overall_hits::total       141602717                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        16509                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         16509                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        16509                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          16509                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        16509                       # number of overall misses
+system.cpu.icache.overall_misses::total         16509                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    235489500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    235489500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    235489500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    235489500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    235489500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    235489500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    141619226                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    141619226                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    141619226                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    141619226                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    141619226                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    141619226                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000117                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000117                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000117                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14264.310376                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14264.310376                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14264.310376                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -363,27 +381,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        1                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1646                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1646                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1646                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           14863                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            14863                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           14863                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    154537000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    154537000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    154537000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000105                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000105                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000105                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 10397.429859                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 10397.429859                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 10397.429859                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
+system.cpu.icache.writebacks::total                 1                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1646                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1646                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1646                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1646                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1646                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1646                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        14863                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        14863                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        14863                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        14863                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        14863                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        14863                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    154537000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    154537000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    154537000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    154537000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    154537000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    154537000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000105                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 10397.429859                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 10397.429859                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 10397.429859                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1212291                       # number of replacements
 system.cpu.dcache.tagsinuse               4058.220860                       # Cycle average of tags in use
@@ -391,40 +414,63 @@ system.cpu.dcache.total_refs                203801196                       # To
 system.cpu.dcache.sampled_refs                1216387                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 167.546345                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             5623769000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4058.220860                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.990777                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              146308743                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              52772298                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits          2488014                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits           2231920                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               199081041                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              199081041                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1241922                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1467008                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses             55                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               2708930                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2708930                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    14257023500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   24962643993                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       523000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     39219667493                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    39219667493                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          147550665                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses      2488069                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses       2231920                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           201789971                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          201789971                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.008417                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.027047                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000022                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.013425                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.013425                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 11479.805898                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 17016.024448                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency  9509.090909                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 14477.918401                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 14477.918401                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4058.220860                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.990777                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.990777                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    146308743                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       146308743                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     52772298                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       52772298                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      2488014                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      2488014                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      2231920                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      2231920                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     199081041                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        199081041                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    199081041                       # number of overall hits
+system.cpu.dcache.overall_hits::total       199081041                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1241922                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1241922                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1467008                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1467008                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           55                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           55                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2708930                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2708930                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2708930                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2708930                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  14257023500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  14257023500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  24962643993                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  24962643993                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       523000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       523000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39219667493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39219667493                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39219667493                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39219667493                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    147550665                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    147550665                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      2488069                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      2488069                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      2231920                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      2231920                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    201789971                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    201789971                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    201789971                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    201789971                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.008417                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.027047                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000022                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.013425                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.013425                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11479.805898                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 17016.024448                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  9509.090909                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 14477.918401                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 14477.918401                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       484000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -433,33 +479,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets  7934.426230                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1079423                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            365990                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1126420                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits           55                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1492410                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1492410                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          875932                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         340588                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1216520                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1216520                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   6305474000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   4364186500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  10669660500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  10669660500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005936                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006279                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.006029                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.006029                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  7198.588475                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 12813.682514                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  8770.641255                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  8770.641255                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1079423                       # number of writebacks
+system.cpu.dcache.writebacks::total           1079423                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       365990                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       365990                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1126420                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1126420                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           55                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           55                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1492410                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1492410                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1492410                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1492410                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       875932                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       875932                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       340588                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       340588                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1216520                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1216520                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1216520                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1216520                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6305474000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   6305474000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4364186500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4364186500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  10669660500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  10669660500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  10669660500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  10669660500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005936                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006279                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006029                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006029                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  7198.588475                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 12813.682514                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data  8770.641255                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data  8770.641255                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                218982                       # number of replacements
 system.cpu.l2cache.tagsinuse             21063.326998                       # Cycle average of tags in use
@@ -467,42 +522,85 @@ system.cpu.l2cache.total_refs                 1568375                       # To
 system.cpu.l2cache.sampled_refs                239342                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  6.552862                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          204310095000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7519.880092                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13543.446906                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.229489                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.413313                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                760536                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1079424                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits                 96                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits              232415                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 992951                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                992951                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              129729                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses               35                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            108423                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               238152                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              238152                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    4437312000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency       171500                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3713377000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     8150689000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    8150689000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            890265                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1079424                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses            131                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          340838                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1231103                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1231103                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.145720                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.267176                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.318107                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.193446                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.193446                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34204.472400                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency         4900                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34248.978538                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34224.734623                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34224.734623                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 13543.446906                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    176.680615                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7343.199477                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.413313                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.005392                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.224097                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.642802                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        11134                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       749402                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         760536                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1079424                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1079424                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           96                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           96                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       232415                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       232415                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        11134                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       981817                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          992951                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        11134                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       981817                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         992951                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3590                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       126139                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       129729                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           35                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           35                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       108423                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       108423                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3590                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       234562                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        238152                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3590                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       234562                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       238152                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    123146500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   4314165500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   4437312000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       171500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total       171500                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3713377000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3713377000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    123146500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8027542500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   8150689000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    123146500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8027542500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   8150689000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        14724                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       875541                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       890265                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1079424                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1079424                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          131                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          131                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       340838                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       340838                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        14724                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1216379                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1231103                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        14724                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1216379                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1231103                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.243820                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.144070                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.267176                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.318107                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.243820                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.192836                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.243820                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.192836                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.646240                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34201.678307                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data         4900                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34248.978538                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.646240                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34223.542176                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.646240                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34223.542176                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -511,35 +609,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  171245                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               22                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                22                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               22                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         129707                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses           35                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       108423                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          238130                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         238130                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4027357500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      1085000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3362010000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   7389367500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   7389367500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.145695                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.267176                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.318107                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.193428                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.193428                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31049.654221                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31008.273152                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31030.813001                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31030.813001                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       171245                       # number of writebacks
+system.cpu.l2cache.writebacks::total           171245                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            3                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           19                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           22                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            3                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           19                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            3                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           19                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3587                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       126120                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       129707                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           35                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           35                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       108423                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       108423                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3587                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       234543                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       238130                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3587                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       234543                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       238130                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    111526500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   3915831000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   4027357500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      1085000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      1085000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3362010000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3362010000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    111526500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   7277841000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   7389367500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    111526500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   7277841000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   7389367500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.243616                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.144048                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.267176                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.318107                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.243616                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.192821                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.243616                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.192821                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.859493                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31048.453853                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31008.273152                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.859493                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31029.879382                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.859493                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31029.879382                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index cbe7d05b4bfde36409a70f96305cc2f91af25091..4fff23cb47f053d63e4f8220a523eb58e50b7fba 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index e26a927e88cd0c80000965ea13b97d026712f725..2e77896eefcc696607836b3a8303847fd1b18288 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:54:41
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:54:26
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 12a51d6fdcbe4aff7a0c79a5080f2131b06b2fd2..52a89931970af333c831b188e997fc6d4a05ffbd 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.290499                       # Nu
 sim_ticks                                290498972000                       # Number of ticks simulated
 final_tick                               290498972000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3123764                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1589318228                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213568                       # Number of bytes of host memory used
-host_seconds                                   182.78                       # Real time elapsed on the host
-sim_insts                                   570968176                       # Number of instructions simulated
+host_inst_rate                                2958479                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3334501                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1696537892                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216124                       # Number of bytes of host memory used
+host_seconds                                   171.23                       # Real time elapsed on the host
+sim_insts                                   506581615                       # Number of instructions simulated
+sim_ops                                     570968176                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2489298238                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             2066445536                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                216067624                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  548                       # Nu
 system.cpu.numCycles                        580997945                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        570968176                       # Number of instructions executed
+system.cpu.committedInsts                   506581615                       # Number of instructions committed
+system.cpu.committedOps                     570968176                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
index 5a2d862327680061a92d6ea03e8026cbb48556d8..4d41782e04100df0a15b72fa5aeb73ab17fce7bf 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 8c135307312c4a672f4187b82cec8e546f9642a2..3a1edbeaad13d8b60c6e343ea7ee7cf59c9ff8ef 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 08:54:55
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:54:39
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/20.parser/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index f9d747bd5cd3e7aad35d8aecaa25803956ab5584..d73359a084d0dcfd5261d1d0eef1839f225bde06 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.722234                       # Nu
 sim_ticks                                722234364000                       # Number of ticks simulated
 final_tick                               722234364000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1518630                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1927485562                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222536                       # Number of bytes of host memory used
-host_seconds                                   374.70                       # Real time elapsed on the host
-sim_insts                                   569034848                       # Number of instructions simulated
+host_inst_rate                                1769028                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1993395                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2530070907                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225284                       # Number of bytes of host memory used
+host_seconds                                   285.46                       # Real time elapsed on the host
+sim_insts                                   504986861                       # Number of instructions simulated
+sim_ops                                     569034848                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    14797056                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 188608                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 11027328                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  548                       # Nu
 system.cpu.numCycles                       1444468728                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        569034848                       # Number of instructions executed
+system.cpu.committedInsts                   504986861                       # Number of instructions committed
+system.cpu.committedOps                     569034848                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             470727703                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                    15725605                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs                516599864                       # To
 system.cpu.icache.sampled_refs                  11521                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               44839.845847                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            984.426148                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.480677                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              516599864                       # number of ReadReq hits
-system.cpu.icache.demand_hits               516599864                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              516599864                       # number of overall hits
-system.cpu.icache.ReadReq_misses                11521                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 11521                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                11521                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      285068000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       285068000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      285068000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          516611385                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           516611385                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          516611385                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000022                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000022                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000022                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 24743.338252                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 24743.338252                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 24743.338252                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     984.426148                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.480677                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.480677                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    516599864                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       516599864                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     516599864                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        516599864                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    516599864                       # number of overall hits
+system.cpu.icache.overall_hits::total       516599864                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        11521                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11521                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11521                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11521                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11521                       # number of overall misses
+system.cpu.icache.overall_misses::total         11521                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    285068000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    285068000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    285068000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    285068000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    285068000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    285068000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    516611385                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    516611385                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    516611385                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    516611385                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    516611385                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    516611385                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000022                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000022                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000022                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24743.338252                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24743.338252                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24743.338252                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           11521                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            11521                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           11521                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    250505000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    250505000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    250505000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000022                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000022                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000022                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21743.338252                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21743.338252                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        11521                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        11521                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        11521                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        11521                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        11521                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        11521                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    250505000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    250505000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    250505000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    250505000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    250505000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    250505000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000022                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21743.338252                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21743.338252                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21743.338252                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1134822                       # number of replacements
 system.cpu.dcache.tagsinuse               4065.490059                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                179817787                       # To
 system.cpu.dcache.sampled_refs                1138918                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 157.884753                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            11889987000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4065.490059                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.992551                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              122957659                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              53883046                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits          1488541                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits           1488541                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               176840705                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              176840705                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               782658                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              356260                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1138918                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1138918                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    15502704000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   10028942000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     25531646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    25531646000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          123740317                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          54239306                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses      1488541                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses       1488541                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           177979623                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          177979623                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.006325                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.006568                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.006399                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.006399                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 19807.762778                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 28150.625947                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 22417.457622                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 22417.457622                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4065.490059                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.992551                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.992551                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    122957659                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       122957659                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     53883046                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       53883046                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total      1488541                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total      1488541                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     176840705                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        176840705                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    176840705                       # number of overall hits
+system.cpu.dcache.overall_hits::total       176840705                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       782658                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        782658                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       356260                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       356260                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1138918                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1138918                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1138918                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1138918                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  15502704000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  15502704000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  10028942000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  10028942000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  25531646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  25531646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  25531646000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  25531646000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    123740317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    123740317                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     54239306                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total      1488541                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total      1488541                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    177979623                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    177979623                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    177979623                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    177979623                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.006325                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006568                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.006399                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.006399                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 19807.762778                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28150.625947                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 22417.457622                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 22417.457622                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1025440                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          782658                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         356260                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1138918                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1138918                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  13154730000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8960162000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  22114892000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  22114892000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.006325                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006568                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.006399                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.006399                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 16807.762778                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 25150.625947                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 19417.457622                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1025440                       # number of writebacks
+system.cpu.dcache.writebacks::total           1025440                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       782658                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       782658                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       356260                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       356260                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1138918                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1138918                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1138918                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1138918                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  13154730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  13154730000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8960162000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8960162000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  22114892000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  22114892000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  22114892000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  22114892000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006325                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006568                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006399                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 16807.762778                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 25150.625947                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 19417.457622                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 19417.457622                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                212089                       # number of replacements
 system.cpu.l2cache.tagsinuse             20443.163614                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                 1426644                       # To
 system.cpu.l2cache.sampled_refs                232128                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  6.145937                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          513135223000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          5849.157602                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         14594.006011                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.178502                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.445374                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                683006                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             1025440                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              236229                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 919235                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                919235                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              111173                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            120031                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               231204                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              231204                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    5780996000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   6241612000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    12022608000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   12022608000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            794179                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         1025440                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          356260                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1150439                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1150439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.139985                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.336920                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.200970                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.200970                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 14594.006011                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    132.842413                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   5716.315189                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.445374                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.004054                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.174448                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.623876                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8574                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       674432                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         683006                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      1025440                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      1025440                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       236229                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       236229                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8574                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       910661                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          919235                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8574                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data       910661                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         919235                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2947                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       108226                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       111173                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       120031                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       120031                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2947                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       228257                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        231204                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2947                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       228257                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       231204                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    153244000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   5627752000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   5780996000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6241612000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6241612000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    153244000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  11869364000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  12022608000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    153244000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  11869364000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  12022608000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        11521                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data       782658                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       794179                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      1025440                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      1025440                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       356260                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       356260                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        11521                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1138918                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1150439                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11521                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1138918                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1150439                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.255794                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.138280                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.336920                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.255794                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.200416                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.255794                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.200416                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  172302                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         111173                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       120031                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          231204                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         231204                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   4446920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4801240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   9248160000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   9248160000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.139985                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.336920                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.200970                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.200970                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       172302                       # number of writebacks
+system.cpu.l2cache.writebacks::total           172302                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2947                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       108226                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       111173                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       120031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       120031                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2947                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       228257                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       231204                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2947                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       228257                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       231204                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    117880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   4329040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   4446920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4801240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4801240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    117880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   9130280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   9248160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    117880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   9130280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   9248160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.255794                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.138280                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.336920                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.255794                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.200416                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.255794                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.200416                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8f133335af427a5e40efc17e9c0d4c9b5b6ac5f5..9b1d88e3159f5547e85a40861ffb03c61049d688 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -442,20 +435,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -494,20 +480,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -531,14 +510,14 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
index 1d5281a91e47afb751b6658dc55a08c55cd8aed7..a99eb01f18b8e86d94dca56675bbd699a5e19093 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  9 2012 12:45:55
-gem5 started Feb  9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:22:59
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 6f075b675be4005eab13b5017395bb79b3d51125..e2e62743e4a69194c34075d1aee99d382a74f811 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.488026                       # Nu
 sim_ticks                                488026375000                       # Number of ticks simulated
 final_tick                               488026375000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  87795                       # Simulator instruction rate (inst/s)
-host_tick_rate                               28022613                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 289796                       # Number of bytes of host memory used
-host_seconds                                 17415.45                       # Real time elapsed on the host
-sim_insts                                  1528988756                       # Number of instructions simulated
+host_inst_rate                                 101458                       # Simulator instruction rate (inst/s)
+host_op_rate                                   187607                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               59880945                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257144                       # Number of bytes of host memory used
+host_seconds                                  8149.94                       # Real time elapsed on the host
+sim_insts                                   826877144                       # Number of instructions simulated
+sim_ops                                    1528988756                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    37539712                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 347136                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 26338560                       # Number of bytes written to this memory
@@ -238,7 +240,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.917211                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.675773                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1528988756                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      826877144                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1528988756                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       745779287                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             553                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts          16577287                       # The number of times a branch was mispredicted
@@ -259,7 +262,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    856525585                       # Number of insts commited each cycle
-system.cpu.commit.count                    1528988756                       # Number of instructions committed
+system.cpu.commit.committedInsts            826877144                       # Number of instructions committed
+system.cpu.commit.committedOps             1528988756                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      533262345                       # Number of memory references committed
 system.cpu.commit.loads                     384102160                       # Number of loads committed
@@ -274,12 +278,13 @@ system.cpu.rob.rob_reads                   3076935822                       # Th
 system.cpu.rob.rob_writes                  4651204201                       # The number of ROB writes
 system.cpu.timesIdled                          418807                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                        18030123                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1528988756                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1528988756                       # Number of Instructions Simulated
-system.cpu.cpi                               0.638365                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.638365                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.566502                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.566502                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   826877144                       # Number of Instructions Simulated
+system.cpu.committedOps                    1528988756                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             826877144                       # Number of Instructions Simulated
+system.cpu.cpi                               1.180408                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.180408                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.847164                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.847164                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               3175693593                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1742205758                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       120                       # number of floating regfile reads
@@ -290,26 +295,39 @@ system.cpu.icache.total_refs                193659156                       # To
 system.cpu.icache.sampled_refs                  11601                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               16693.315749                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            973.820201                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.475498                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              193665655                       # number of ReadReq hits
-system.cpu.icache.demand_hits               193665655                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              193665655                       # number of overall hits
-system.cpu.icache.ReadReq_misses               234749                       # number of ReadReq misses
-system.cpu.icache.demand_misses                234749                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses               234749                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     1699920500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      1699920500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     1699920500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          193900404                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           193900404                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          193900404                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.001211                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.001211                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.001211                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  7241.438728                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  7241.438728                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  7241.438728                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     973.820201                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.475498                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.475498                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    193665655                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       193665655                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     193665655                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        193665655                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    193665655                       # number of overall hits
+system.cpu.icache.overall_hits::total       193665655                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       234749                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        234749                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       234749                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         234749                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       234749                       # number of overall misses
+system.cpu.icache.overall_misses::total        234749                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1699920500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1699920500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1699920500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1699920500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1699920500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1699920500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    193900404                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    193900404                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    193900404                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    193900404                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    193900404                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    193900404                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001211                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001211                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001211                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  7241.438728                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  7241.438728                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  7241.438728                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -318,27 +336,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        4                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              2040                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               2040                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              2040                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          232709                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           232709                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          232709                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    952455000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    952455000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    952455000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001200                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.001200                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.001200                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  4092.901435                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  4092.901435                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  4092.901435                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks            4                       # number of writebacks
+system.cpu.icache.writebacks::total                 4                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2040                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2040                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2040                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2040                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2040                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2040                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       232709                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       232709                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       232709                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       232709                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       232709                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       232709                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    952455000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    952455000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    952455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    952455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    952455000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    952455000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001200                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001200                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001200                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  4092.901435                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  4092.901435                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  4092.901435                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2529316                       # number of replacements
 system.cpu.dcache.tagsinuse               4087.520068                       # Cycle average of tags in use
@@ -346,32 +369,49 @@ system.cpu.dcache.total_refs                427611101                       # To
 system.cpu.dcache.sampled_refs                2533412                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 168.788614                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             2115074000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4087.520068                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997930                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              278887188                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             148162157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               427049345                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              427049345                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              2665882                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              998044                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               3663926                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              3663926                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    39487902000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   20586128000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     60074030000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    60074030000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          281553070                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           430713271                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          430713271                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.009468                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.006691                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.008507                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.008507                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 14812.321776                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 20626.473382                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 16396.081689                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 16396.081689                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4087.520068                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997930                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997930                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    278887188                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       278887188                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148162157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148162157                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     427049345                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        427049345                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    427049345                       # number of overall hits
+system.cpu.dcache.overall_hits::total       427049345                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      2665882                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       2665882                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       998044                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       998044                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      3663926                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        3663926                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      3663926                       # number of overall misses
+system.cpu.dcache.overall_misses::total       3663926                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  39487902000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  39487902000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  20586128000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20586128000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  60074030000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  60074030000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  60074030000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  60074030000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    281553070                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    281553070                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    430713271                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    430713271                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    430713271                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    430713271                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.009468                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.006691                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.008507                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.008507                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14812.321776                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 20626.473382                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 16396.081689                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 16396.081689                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -380,32 +420,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  2229932                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            902993                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6453                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             909446                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            909446                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1762889                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         991591                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2754480                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2754480                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  14966916500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  17535799000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  32502715500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  32502715500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.006261                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.006648                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.006395                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.006395                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  8489.993698                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 17684.508028                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 11799.946088                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 11799.946088                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      2229932                       # number of writebacks
+system.cpu.dcache.writebacks::total           2229932                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       902993                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       902993                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6453                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6453                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       909446                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       909446                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       909446                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       909446                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1762889                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1762889                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       991591                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       991591                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2754480                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2754480                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2754480                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2754480                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  14966916500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  14966916500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  17535799000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  17535799000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32502715500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  32502715500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32502715500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  32502715500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.006261                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.006648                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.006395                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.006395                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data  8489.993698                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 17684.508028                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 11799.946088                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 11799.946088                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                575774                       # number of replacements
 system.cpu.l2cache.tagsinuse             21621.732877                       # Cycle average of tags in use
@@ -413,42 +461,85 @@ system.cpu.l2cache.total_refs                 3195554                       # To
 system.cpu.l2cache.sampled_refs                594946                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  5.371166                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          268816776000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7838.250700                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13783.482177                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.239204                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.420638                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1434280                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             2229936                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits               1289                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits              524029                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1958309                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1958309                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              339456                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses           219771                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            247125                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               586581                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              586581                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   11594725000                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency      9650000                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   8467808500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    20062533500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   20062533500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1773736                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         2229936                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses         221060                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          771154                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2544890                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2544890                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.191379                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.994169                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.320461                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.230494                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.230494                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34156.783206                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency    43.909342                       # average UpgradeReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34265.284775                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34202.494626                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34202.494626                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 13783.482177                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     57.596580                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7780.654120                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.420638                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001758                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.237447                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.659843                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         6132                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1428148                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1434280                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2229936                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2229936                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data         1289                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total         1289                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       524029                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       524029                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         6132                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1952177                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1958309                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         6132                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1952177                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1958309                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         5424                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       334032                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       339456                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data       219771                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total       219771                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       247125                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       247125                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         5424                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       581157                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        586581                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         5424                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       581157                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       586581                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    185788500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  11408936500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  11594725000                       # number of ReadReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data      9650000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::total      9650000                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   8467808500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   8467808500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    185788500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  19876745000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  20062533500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    185788500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  19876745000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  20062533500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        11556                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1762180                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1773736                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2229936                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2229936                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data       221060                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total       221060                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       771154                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       771154                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        11556                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2533334                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2544890                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        11556                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2533334                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2544890                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.469367                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.189556                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.994169                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.320461                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.469367                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229404                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.469367                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229404                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.042035                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34155.220159                       # average ReadReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data    43.909342                       # average UpgradeReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34265.284775                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.042035                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34202.022861                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.042035                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34202.022861                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -457,34 +548,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  411540                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         339456                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses       219771                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       247125                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          586581                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         586581                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  10530013500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency   6813351000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   7661828500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  18191842000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  18191842000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191379                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.994169                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.320461                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.230494                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.230494                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31020.260358                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31002.047586                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31003.858371                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31013.350245                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31013.350245                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       411540                       # number of writebacks
+system.cpu.l2cache.writebacks::total           411540                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5424                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       334032                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       339456                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data       219771                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total       219771                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       247125                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       247125                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         5424                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       581157                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       586581                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         5424                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       581157                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       586581                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    168319500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  10361694000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  10530013500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data   6813351000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total   6813351000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7661828500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7661828500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    168319500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  18023522500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  18191842000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    168319500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  18023522500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  18191842000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.469367                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.189556                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.994169                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.320461                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.469367                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229404                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.469367                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229404                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31032.356195                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31020.063946                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31002.047586                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31003.858371                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31032.356195                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31013.172860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31032.356195                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31013.172860                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b1057156b2f73ac65d7e2a6246b6a9cef8f523fd..304b981945b697f848d4eda282361ba00e7230a2 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +97,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +121,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index b86175ab280927fc52eaec8961c57b6056582264..80f8eeac5893d0041467d75b53c45126e406a4d2 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 06:59:28
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:26:26
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 4e0a10e13709f07767b1c6c632fb246d41436d23..8da8b6e9b27c0804b8d4fc18db33b479b3e2b95d 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.885229                       # Nu
 sim_ticks                                885229360000                       # Number of ticks simulated
 final_tick                               885229360000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2258239                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1307438877                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208528                       # Number of bytes of host memory used
-host_seconds                                   677.07                       # Real time elapsed on the host
-sim_insts                                  1528988757                       # Number of instructions simulated
+host_inst_rate                                1663979                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3076883                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1781404357                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214024                       # Number of bytes of host memory used
+host_seconds                                   496.93                       # Real time elapsed on the host
+sim_insts                                   826877145                       # Number of instructions simulated
+sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 10832432532                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             8546776872                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                991849460                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  551                       # Nu
 system.cpu.numCycles                       1770458721                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1528988757                       # Number of instructions executed
+system.cpu.committedInsts                   826877145                       # Number of instructions committed
+system.cpu.committedOps                    1528988757                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index c570a48d2ebed608bd9348be66a2f8682a2fd065..36ec559e81c539e54fb6201d73ffab2af91ae644 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +104,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +118,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +149,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +171,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=parser 2.1.dict -batch
-cwd=build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -191,7 +203,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index a297c4bc8781d029568a558bb7a118e1990ab6b0..a07142e7a60a0d8cf4e8ff5aecff510d96f7666c 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:10:56
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:34:54
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/20.parser/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 28d09902a6446c71248d296726f302731a05d98d..aa053a2736440a8f75534b73bf1217d6406276f2 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.658730                       # Nu
 sim_ticks                                1658729604000                       # Number of ticks simulated
 final_tick                               1658729604000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1326745                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1439324936                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217512                       # Number of bytes of host memory used
-host_seconds                                  1152.44                       # Real time elapsed on the host
-sim_insts                                  1528988757                       # Number of instructions simulated
+host_inst_rate                                1021382                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1888649                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2048908881                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222932                       # Number of bytes of host memory used
+host_seconds                                   809.57                       # Real time elapsed on the host
+sim_insts                                   826877145                       # Number of instructions simulated
+sim_ops                                    1528988757                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    37094976                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 148544                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 26349376                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  551                       # Nu
 system.cpu.numCycles                       3317459208                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1528988757                       # Number of instructions executed
+system.cpu.committedInsts                   826877145                       # Number of instructions committed
+system.cpu.committedOps                    1528988757                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1528317615                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs               1068344296                       # To
 system.cpu.icache.sampled_refs                   2814                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               379653.267946                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            882.231489                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.430777                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1068344296                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1068344296                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1068344296                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 2814                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  2814                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 2814                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      136878000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       136878000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      136878000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1068347110                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1068347110                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1068347110                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 48641.791045                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 48641.791045                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 48641.791045                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     882.231489                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.430777                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.430777                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1068344296                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1068344296                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1068344296                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1068344296                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1068344296                       # number of overall hits
+system.cpu.icache.overall_hits::total      1068344296                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         2814                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          2814                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         2814                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           2814                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         2814                       # number of overall misses
+system.cpu.icache.overall_misses::total          2814                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    136878000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    136878000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    136878000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    136878000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    136878000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    136878000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1068347110                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1068347110                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1068347110                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1068347110                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1068347110                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1068347110                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48641.791045                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48641.791045                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48641.791045                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            2814                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             2814                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            2814                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    128436000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    128436000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    128436000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 45641.791045                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 45641.791045                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         2814                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         2814                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         2814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         2814                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         2814                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         2814                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    128436000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    128436000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    128436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    128436000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    128436000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    128436000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 45641.791045                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2514362                       # number of replacements
 system.cpu.dcache.tagsinuse               4086.472055                       # Cycle average of tags in use
@@ -102,32 +116,49 @@ system.cpu.dcache.total_refs                530743932                       # To
 system.cpu.dcache.sampled_refs                2518458                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 210.741625                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             8216675000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4086.472055                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997674                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              382374775                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             148369157                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               530743932                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              530743932                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1727414                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              791044                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               2518458                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2518458                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    38012508000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   21492013500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     59504521500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    59504521500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          384102189                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         149160201                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           533262390                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          533262390                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.004497                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.005303                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.004723                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.004723                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 22005.441660                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27169.175798                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 23627.363053                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 23627.363053                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4086.472055                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997674                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997674                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    382374775                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       382374775                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    148369157                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      148369157                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     530743932                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        530743932                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    530743932                       # number of overall hits
+system.cpu.dcache.overall_hits::total       530743932                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1727414                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1727414                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       791044                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       791044                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      2518458                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2518458                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2518458                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2518458                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  38012508000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  38012508000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21492013500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  21492013500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  59504521500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  59504521500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  59504521500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  59504521500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    384102189                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    384102189                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    149160201                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    533262390                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    533262390                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    533262390                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    533262390                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004497                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005303                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.004723                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.004723                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22005.441660                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27169.175798                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 23627.363053                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 23627.363053                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  2223170                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1727414                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         791044                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          2518458                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         2518458                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  32830264000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  19118876000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  51949140000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  51949140000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.004497                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005303                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.004723                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.004723                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 19005.440502                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 24169.168845                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 20627.360075                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      2223170                       # number of writebacks
+system.cpu.dcache.writebacks::total           2223170                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1727414                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1727414                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       791044                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       791044                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      2518458                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      2518458                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      2518458                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      2518458                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  32830264000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  32830264000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  19118876000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  19118876000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  51949140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  51949140000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  51949140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  51949140000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.004497                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005303                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.004723                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 19005.440502                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24169.168845                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20627.360075                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20627.360075                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                568906                       # number of replacements
 system.cpu.l2cache.tagsinuse             21228.193311                       # Cycle average of tags in use
@@ -167,36 +200,75 @@ system.cpu.l2cache.total_refs                 3146531                       # To
 system.cpu.l2cache.sampled_refs                587958                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  5.351625                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          896565143000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          7549.128601                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         13679.064710                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.230381                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.417452                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               1398652                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             2223170                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              543011                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                1941663                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               1941663                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses              331576                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            248033                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               579609                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              579609                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   17241952000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  12897722000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    30139674000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   30139674000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1730228                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         2223170                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          791044                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            2521272                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           2521272                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.191637                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.313551                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.229888                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.229888                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52000.024190                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52000.010352                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52000.010352                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 13679.064710                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     30.006309                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   7519.122292                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.417452                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000916                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.229465                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.647833                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          493                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      1398159                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        1398652                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      2223170                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      2223170                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       543011                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       543011                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          493                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      1941170                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         1941663                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          493                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      1941170                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        1941663                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2321                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data       329255                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total       331576                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       248033                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       248033                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2321                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       577288                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        579609                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2321                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       577288                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       579609                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    120692000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  17121260000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  17241952000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  12897722000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  12897722000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    120692000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  30018982000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  30139674000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    120692000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  30018982000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  30139674000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         2814                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1727414                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1730228                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      2223170                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      2223170                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       791044                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       791044                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         2814                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      2518458                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      2521272                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         2814                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      2518458                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      2521272                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.824805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.190606                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.313551                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.824805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.229223                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.824805                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.229223                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000.024190                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.010393                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.010393                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -205,30 +277,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  411709                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses         331576                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       248033                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          579609                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         579609                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  13263040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   9921320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  23184360000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  23184360000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.191637                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.313551                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.229888                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.229888                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       411709                       # number of writebacks
+system.cpu.l2cache.writebacks::total           411709                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2321                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data       329255                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total       331576                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       248033                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       248033                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2321                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       577288                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       579609                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2321                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       577288                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       579609                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     92840000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  13170200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  13263040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   9921320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   9921320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     92840000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  23091520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  23184360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     92840000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  23091520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  23184360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.190606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.313551                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.229223                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.824805                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.229223                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 16e4d1756a5859b1a5c19517e1051290410cd44a..2ad80ff6d62666e0b31552ccf67216b621dd23f7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -202,7 +194,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
index 1c2a18294fd769f76fe73a088991a9de2bbdf930..b600ef5371c84756daeb16505cfed90958be04a8 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:43
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index a04efd18a2f53cca69178033a9ae099fd7306cc9..58ea20ddf2dc6c665509bb2ce809ed79c5b62789 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.139995                       # Nu
 sim_ticks                                139995113500                       # Number of ticks simulated
 final_tick                               139995113500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 118986                       # Simulator instruction rate (inst/s)
-host_tick_rate                               41783300                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214012                       # Number of bytes of host memory used
-host_seconds                                  3350.50                       # Real time elapsed on the host
+host_inst_rate                                 154307                       # Simulator instruction rate (inst/s)
+host_op_rate                                   154307                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54186341                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215920                       # Number of bytes of host memory used
+host_seconds                                  2583.59                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
+sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      469184                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 214784                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -68,9 +70,10 @@ system.cpu.comNops                           23089775                       # Nu
 system.cpu.comNonSpec                             215                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                          112239074                       # Number of Integer instructions committed
 system.cpu.comFloats                         50439198                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                   398664595                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total             398664595                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                   398664595                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                     398664595                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total             398664595                       # Number of Instructions committed (Total)
 system.cpu.cpi                               0.702320                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         0.702320                       # CPI: Total CPI of All Threads
@@ -124,26 +127,39 @@ system.cpu.icache.total_refs                 48855472                       # To
 system.cpu.icache.sampled_refs                   3897                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               12536.687708                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1829.847469                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.893480                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               48855472                       # number of ReadReq hits
-system.cpu.icache.demand_hits                48855472                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               48855472                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 4376                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  4376                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 4376                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      214318500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       214318500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      214318500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           48859848                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            48859848                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           48859848                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000090                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000090                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000090                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 48975.891225                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 48975.891225                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 48975.891225                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1829.847469                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.893480                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.893480                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     48855472                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        48855472                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      48855472                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         48855472                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     48855472                       # number of overall hits
+system.cpu.icache.overall_hits::total        48855472                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4376                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4376                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4376                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4376                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4376                       # number of overall misses
+system.cpu.icache.overall_misses::total          4376                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    214318500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    214318500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    214318500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    214318500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    214318500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    214318500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     48859848                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     48859848                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     48859848                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     48859848                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     48859848                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     48859848                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000090                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000090                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000090                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48975.891225                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 48975.891225                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 48975.891225                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        45000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets        45000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               479                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                479                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               479                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            3897                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             3897                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            3897                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    185285000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    185285000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    185285000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000080                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000080                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000080                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 47545.547857                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 47545.547857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 47545.547857                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          479                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          479                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          479                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          479                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          479                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          479                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3897                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         3897                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         3897                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         3897                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         3897                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         3897                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    185285000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    185285000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    185285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    185285000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    185285000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    185285000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000080                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47545.547857                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47545.547857                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47545.547857                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.tagsinuse               3284.892021                       # Cycle average of tags in use
@@ -180,32 +199,49 @@ system.cpu.dcache.total_refs                168261959                       # To
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               40525.519990                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3284.892021                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.801976                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               94753265                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              73508694                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               168261959                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              168261959                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1224                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               12035                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                 13259                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                13259                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       63830500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     626731500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       690562000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      690562000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           94754489                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          73520729                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           168275218                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          168275218                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000013                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000164                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000079                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000079                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 52149.101307                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 52075.737432                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 52082.509993                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 52082.509993                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3284.892021                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.801976                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.801976                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     94753265                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94753265                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73508694                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73508694                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     168261959                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168261959                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168261959                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168261959                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1224                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1224                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        12035                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        12035                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        13259                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          13259                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        13259                       # number of overall misses
+system.cpu.dcache.overall_misses::total         13259                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     63830500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     63830500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    626731500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    626731500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    690562000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    690562000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    690562000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    690562000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94754489                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94754489                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     73520729                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     73520729                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    168275218                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168275218                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168275218                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168275218                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000013                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000164                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000079                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000079                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52149.101307                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52075.737432                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 52082.509993                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 52082.509993                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets     82468500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 44625.811688                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      649                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               274                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             8833                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               9107                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              9107                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     46185000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    169537500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    215722500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    215722500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48615.789474                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52947.376640                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51956.286127                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51956.286127                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
+system.cpu.dcache.writebacks::total               649                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          274                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          274                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         8833                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         8833                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         9107                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         9107                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         9107                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         9107                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          950                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          950                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     46185000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     46185000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    169537500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    169537500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    215722500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    215722500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    215722500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    215722500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48615.789474                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52947.376640                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51956.286127                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51956.286127                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    13                       # number of replacements
 system.cpu.l2cache.tagsinuse              3900.004949                       # Cycle average of tags in use
@@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs                     729                       # To
 system.cpu.l2cache.sampled_refs                  4720                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.154449                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3529.472340                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           370.532609                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.107711                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011308                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                   658                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  60                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                    718                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                   718                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4186                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              3145                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 7331                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                7331                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     219209500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    164966000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      384175500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     384175500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              4844                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             649                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            3205                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               8049                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              8049                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.864162                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.981279                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.910796                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.910796                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52367.295748                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52453.418124                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52404.242259                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52404.242259                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks   370.532609                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2905.642885                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    623.829454                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.011308                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.088673                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.019038                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.119019                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          541                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          117                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            658                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          649                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          649                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          541                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          177                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             718                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          541                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          177                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            718                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3356                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          830                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4186                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3145                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3145                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3356                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3975                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7331                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3356                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3975                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7331                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    175581500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     43628000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    219209500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    164966000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    164966000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    175581500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    208594000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    384175500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    175581500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    208594000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    384175500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         3897                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          947                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4844                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3205                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         3897                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4152                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8049                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         3897                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4152                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8049                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.861175                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.876452                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981279                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.861175                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.957370                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.861175                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.957370                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52318.682956                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52563.855422                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52453.418124                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52318.682956                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52476.477987                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52318.682956                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52476.477987                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4186                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         3145                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            7331                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           7331                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    168226500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    126764000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    294990500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    294990500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.864162                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981279                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.910796                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.910796                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40187.888199                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40306.518283                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40238.780521                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40238.780521                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3356                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          830                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4186                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3145                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3145                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3356                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3975                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7331                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3356                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3975                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7331                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    134709500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     33517000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    168226500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    126764000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    126764000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    134709500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    160281000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    294990500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    134709500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    160281000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    294990500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.861175                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.876452                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981279                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.861175                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.861175                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40139.898689                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40381.927711                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40306.518283                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40139.898689                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40322.264151                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40139.898689                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40322.264151                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 0fce2844b67c8555a8c40c7e438baf278cda8ad4..c359a496a7969a78d07502ec0f83fbc7ae0ab653 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
index 137fd0ee887dd46766e64fcc7bfc55f63fe5e30a..d3938f0909c384a2599d62b80c0dc9d28716557a 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:45
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 28785f46938436c776a53b4f00f2d12c0876b1ba..e5ff3033e576bd5ce17feb5f40e22b20fd3c605c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.089480                       # Nu
 sim_ticks                                 89480174500                       # Number of ticks simulated
 final_tick                                89480174500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 190161                       # Simulator instruction rate (inst/s)
-host_tick_rate                               45305657                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214676                       # Number of bytes of host memory used
-host_seconds                                  1975.03                       # Real time elapsed on the host
+host_inst_rate                                 246728                       # Simulator instruction rate (inst/s)
+host_op_rate                                   246728                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               58782597                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216860                       # Number of bytes of host memory used
+host_seconds                                  1522.22                       # Real time elapsed on the host
 sim_insts                                   375574794                       # Number of instructions simulated
+sim_ops                                     375574794                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      475840                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 219968                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -271,6 +273,7 @@ system.cpu.iew.wb_rate                       2.269707                       # in
 system.cpu.iew.wb_fanout                     0.713332                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts      398664569                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        398664569                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        60016815                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             215                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           3547729                       # The number of times a branch was mispredicted
@@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    169731918                       # Number of insts commited each cycle
-system.cpu.commit.count                     398664569                       # Number of instructions committed
+system.cpu.commit.committedInsts            398664569                       # Number of instructions committed
+system.cpu.commit.committedOps              398664569                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      168275214                       # Number of memory references committed
 system.cpu.commit.loads                      94754486                       # Number of loads committed
@@ -307,6 +311,7 @@ system.cpu.rob.rob_writes                   926487800                       # Th
 system.cpu.timesIdled                            2712                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          121803                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                   375574794                       # Number of Instructions Simulated
+system.cpu.committedOps                     375574794                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total             375574794                       # Number of Instructions Simulated
 system.cpu.cpi                               0.476497                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         0.476497                       # CPI: Total CPI of All Threads
@@ -324,26 +329,39 @@ system.cpu.icache.total_refs                 57898804                       # To
 system.cpu.icache.sampled_refs                   4037                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               14342.037156                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1834.326922                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.895667                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               57898804                       # number of ReadReq hits
-system.cpu.icache.demand_hits                57898804                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               57898804                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 5282                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  5282                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 5282                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      167914000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       167914000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      167914000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           57904086                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            57904086                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           57904086                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000091                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000091                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000091                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 31789.852329                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 31789.852329                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 31789.852329                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1834.326922                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.895667                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.895667                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     57898804                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        57898804                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      57898804                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         57898804                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     57898804                       # number of overall hits
+system.cpu.icache.overall_hits::total        57898804                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         5282                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          5282                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         5282                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           5282                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         5282                       # number of overall misses
+system.cpu.icache.overall_misses::total          5282                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    167914000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    167914000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    167914000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    167914000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    167914000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    167914000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     57904086                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     57904086                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     57904086                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     57904086                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     57904086                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     57904086                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000091                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000091                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000091                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31789.852329                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 31789.852329                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 31789.852329                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1245                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1245                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1245                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            4037                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             4037                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            4037                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    123459000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    123459000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    123459000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000070                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000070                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000070                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 30581.867724                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 30581.867724                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 30581.867724                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1245                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1245                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1245                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1245                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1245                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1245                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4037                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4037                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4037                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4037                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4037                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4037                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    123459000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    123459000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    123459000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    123459000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    123459000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    123459000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000070                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000070                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000070                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30581.867724                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30581.867724                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30581.867724                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    793                       # number of replacements
 system.cpu.dcache.tagsinuse               3296.196945                       # Cycle average of tags in use
@@ -380,34 +401,53 @@ system.cpu.dcache.total_refs                164730953                       # To
 system.cpu.dcache.sampled_refs                   4193                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               39287.134033                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3296.196945                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.804736                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               91229707                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              73501239                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                7                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               164730946                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              164730946                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1678                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               19489                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                 21167                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                21167                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       55919500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     568883000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       624802500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      624802500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           91231385                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          73520728                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses            7                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           164752113                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          164752113                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000018                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000265                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000128                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000128                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33325.089392                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 29189.953307                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 29517.763500                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 29517.763500                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3296.196945                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.804736                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.804736                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     91229707                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        91229707                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73501239                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73501239                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            7                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            7                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     164730946                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        164730946                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    164730946                       # number of overall hits
+system.cpu.dcache.overall_hits::total       164730946                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1678                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1678                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19489                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19489                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data        21167                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          21167                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        21167                       # number of overall misses
+system.cpu.dcache.overall_misses::total         21167                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     55919500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     55919500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    568883000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    568883000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    624802500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    624802500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    624802500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    624802500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     91231385                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     91231385                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     73520728                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     73520728                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            7                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            7                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    164752113                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    164752113                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    164752113                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    164752113                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000018                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000265                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000128                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000128                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33325.089392                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 29189.953307                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 29517.763500                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 29517.763500                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs        13000                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 5                       # number of cycles access was blocked
@@ -416,32 +456,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs         2600
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      671                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               680                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits            16294                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits              16974                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits             16974                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             998                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           3195                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4193                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4193                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     31703500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    113133500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    144837000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    144837000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000011                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000043                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31767.034068                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35409.546166                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34542.570952                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34542.570952                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          671                       # number of writebacks
+system.cpu.dcache.writebacks::total               671                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          680                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          680                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16294                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16294                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        16974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        16974                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        16974                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        16974                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          998                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          998                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3195                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3195                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4193                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4193                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4193                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4193                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     31703500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     31703500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    113133500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    113133500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    144837000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    144837000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    144837000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    144837000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000011                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31767.034068                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35409.546166                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34542.570952                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34542.570952                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    10                       # number of replacements
 system.cpu.l2cache.tagsinuse              4007.455925                       # Cycle average of tags in use
@@ -449,36 +497,75 @@ system.cpu.l2cache.total_refs                     810                       # To
 system.cpu.l2cache.sampled_refs                  4847                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.167114                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3629.785283                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           377.670641                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.110772                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011526                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                   730                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 671                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  65                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                    795                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                   795                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4305                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              3130                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 7435                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                7435                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     148163500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    108392000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      256555500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     256555500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              5035                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             671                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            3195                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               8230                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              8230                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.855015                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.979656                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.903402                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.903402                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34416.608595                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34630.031949                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34506.455952                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34506.455952                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks   377.670641                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2971.084033                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    658.701251                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.011526                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.090670                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.020102                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.122298                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          600                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          130                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            730                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          671                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          671                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           65                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           65                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          600                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          195                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             795                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          600                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          195                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            795                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3437                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          868                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4305                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3130                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3130                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3437                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3998                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7435                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3437                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3998                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7435                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    118151500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     30012000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    148163500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    108392000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    108392000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    118151500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    138404000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    256555500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    118151500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    138404000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    256555500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4037                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          998                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5035                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          671                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          671                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3195                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3195                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4037                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4193                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8230                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4037                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4193                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8230                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.851375                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.869739                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.979656                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.851375                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.953494                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.851375                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.953494                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34376.345650                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34576.036866                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34630.031949                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34376.345650                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34618.309155                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34376.345650                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34618.309155                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -487,30 +574,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4305                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         3130                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            7435                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           7435                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    134314000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     98534000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    232848000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    232848000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.855015                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.979656                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.903402                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.903402                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31199.535424                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31480.511182                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31317.821116                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31317.821116                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3437                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          868                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4305                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3130                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3130                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3437                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3998                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7435                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3437                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3998                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7435                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    107040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     27274000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    134314000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     98534000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     98534000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    107040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    125808000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    232848000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    107040000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    125808000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    232848000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.851375                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.869739                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.979656                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.851375                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.953494                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.851375                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.953494                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31143.439046                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31421.658986                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31480.511182                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31143.439046                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31467.733867                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31143.439046                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31467.733867                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8310ba9e44c87a08963a1d4c6fb28ec6a51fa9fd..ce995453a8015eda89f176e2eae5d8d28426f643 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
index 3a628f576de78676c1e14bda1b8b87877eaa3fe9..3f05b7dbac821252a71a58178b733b91156e7142 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:11:11
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 3ed2b47f1b4e12d94962a760c1b25617e81cc400..cdec8f7fdf5e7a7fc0956153e2269f5a7e4867f7 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.199332                       # Nu
 sim_ticks                                199332411500                       # Number of ticks simulated
 final_tick                               199332411500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3927016                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1963508553                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204908                       # Number of bytes of host memory used
-host_seconds                                   101.52                       # Real time elapsed on the host
+host_inst_rate                                4966970                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4966969                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2483485434                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206672                       # Number of bytes of host memory used
+host_seconds                                    80.26                       # Real time elapsed on the host
 sim_insts                                   398664595                       # Number of instructions simulated
+sim_ops                                     398664595                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  2257107875                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             1594658604                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                492356798                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                  215                       # Nu
 system.cpu.numCycles                        398664824                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        398664595                       # Number of instructions executed
+system.cpu.committedInsts                   398664595                       # Number of instructions committed
+system.cpu.committedOps                     398664595                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             316365907                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
 system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
index 63aac5a1a591f05ad70b1290fc12d54633de79d4..c8010ddb27b426e1a6e411b542e6bf808318e1bb 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
index 06075d86e55e9a698b09a6c648d44d8e5e8b5084..fe28e85e0480c6edea101edb6985af8c7ba96de3 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:24:12
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:03
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/30.eon/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index af7a7f90dc5c1f922d439869446d1bcc132a02fa..0281e5820edbcaa1d5c192dee5174289daa2affd 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.567343                       # Nu
 sim_ticks                                567343170000                       # Number of ticks simulated
 final_tick                               567343170000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1814376                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2582053806                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213620                       # Number of bytes of host memory used
-host_seconds                                   219.73                       # Real time elapsed on the host
+host_inst_rate                                2193403                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2193403                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3121451222                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215564                       # Number of bytes of host memory used
+host_seconds                                   181.76                       # Real time elapsed on the host
 sim_insts                                   398664609                       # Number of instructions simulated
+sim_ops                                     398664609                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      459520                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 205120                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls                  215                       # Nu
 system.cpu.numCycles                       1134686340                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        398664609                       # Number of instructions executed
+system.cpu.committedInsts                   398664609                       # Number of instructions committed
+system.cpu.committedOps                     398664609                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             316365921                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              155295119                       # Number of float alu accesses
 system.cpu.num_func_calls                    16015498                       # number of times a function call or return occured
@@ -78,26 +81,39 @@ system.cpu.icache.total_refs                398660993                       # To
 system.cpu.icache.sampled_refs                   3673                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               108538.250204                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1795.131074                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.876529                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              398660993                       # number of ReadReq hits
-system.cpu.icache.demand_hits               398660993                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              398660993                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 3673                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  3673                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 3673                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      186032000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       186032000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      186032000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          398664666                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           398664666                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          398664666                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000009                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000009                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 50648.516199                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 50648.516199                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 50648.516199                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1795.131074                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.876529                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.876529                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    398660993                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       398660993                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     398660993                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        398660993                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    398660993                       # number of overall hits
+system.cpu.icache.overall_hits::total       398660993                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         3673                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          3673                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         3673                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           3673                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         3673                       # number of overall misses
+system.cpu.icache.overall_misses::total          3673                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    186032000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    186032000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    186032000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    186032000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    186032000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    186032000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    398664666                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    398664666                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    398664666                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    398664666                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    398664666                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    398664666                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000009                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000009                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000009                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50648.516199                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 50648.516199                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 50648.516199                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            3673                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             3673                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            3673                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    175013000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    175013000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    175013000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000009                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000009                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 47648.516199                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 47648.516199                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3673                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         3673                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         3673                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         3673                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         3673                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         3673                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    175013000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    175013000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    175013000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    175013000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    175013000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    175013000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000009                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47648.516199                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    764                       # number of replacements
 system.cpu.dcache.tagsinuse               3288.912598                       # Cycle average of tags in use
@@ -133,32 +147,49 @@ system.cpu.dcache.total_refs                168271068                       # To
 system.cpu.dcache.sampled_refs                   4152                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               40527.713873                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3288.912598                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.802957                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               94753540                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              73517528                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               168271068                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              168271068                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  950                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                3202                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  4152                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 4152                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       48286000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     176792000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       225078000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      225078000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           94754490                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          73520730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           168275220                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          168275220                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000010                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000044                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 50827.368421                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55212.991880                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54209.537572                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54209.537572                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3288.912598                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.802957                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.802957                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     94753540                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94753540                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     73517528                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       73517528                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     168271068                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        168271068                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    168271068                       # number of overall hits
+system.cpu.dcache.overall_hits::total       168271068                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          950                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           950                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         3202                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         3202                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         4152                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           4152                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         4152                       # number of overall misses
+system.cpu.dcache.overall_misses::total          4152                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     48286000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     48286000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    176792000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    176792000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    225078000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    225078000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    225078000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    225078000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94754490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94754490                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     73520730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     73520730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    168275220                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    168275220                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    168275220                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    168275220                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000010                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000044                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50827.368421                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55212.991880                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54209.537572                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54209.537572                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      649                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             950                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           3202                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4152                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4152                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     45436000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    167186000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    212622000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    212622000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000010                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000044                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 47827.368421                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52212.991880                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51209.537572                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          649                       # number of writebacks
+system.cpu.dcache.writebacks::total               649                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          950                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          950                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         3202                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4152                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4152                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4152                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     45436000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     45436000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    167186000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    167186000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    212622000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    212622000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    212622000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    212622000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000010                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000044                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47827.368421                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52212.991880                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51209.537572                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51209.537572                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    13                       # number of replacements
 system.cpu.l2cache.tagsinuse              3768.712262                       # Cycle average of tags in use
@@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs                     656                       # To
 system.cpu.l2cache.sampled_refs                  4572                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.143482                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3397.175455                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           371.536808                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.103674                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011338                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                   585                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 649                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  60                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                    645                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                   645                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4038                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              3142                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 7180                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                7180                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     209976000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    163384000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      373360000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     373360000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              4623                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             649                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            3202                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               7825                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              7825                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.873459                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.981262                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.917572                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.917572                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks   371.536808                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2770.454482                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    626.720973                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.011338                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.084548                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.019126                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.115012                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst          468                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          117                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total            585                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          649                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          649                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           60                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           60                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst          468                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          177                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total             645                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst          468                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          177                       # number of overall hits
+system.cpu.l2cache.overall_hits::total            645                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3205                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          833                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4038                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         3142                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         3142                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3205                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         3975                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7180                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3205                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         3975                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7180                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    166660000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     43316000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    209976000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    163384000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    163384000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    166660000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    206700000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    373360000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    166660000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    206700000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    373360000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         3673                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          950                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4623                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          649                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         3202                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         3673                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4152                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         7825                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         3673                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4152                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         7825                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.872584                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.876842                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.981262                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.872584                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.957370                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.872584                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.957370                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4038                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         3142                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            7180                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           7180                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    161520000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    125680000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    287200000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    287200000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.873459                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.981262                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.917572                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.917572                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3205                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          833                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4038                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         3142                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         3142                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3205                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         3975                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7180                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3205                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         3975                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7180                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    128200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     33320000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    161520000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    125680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    125680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    128200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    159000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    287200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    128200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    159000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    287200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.876842                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.981262                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.872584                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.957370                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 46adc802eb82cc98e750c909e68c560c1bab9264..3b6ae18fc18c866c5c5b41be4be8c2e1e3f02933 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
index df63c01b76de679dad5e1af69a3959aa7fd2b6d7..347d30ac03b8ba15c55589b1636b9f4932c01a2b 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:57:28
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 44e129451f96735d9e2e1f97fe61ff005eb1c600..242cca72318d758c85070c9604145989ba5c3bc5 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.104493                       # Nu
 sim_ticks                                104492506500                       # Number of ticks simulated
 final_tick                               104492506500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  80425                       # Simulator instruction rate (inst/s)
-host_tick_rate                               24075162                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264476                       # Number of bytes of host memory used
-host_seconds                                  4340.26                       # Real time elapsed on the host
-sim_insts                                   349066034                       # Number of instructions simulated
+host_inst_rate                                 158423                       # Simulator instruction rate (inst/s)
+host_op_rate                                   202536                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               60628822                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231676                       # Number of bytes of host memory used
+host_seconds                                  1723.48                       # Real time elapsed on the host
+sim_insts                                   273038258                       # Number of instructions simulated
+sim_ops                                     349066034                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      464000                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 192512                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.769576                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.508145                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      349066646                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      273038870                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        349066646                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        49103053                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         3555641                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           3227876                       # The number of times a branch was mispredicted
@@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    201258644                       # Number of insts commited each cycle
-system.cpu.commit.count                     349066646                       # Number of instructions committed
+system.cpu.commit.committedInsts            273038870                       # Number of instructions committed
+system.cpu.commit.committedOps              349066646                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      177024831                       # Number of memory references committed
 system.cpu.commit.loads                      94649000                       # Number of loads committed
@@ -316,12 +320,13 @@ system.cpu.rob.rob_reads                    587812621                       # Th
 system.cpu.rob.rob_writes                   803956224                       # The number of ROB writes
 system.cpu.timesIdled                            2582                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          112680                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   349066034                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             349066034                       # Number of Instructions Simulated
-system.cpu.cpi                               0.598698                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.598698                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.670292                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.670292                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   273038258                       # Number of Instructions Simulated
+system.cpu.committedOps                     349066034                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             273038258                       # Number of Instructions Simulated
+system.cpu.cpi                               0.765406                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.765406                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.306497                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.306497                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               1781918480                       # number of integer regfile reads
 system.cpu.int_regfile_writes               235832393                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                 188783884                       # number of floating regfile reads
@@ -334,26 +339,39 @@ system.cpu.icache.total_refs                 41220872                       # To
 system.cpu.icache.sampled_refs                  15988                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                2578.238179                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1842.733120                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.899772                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               41220872                       # number of ReadReq hits
-system.cpu.icache.demand_hits                41220872                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               41220872                       # number of overall hits
-system.cpu.icache.ReadReq_misses                16648                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 16648                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                16648                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      201025000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       201025000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      201025000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           41237520                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            41237520                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           41237520                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000404                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000404                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000404                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 12075.024027                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 12075.024027                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 12075.024027                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1842.733120                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.899772                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.899772                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     41220872                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        41220872                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      41220872                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         41220872                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     41220872                       # number of overall hits
+system.cpu.icache.overall_hits::total        41220872                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        16648                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         16648                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        16648                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          16648                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        16648                       # number of overall misses
+system.cpu.icache.overall_misses::total         16648                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    201025000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    201025000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    201025000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    201025000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    201025000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    201025000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     41237520                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     41237520                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     41237520                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     41237520                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     41237520                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     41237520                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000404                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000404                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000404                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12075.024027                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 12075.024027                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12075.024027                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               637                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                637                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               637                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           16011                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            16011                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           16011                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    135953500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    135953500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    135953500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000388                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000388                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000388                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  8491.256011                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  8491.256011                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  8491.256011                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          637                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          637                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          637                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          637                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          637                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          637                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        16011                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        16011                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        16011                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        16011                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        16011                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        16011                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    135953500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    135953500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    135953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    135953500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    135953500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    135953500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000388                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000388                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000388                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8491.256011                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8491.256011                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8491.256011                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                   1410                       # number of replacements
 system.cpu.dcache.tagsinuse               3098.497902                       # Cycle average of tags in use
@@ -390,40 +411,63 @@ system.cpu.dcache.total_refs                176602100                       # To
 system.cpu.dcache.sampled_refs                   4594                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               38441.902481                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3098.497902                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.756469                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               94546395                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              82033205                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            11358                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             11114                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               176579600                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              176579600                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 3383                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               19489                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                 22872                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                22872                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency      111712500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     649715000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        76000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       761427500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      761427500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           94549778                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          82052694                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        11360                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         11114                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           176602472                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          176602472                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000036                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000238                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000176                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000130                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000130                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33021.726278                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33337.523731                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33290.814096                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33290.814096                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3098.497902                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.756469                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.756469                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     94546395                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94546395                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82033205                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82033205                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        11358                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        11358                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        11114                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        11114                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     176579600                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        176579600                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    176579600                       # number of overall hits
+system.cpu.dcache.overall_hits::total       176579600                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         3383                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          3383                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        19489                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        19489                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data        22872                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total          22872                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data        22872                       # number of overall misses
+system.cpu.dcache.overall_misses::total         22872                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data    111712500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total    111712500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    649715000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    649715000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        76000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        76000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    761427500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    761427500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    761427500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    761427500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94549778                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94549778                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     82052694                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052694                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        11360                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        11360                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        11114                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        11114                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    176602472                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    176602472                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    176602472                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    176602472                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000036                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000238                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000176                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000130                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000130                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33021.726278                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33337.523731                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33290.814096                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33290.814096                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       307500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 27954.545455                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                     1034                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              1633                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits            16622                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits              18255                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits             18255                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses            1750                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           2867                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4617                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4617                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     53344000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    101787500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    155131500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    155131500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000019                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000026                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000026                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 30482.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35503.139170                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33600.064977                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33600.064977                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks         1034                       # number of writebacks
+system.cpu.dcache.writebacks::total              1034                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1633                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1633                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data        16622                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total        16622                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data        18255                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total        18255                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data        18255                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total        18255                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1750                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1750                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2867                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2867                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4617                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4617                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4617                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4617                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     53344000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     53344000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    101787500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    101787500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    155131500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    155131500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    155131500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    155131500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000019                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000026                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 30482.285714                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35503.139170                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33600.064977                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33600.064977                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    57                       # number of replacements
 system.cpu.l2cache.tagsinuse              3892.486015                       # Cycle average of tags in use
@@ -466,39 +519,80 @@ system.cpu.l2cache.total_refs                   13341                       # To
 system.cpu.l2cache.sampled_refs                  5352                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.492713                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3513.908293                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           378.577721                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.107236                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.011553                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 13258                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                1034                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  19                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  13277                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 13277                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4479                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses               23                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses              2826                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 7305                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                7305                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     153679500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     97429500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      251109000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     251109000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             17737                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses            1034                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses             23                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            2845                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              20582                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             20582                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.252523                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.993322                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.354922                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.354922                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34311.118553                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34476.114650                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34374.948665                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34374.948665                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks   378.577721                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2756.979421                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    756.928873                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.011553                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.084136                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.023100                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.118789                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12970                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          288                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          13258                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks         1034                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total         1034                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           19                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           19                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        12970                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          307                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           13277                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12970                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          307                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          13277                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3018                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         1461                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4479                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           23                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           23                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2826                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2826                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3018                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4287                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          7305                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3018                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         4287                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         7305                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    103392000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     50287500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    153679500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     97429500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     97429500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    103392000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    147717000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    251109000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    103392000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    147717000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    251109000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        15988                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1749                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        17737                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks         1034                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total         1034                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           23                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           23                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         2845                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2845                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        15988                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4594                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        20582                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15988                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4594                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        20582                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.188767                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.835334                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.993322                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.188767                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.933174                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.188767                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.933174                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34258.449304                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34419.917864                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34476.114650                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34258.449304                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34456.962911                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34258.449304                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34456.962911                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -507,35 +601,57 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               55                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                55                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               55                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4424                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses           23                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         2826                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            7250                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           7250                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    137822500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       713000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     88418000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    226240500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    226240500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.249422                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.993322                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.352250                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.352250                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31153.367993                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31287.331918                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31205.586207                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31205.586207                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           45                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           55                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           45                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           55                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           45                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           55                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3008                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1416                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4424                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           23                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           23                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2826                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2826                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3008                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4242                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         7250                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3008                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4242                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         7250                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     93473500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     44349000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    137822500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       713000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       713000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     88418000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     88418000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     93473500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    132767000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    226240500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     93473500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    132767000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    226240500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.188141                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.809605                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.993322                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.188141                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.923378                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.188141                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.923378                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31074.966755                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31319.915254                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31287.331918                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31074.966755                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31298.208392                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31074.966755                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31298.208392                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 5628f29f0e93f7022368fa02ec13e893cdf622a7..2d58b995263fb3d48e160c6f136084fb9a8da01a 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index 2369bef1b78e2f3eb8188e838d98afbe621e688a..861cd978dd19fa94309eb3ddd3370e5b4d7ba034 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:01:21
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:59:35
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 7857a903176d5dcc55c5a30a9b7bc39982ca9d16..24bfa1f56c7bbd38c92f9e23cf7a85f2a8443702 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.212344                       # Nu
 sim_ticks                                212344048000                       # Number of ticks simulated
 final_tick                               212344048000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2434260                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1480812932                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218160                       # Number of bytes of host memory used
-host_seconds                                   143.40                       # Real time elapsed on the host
-sim_insts                                   349065408                       # Number of instructions simulated
+host_inst_rate                                2097833                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2681977                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1631504750                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220728                       # Number of bytes of host memory used
+host_seconds                                   130.15                       # Real time elapsed on the host
+sim_insts                                   273037671                       # Number of instructions simulated
+sim_ops                                     349065408                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1875350709                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             1394641440                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                400047783                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  191                       # Nu
 system.cpu.numCycles                        424688097                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        349065408                       # Number of instructions executed
+system.cpu.committedInsts                   273037671                       # Number of instructions committed
+system.cpu.committedOps                     349065408                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             279584926                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
index 28a0917d8e0d8ee9db5f12547ab0460b0b7cdfe8..bc61fa4c6a37a853122a33de80729b9a8c8a64fd 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
-cwd=build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 3428f822471e55001f0317aa2e7ad5a466ba5c4d..aff2d34a5ed1502dccce19ba1dfbf957be6a4c0e 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:03:55
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:01:56
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/30.eon/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 3b365c7592890b71d902744efe13f4818f593d64..bcea217f3c6fd1ae60727e7b9451df80b48ca67f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.525854                       # Nu
 sim_ticks                                525854475000                       # Number of ticks simulated
 final_tick                               525854475000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1206167                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1819018700                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 227092                       # Number of bytes of host memory used
-host_seconds                                   289.09                       # Real time elapsed on the host
-sim_insts                                   348687131                       # Number of instructions simulated
+host_inst_rate                                1153060                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1474144                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2223154070                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229624                       # Number of bytes of host memory used
+host_seconds                                   236.54                       # Real time elapsed on the host
+sim_insts                                   272739291                       # Number of instructions simulated
+sim_ops                                     348687131                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      437312                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 167040                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls                  191                       # Nu
 system.cpu.numCycles                       1051708950                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        348687131                       # Number of instructions executed
+system.cpu.committedInsts                   272739291                       # Number of instructions committed
+system.cpu.committedOps                     348687131                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             279584925                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses              114216705                       # Number of float alu accesses
 system.cpu.num_func_calls                    12433363                       # number of times a function call or return occured
@@ -88,26 +91,39 @@ system.cpu.icache.total_refs                348644756                       # To
 system.cpu.icache.sampled_refs                  15603                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               22344.725758                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1765.984158                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.862297                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              348644756                       # number of ReadReq hits
-system.cpu.icache.demand_hits               348644756                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              348644756                       # number of overall hits
-system.cpu.icache.ReadReq_misses                15603                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 15603                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                15603                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      328062000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       328062000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      328062000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          348660359                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           348660359                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          348660359                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000045                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000045                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000045                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 21025.572005                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 21025.572005                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 21025.572005                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1765.984158                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.862297                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.862297                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    348644756                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       348644756                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     348644756                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        348644756                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    348644756                       # number of overall hits
+system.cpu.icache.overall_hits::total       348644756                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        15603                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         15603                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        15603                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          15603                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        15603                       # number of overall misses
+system.cpu.icache.overall_misses::total         15603                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    328062000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    328062000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    328062000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    328062000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    328062000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    328062000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    348660359                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    348660359                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    348660359                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    348660359                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    348660359                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    348660359                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000045                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000045                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000045                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 21025.572005                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 21025.572005                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 21025.572005                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           15603                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            15603                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           15603                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    281253000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    281253000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    281253000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000045                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000045                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000045                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 18025.572005                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 18025.572005                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        15603                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        15603                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        15603                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        15603                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        15603                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        15603                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    281253000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    281253000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    281253000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    281253000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    281253000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    281253000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000045                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 18025.572005                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 18025.572005                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 18025.572005                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                   1332                       # number of replacements
 system.cpu.dcache.tagsinuse               3078.396238                       # Cycle average of tags in use
@@ -143,36 +157,57 @@ system.cpu.dcache.total_refs                176641600                       # To
 system.cpu.dcache.sampled_refs                   4478                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               39446.538633                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           3078.396238                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.751562                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               94570005                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              82049805                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            10895                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             10895                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               176619810                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              176619810                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1606                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                2872                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  4478                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 4478                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       79898000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     160160000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       240058000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      240058000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           94571611                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          82052677                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        10895                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         10895                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           176624288                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          176624288                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000017                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000035                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 49749.688667                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55766.016713                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 53608.307280                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 53608.307280                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    3078.396238                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.751562                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.751562                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     94570005                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        94570005                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     82049805                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       82049805                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        10895                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        10895                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        10895                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        10895                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     176619810                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        176619810                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    176619810                       # number of overall hits
+system.cpu.dcache.overall_hits::total       176619810                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1606                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1606                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         2872                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         2872                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         4478                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           4478                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         4478                       # number of overall misses
+system.cpu.dcache.overall_misses::total          4478                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     79898000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     79898000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    160160000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    160160000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    240058000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    240058000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    240058000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    240058000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     94571611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     94571611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     82052677                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        10895                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        10895                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    176624288                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    176624288                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    176624288                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    176624288                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000017                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000035                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49749.688667                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55766.016713                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 53608.307280                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 53608.307280                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -181,30 +216,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      998                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses            1606                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           2872                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             4478                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            4478                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     75080000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency    151544000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    226624000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    226624000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000017                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000035                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46749.688667                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52766.016713                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 50608.307280                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          998                       # number of writebacks
+system.cpu.dcache.writebacks::total               998                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data         1606                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total         1606                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         2872                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         2872                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         4478                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         4478                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         4478                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         4478                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     75080000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     75080000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data    151544000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total    151544000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    226624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    226624000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    226624000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    226624000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000017                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000035                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46749.688667                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52766.016713                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50608.307280                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                    48                       # number of replacements
 system.cpu.l2cache.tagsinuse              3475.672922                       # Cycle average of tags in use
@@ -212,36 +249,75 @@ system.cpu.l2cache.total_refs                   13308                       # To
 system.cpu.l2cache.sampled_refs                  4883                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.725374                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3134.059650                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1           341.613272                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.095644                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.010425                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 13232                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 998                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  16                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  13248                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 13248                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3977                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              2856                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 6833                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                6833                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     206804000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency    148512000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      355316000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     355316000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             17209                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             998                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            2872                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              20081                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             20081                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.231100                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.994429                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.340272                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.340272                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks   341.613272                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2402.300580                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    731.759070                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.010425                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.073312                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.022332                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.106069                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        12993                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data          239                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          13232                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          998                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          998                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           16                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           16                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        12993                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data          255                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           13248                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        12993                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data          255                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          13248                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2610                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data         1367                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3977                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         2856                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         2856                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2610                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         4223                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          6833                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2610                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         4223                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         6833                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    135720000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     71084000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    206804000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data    148512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total    148512000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    135720000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    219596000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    355316000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    135720000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    219596000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    355316000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        15603                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data         1606                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        17209                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          998                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          998                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         2872                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         2872                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        15603                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         4478                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        20081                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        15603                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         4478                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        20081                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.167276                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.851183                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994429                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.167276                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.943055                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.167276                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.943055                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -250,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3977                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         2856                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            6833                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           6833                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    159080000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency    114240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    273320000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    273320000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.231100                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994429                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.340272                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.340272                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2610                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data         1367                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3977                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         2856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         2856                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2610                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         4223                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         6833                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2610                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         4223                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         6833                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    104400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     54680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    159080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data    114240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total    114240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    104400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    168920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    273320000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    104400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    168920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    273320000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.167276                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.851183                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994429                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.167276                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.167276                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.943055                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index c87170fbe797d0015e4ac0047a7959b02a8cdc34..2d167e65d4d76040af96165b0d6c2f20f30e4698 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
index 2a099e16b685d177fa3253212c1da0181c8ac4bb..af8dce3f0872319af80b7ca663b170f5c50577b5 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:26:04
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:28
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 90210da82bacd4b8b9ffa0ce99e38f77b2877dbd..4c98d62891236e47e95def59f792c0584873dd8a 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.643030                       # Nu
 sim_ticks                                643030478500                       # Number of ticks simulated
 final_tick                               643030478500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 153915                       # Simulator instruction rate (inst/s)
-host_tick_rate                               54289503                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215008                       # Number of bytes of host memory used
-host_seconds                                 11844.47                       # Real time elapsed on the host
+host_inst_rate                                 198283                       # Simulator instruction rate (inst/s)
+host_op_rate                                   198283                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69939236                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217424                       # Number of bytes of host memory used
+host_seconds                                  9194.13                       # Real time elapsed on the host
 sim_insts                                  1823043370                       # Number of instructions simulated
+sim_ops                                    1823043370                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94779264                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 185664                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
@@ -272,6 +274,7 @@ system.cpu.iew.wb_rate                       1.604576                       # in
 system.cpu.iew.wb_fanout                     0.675414                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     2008987604                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       2008987604                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       979738658                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              39                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts          28886163                       # The number of times a branch was mispredicted
@@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total   1150060787                       # Number of insts commited each cycle
-system.cpu.commit.count                    2008987604                       # Number of instructions committed
+system.cpu.commit.committedInsts           2008987604                       # Number of instructions committed
+system.cpu.commit.committedOps             2008987604                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      721864922                       # Number of memory references committed
 system.cpu.commit.loads                     511070026                       # Number of loads committed
@@ -308,6 +312,7 @@ system.cpu.rob.rob_writes                  6113513811                       # Th
 system.cpu.timesIdled                            3507                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          125916                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1823043370                       # Number of Instructions Simulated
+system.cpu.committedOps                    1823043370                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1823043370                       # Number of Instructions Simulated
 system.cpu.cpi                               0.705447                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         0.705447                       # CPI: Total CPI of All Threads
@@ -325,26 +330,39 @@ system.cpu.icache.total_refs                398299261                       # To
 system.cpu.icache.sampled_refs                   9946                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               40046.175447                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1650.873085                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.806090                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              398299261                       # number of ReadReq hits
-system.cpu.icache.demand_hits               398299261                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              398299261                       # number of overall hits
-system.cpu.icache.ReadReq_misses                11100                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 11100                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                11100                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      182477500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       182477500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      182477500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          398310361                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           398310361                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          398310361                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000028                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000028                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000028                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 16439.414414                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 16439.414414                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 16439.414414                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1650.873085                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.806090                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.806090                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    398299261                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       398299261                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     398299261                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        398299261                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    398299261                       # number of overall hits
+system.cpu.icache.overall_hits::total       398299261                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        11100                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11100                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11100                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11100                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11100                       # number of overall misses
+system.cpu.icache.overall_misses::total         11100                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    182477500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    182477500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    182477500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    182477500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    182477500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    182477500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    398310361                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    398310361                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    398310361                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    398310361                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    398310361                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    398310361                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000028                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000028                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000028                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16439.414414                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16439.414414                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16439.414414                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1153                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1153                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1153                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            9947                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             9947                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            9947                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    119555000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    119555000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    119555000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000025                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 12019.201769                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 12019.201769                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 12019.201769                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1153                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1153                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1153                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1153                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1153                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1153                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9947                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         9947                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         9947                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         9947                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         9947                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         9947                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    119555000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    119555000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    119555000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    119555000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    119555000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    119555000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000025                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12019.201769                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12019.201769                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12019.201769                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1527592                       # number of replacements
 system.cpu.dcache.tagsinuse               4095.113983                       # Cycle average of tags in use
@@ -381,38 +402,59 @@ system.cpu.dcache.total_refs                660890207                       # To
 system.cpu.dcache.sampled_refs                1531688                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 431.478347                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              255376000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.113983                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999784                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              450646939                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             210243259                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               660890198                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              660890198                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1928305                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              551637                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               2479942                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2479942                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    71444429000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   20878144491                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        59000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     92322573491                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    92322573491                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          452575244                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           663370140                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          663370140                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.004261                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.002617                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.003738                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.003738                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 37050.377923                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 37847.614448                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        29500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 37227.714798                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 37227.714798                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4095.113983                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999784                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999784                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    450646939                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       450646939                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    210243259                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      210243259                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     660890198                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        660890198                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    660890198                       # number of overall hits
+system.cpu.dcache.overall_hits::total       660890198                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1928305                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1928305                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       551637                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       551637                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2479942                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2479942                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2479942                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2479942                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  71444429000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  71444429000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  20878144491                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  20878144491                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        59000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        59000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  92322573491                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  92322573491                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  92322573491                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  92322573491                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    452575244                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    452575244                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    663370140                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    663370140                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    663370140                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    663370140                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004261                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002617                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.003738                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.003738                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37050.377923                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37847.614448                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        29500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37227.714798                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37227.714798                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs        79500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        20500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                14                       # number of cycles access was blocked
@@ -421,37 +463,48 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  5678.571429
 system.cpu.dcache.avg_blocked_cycles::no_targets        20500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   107326                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            468223                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           480032                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            1                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             948255                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            948255                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1460082                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          71605                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1531687                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1531687                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  49942277500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2493130000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  52435407500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  52435407500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.003226                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000340                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.090909                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002309                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002309                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34205.118274                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34817.819985                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34233.761532                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34233.761532                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       107326                       # number of writebacks
+system.cpu.dcache.writebacks::total            107326                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       468223                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       468223                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       480032                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       480032                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            1                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       948255                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       948255                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       948255                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       948255                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460082                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1460082                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71605                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71605                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1531687                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1531687                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1531687                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1531687                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  49942277500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  49942277500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2493130000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2493130000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        35000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        35000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52435407500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  52435407500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52435407500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  52435407500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.003226                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000340                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.090909                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002309                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002309                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34205.118274                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34817.819985                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        35000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34233.761532                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34233.761532                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1480630                       # number of replacements
 system.cpu.l2cache.tagsinuse             31935.913288                       # Cycle average of tags in use
@@ -459,36 +512,75 @@ system.cpu.l2cache.total_refs                   63583                       # To
 system.cpu.l2cache.sampled_refs               1513317                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.042016                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         28876.475418                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3059.437870                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.881240                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.093367                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 55959                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              107326                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                4750                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  60709                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 60709                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1414071                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             66855                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1480926                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1480926                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   48513510000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2349021500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    50862531500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   50862531500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1470030                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          107326                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           71605                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1541635                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1541635                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.961933                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.933664                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.960620                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.960620                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34307.690349                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 35136.063122                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34345.086453                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34345.086453                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  3059.437870                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     43.056925                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  28833.418493                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.093367                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001314                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.879926                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.974607                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         7046                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        48913                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          55959                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       107326                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       107326                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4750                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4750                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         7046                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        53663                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           60709                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         7046                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        53663                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          60709                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2901                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1411170                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1414071                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66855                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66855                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2901                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1478025                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1480926                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2901                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1478025                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1480926                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     99564500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48413945500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  48513510000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2349021500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2349021500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     99564500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  50762967000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  50862531500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     99564500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  50762967000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  50862531500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         9947                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1460083                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1470030                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       107326                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       107326                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        71605                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        71605                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         9947                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1531688                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1541635                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         9947                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1531688                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1541635                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.291646                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.966500                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.933664                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.291646                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964965                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.291646                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964965                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34320.751465                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34307.663499                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35136.063122                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34320.751465                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34345.134216                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34320.751465                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34345.134216                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs        37500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                5                       # number of cycles access was blocked
@@ -497,30 +589,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs         7500
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   66898                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1414071                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66855                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1480926                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1480926                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  43837380500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2147695000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  45985075500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  45985075500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.961933                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.933664                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.960620                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.960620                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31000.834117                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 32124.672799                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31051.568748                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31051.568748                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2901                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1411170                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1414071                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66855                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66855                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2901                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1478025                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1480926                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2901                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1478025                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1480926                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     90197000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43747183500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43837380500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2147695000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2147695000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     90197000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  45894878500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  45985075500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     90197000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  45894878500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  45985075500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.291646                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.966500                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.933664                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.291646                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964965                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.291646                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964965                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31091.692520                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31000.647335                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32124.672799                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31091.692520                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31051.489995                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31091.692520                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31051.489995                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index a895468a4f8923a0f1e7f4db7be0258f785483b1..e114fdc815d8891870ea177215362f658f29336e 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
index 67c7a90bddf2c99006b9319d3eefa54359356391..d7926f03a0319c9b8c779d0dbff9b2a914903941 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:26:36
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:12:42
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 5a9e50b92deca8ea2f0f16744972f08aa896ead1..4c63884c798c961ba219d95d4dd603b3ec88c455 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.004711                       # Nu
 sim_ticks                                1004710587000                       # Number of ticks simulated
 final_tick                               1004710587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4051601                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2026237516                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204820                       # Number of bytes of host memory used
-host_seconds                                   495.85                       # Real time elapsed on the host
+host_inst_rate                                5076159                       # Simulator instruction rate (inst/s)
+host_op_rate                                  5076159                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2538627026                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 206544                       # Number of bytes of host memory used
+host_seconds                                   395.77                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
+sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 11607100996                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             8037684280                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written               1586125963                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   39                       # Nu
 system.cpu.numCycles                       2009421175                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       2008987605                       # Number of instructions executed
+system.cpu.committedInsts                  2008987605                       # Number of instructions committed
+system.cpu.committedOps                    2008987605                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
 system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
index f60b7883772802d3e5244e6247e18ee390f866e3..794cf18d1a8cbbc133b48106dbe1fc21ff6ed31c 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
index e767ec1c44f581d5be74f84fcdb5328d36f7099d..25b9957936075e5f09c8adaea1229e7f64e18d42 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:28:03
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:14:25
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 668a6f1dd9542fe4df3a8cecba7d9a03f78b582c..19236d33887d3acb24c1ad0e27fe71f99eb711a0 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.813468                       # Nu
 sim_ticks                                2813467842000                       # Number of ticks simulated
 final_tick                               2813467842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1954286                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2736861040                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213480                       # Number of bytes of host memory used
-host_seconds                                  1027.99                       # Real time elapsed on the host
+host_inst_rate                                2306294                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2306294                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3229827855                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 215660                       # Number of bytes of host memory used
+host_seconds                                   871.09                       # Real time elapsed on the host
 sim_insts                                  2008987605                       # Number of instructions simulated
+sim_ops                                    2008987605                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94708160                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 152128                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  4281472                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   39                       # Nu
 system.cpu.numCycles                       5626935684                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       2008987605                       # Number of instructions executed
+system.cpu.committedInsts                  2008987605                       # Number of instructions committed
+system.cpu.committedOps                    2008987605                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1779374816                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               71831671                       # Number of float alu accesses
 system.cpu.num_func_calls                    79910682                       # number of times a function call or return occured
@@ -79,26 +82,39 @@ system.cpu.icache.total_refs               2009410475                       # To
 system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               189638.587675                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1478.423269                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.721886                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             2009410475                       # number of ReadReq hits
-system.cpu.icache.demand_hits              2009410475                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             2009410475                       # number of overall hits
-system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                10596                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      248178000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       248178000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      248178000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         2009421071                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          2009421071                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         2009421071                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23421.857305                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23421.857305                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23421.857305                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1478.423269                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.721886                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.721886                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   2009410475                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      2009410475                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    2009410475                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       2009410475                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   2009410475                       # number of overall hits
+system.cpu.icache.overall_hits::total      2009410475                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        10596                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         10596                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        10596                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          10596                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        10596                       # number of overall misses
+system.cpu.icache.overall_misses::total         10596                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    248178000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    248178000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    248178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    248178000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    248178000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    248178000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   2009421071                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   2009421071                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   2009421071                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   2009421071                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   2009421071                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   2009421071                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23421.857305                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23421.857305                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23421.857305                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    216390000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    216390000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    216390000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20421.857305                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20421.857305                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10596                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10596                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10596                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10596                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10596                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10596                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    216390000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    216390000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    216390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    216390000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    216390000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000005                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20421.857305                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1526048                       # number of replacements
 system.cpu.dcache.tagsinuse               4095.204626                       # Cycle average of tags in use
@@ -134,32 +148,49 @@ system.cpu.dcache.total_refs                720334778                       # To
 system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             1049839000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4095.204626                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999806                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              720334778                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1530144                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    79658418000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3815994000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     83474412000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    83474412000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 54628.209454                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 53035.273516                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54553.304787                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54553.304787                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4095.204626                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999806                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    509611834                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       509611834                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    210722944                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      210722944                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     720334778                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        720334778                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    720334778                       # number of overall hits
+system.cpu.dcache.overall_hits::total       720334778                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1458192                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1458192                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        71952                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        71952                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1530144                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1530144                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1530144                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1530144                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79658418000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79658418000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3815994000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3815994000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83474412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83474412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83474412000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83474412000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002853                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000341                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002120                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002120                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54628.209454                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 53035.273516                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54553.304787                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54553.304787                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   107612                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  75283842000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3600138000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  78883980000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  78883980000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51628.209454                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50035.273516                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51553.304787                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       107612                       # number of writebacks
+system.cpu.dcache.writebacks::total            107612                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1458192                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1458192                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1530144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1530144                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75283842000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75283842000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3600138000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3600138000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78883980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  78883980000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78883980000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  78883980000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002853                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002120                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51628.209454                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50035.273516                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51553.304787                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51553.304787                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1479797                       # number of replacements
 system.cpu.l2cache.tagsinuse             31929.841726                       # Cycle average of tags in use
@@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs                   63431                       # To
 system.cpu.l2cache.sampled_refs               1512480                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.041938                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         28848.012979                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3081.828747                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.880371                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.094050                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 55846                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              107612                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                5079                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  60925                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 60925                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1412942                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             66873                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1479815                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1479815                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   73472984000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3477396000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    76950380000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   76950380000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1468788                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          107612                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           71952                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1540740                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.961978                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.929411                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.960457                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.960457                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  3081.828747                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     33.409968                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  28814.603011                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.094050                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001020                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.879352                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.974421                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8219                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        47627                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          55846                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       107612                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       107612                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         5079                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         5079                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         8219                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        52706                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           60925                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8219                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        52706                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          60925                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2377                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1410565                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1412942                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66873                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66873                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2377                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1477438                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1479815                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2377                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1477438                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1479815                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    123604000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73349380000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  73472984000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3477396000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3477396000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    123604000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  76826776000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  76950380000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    123604000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  76826776000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  76950380000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10596                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1458192                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1468788                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       107612                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       107612                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        71952                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        71952                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        10596                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1530144                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1540740                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10596                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1530144                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1540740                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.224330                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.967338                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.929411                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.224330                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.965555                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.224330                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.965555                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   66898                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1412942                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66873                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1479815                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1479815                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56517680000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2674920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  59192600000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  59192600000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.961978                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.929411                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.960457                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.960457                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        66898                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66898                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2377                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1410565                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1412942                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66873                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66873                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2377                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1477438                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1479815                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2377                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1477438                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1479815                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     95080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56422600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56517680000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2674920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     95080000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59097520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  59192600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     95080000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59097520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  59192600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.967338                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.929411                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.965555                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.224330                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.965555                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 78c85cac98bb6c3fbc34b459b546750a3c88bfbd..3a59e4035e0881fe70c375a84e4e3751a2e7cc31 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
index 76bc74d1eb65f35646c0ae07768bb652a29f8a08..96ddf0fe46faecfec433d77588eccdfe17bcc040 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:06:03
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 801f115d2d9d90a7cff60e0aaebbe0e924eef5fd..b8fd6e3440fed755d438b0c0acfa9ba80e7f71cf 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.708285                       # Nu
 sim_ticks                                708285420500                       # Number of ticks simulated
 final_tick                               708285420500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  74841                       # Simulator instruction rate (inst/s)
-host_tick_rate                               28116271                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262240                       # Number of bytes of host memory used
-host_seconds                                 25191.30                       # Real time elapsed on the host
-sim_insts                                  1885333786                       # Number of instructions simulated
+host_inst_rate                                 110657                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150700                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               56615274                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229476                       # Number of bytes of host memory used
+host_seconds                                 12510.50                       # Real time elapsed on the host
+sim_insts                                  1384379033                       # Number of instructions simulated
+sim_ops                                    1885333786                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94806144                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 201024                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  4230336                       # Number of bytes written to this memory
@@ -281,7 +283,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.741158                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.534869                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1885344802                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts     1384390049                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1885344802                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts      1192760864                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls          211330                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts          38418907                       # The number of times a branch was mispredicted
@@ -302,7 +305,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total   1198732893                       # Number of insts commited each cycle
-system.cpu.commit.count                    1885344802                       # Number of instructions committed
+system.cpu.commit.committedInsts           1384390049                       # Number of instructions committed
+system.cpu.commit.committedOps             1885344802                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      908385853                       # Number of memory references committed
 system.cpu.commit.loads                     631388869                       # Number of loads committed
@@ -317,12 +321,13 @@ system.cpu.rob.rob_reads                   4196573290                       # Th
 system.cpu.rob.rob_writes                  6322749564                       # The number of ROB writes
 system.cpu.timesIdled                         1340847                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                        51326273                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1885333786                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1885333786                       # Number of Instructions Simulated
-system.cpu.cpi                               0.751363                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.751363                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.330914                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.330914                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                  1384379033                       # Number of Instructions Simulated
+system.cpu.committedOps                    1885333786                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total            1384379033                       # Number of Instructions Simulated
+system.cpu.cpi                               1.023254                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.023254                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.977275                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.977275                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads              12567200244                       # number of integer regfile reads
 system.cpu.int_regfile_writes              2359430733                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                  68800397                       # number of floating regfile reads
@@ -335,26 +340,39 @@ system.cpu.icache.total_refs                384162744                       # To
 system.cpu.icache.sampled_refs                  28920                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               13283.635685                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1638.335274                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.799968                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              384163979                       # number of ReadReq hits
-system.cpu.icache.demand_hits               384163979                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              384163979                       # number of overall hits
-system.cpu.icache.ReadReq_misses                34037                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 34037                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                34037                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      300707500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       300707500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      300707500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          384198016                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           384198016                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          384198016                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000089                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000089                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000089                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  8834.723977                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  8834.723977                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  8834.723977                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1638.335274                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.799968                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.799968                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    384163979                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       384163979                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     384163979                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        384163979                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    384163979                       # number of overall hits
+system.cpu.icache.overall_hits::total       384163979                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        34037                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         34037                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        34037                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          34037                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        34037                       # number of overall misses
+system.cpu.icache.overall_misses::total         34037                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    300707500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    300707500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    300707500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    300707500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    300707500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    300707500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    384198016                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    384198016                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    384198016                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    384198016                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    384198016                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    384198016                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000089                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000089                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000089                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  8834.723977                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  8834.723977                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  8834.723977                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -363,27 +381,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               775                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                775                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               775                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           33262                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            33262                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           33262                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    180621500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    180621500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    180621500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000087                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000087                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000087                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  5430.265769                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  5430.265769                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  5430.265769                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          775                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          775                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          775                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          775                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          775                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          775                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        33262                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        33262                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        33262                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        33262                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        33262                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        33262                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    180621500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    180621500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    180621500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    180621500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    180621500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    180621500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000087                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  5430.265769                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  5430.265769                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  5430.265769                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1531781                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.791758                       # Cycle average of tags in use
@@ -391,40 +412,63 @@ system.cpu.dcache.total_refs               1029515809                       # To
 system.cpu.dcache.sampled_refs                1535877                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 670.311365                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              305571000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.791758                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999705                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              753356755                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             276118556                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            15246                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             11672                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits              1029475311                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits             1029475311                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1938073                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              817122                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               2755195                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              2755195                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    69347083500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   28485572000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       108500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     97832655500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    97832655500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          755294828                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        15249                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         11672                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses          1032230506                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses         1032230506                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002566                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.002951                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000197                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.002669                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002669                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35781.461018                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 34860.855539                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 36166.666667                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35508.432434                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35508.432434                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.791758                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999705                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999705                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    753356755                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       753356755                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    276118556                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      276118556                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15246                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15246                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        11672                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        11672                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data    1029475311                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total       1029475311                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data   1029475311                       # number of overall hits
+system.cpu.dcache.overall_hits::total      1029475311                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1938073                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1938073                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       817122                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       817122                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      2755195                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        2755195                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      2755195                       # number of overall misses
+system.cpu.dcache.overall_misses::total       2755195                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  69347083500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  69347083500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  28485572000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  28485572000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       108500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       108500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  97832655500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  97832655500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  97832655500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  97832655500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    755294828                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    755294828                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15249                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15249                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        11672                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        11672                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data   1032230506                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total   1032230506                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data   1032230506                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total   1032230506                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002566                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.002951                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000197                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002669                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002669                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35781.461018                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34860.855539                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 36166.666667                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35508.432434                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35508.432434                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        62000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -433,33 +477,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets        15500                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   106815                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            474897                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           740078                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1214975                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1214975                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1463176                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          77044                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1540220                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1540220                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  50021914000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   2483063000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  52504977000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  52504977000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001937                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000278                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001492                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001492                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34187.216029                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 32229.154769                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34089.271013                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34089.271013                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       106815                       # number of writebacks
+system.cpu.dcache.writebacks::total            106815                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       474897                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       474897                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       740078                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       740078                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1214975                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1214975                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1214975                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1214975                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1463176                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1463176                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        77044                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        77044                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1540220                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1540220                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1540220                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1540220                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  50021914000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  50021914000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   2483063000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   2483063000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  52504977000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  52504977000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  52504977000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  52504977000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001937                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000278                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001492                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001492                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34187.216029                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32229.154769                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34089.271013                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34089.271013                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1480005                       # number of replacements
 system.cpu.l2cache.tagsinuse             31970.457215                       # Cycle average of tags in use
@@ -467,40 +520,82 @@ system.cpu.l2cache.total_refs                   85123                       # To
 system.cpu.l2cache.sampled_refs               1512725                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.056271                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         29003.484666                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          2966.972548                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.885116                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.090545                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 76806                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              106815                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits                  4                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits                6620                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  83426                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 83426                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1415291                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses             4338                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses             66082                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1481373                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1481373                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   48556724500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   2252633500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    50809358000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   50809358000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1492097                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          106815                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses           4342                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           72702                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1564799                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1564799                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.948525                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.999079                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.908943                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.946686                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.946686                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34308.650659                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34088.458279                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34298.828182                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34298.828182                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  2966.972548                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     53.821499                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  28949.663167                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.090545                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.001643                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.883474                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.975661                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        25776                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        51030                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          76806                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       106815                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       106815                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data            4                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total            4                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         6620                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         6620                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        25776                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        57650                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           83426                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        25776                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        57650                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          83426                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3145                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1412146                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1415291                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         4338                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total         4338                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66082                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3145                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1478228                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1481373                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3145                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1478228                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1481373                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    107831000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  48448893500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  48556724500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   2252633500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   2252633500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    107831000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  50701527000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  50809358000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    107831000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  50701527000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  50809358000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        28921                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1463176                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1492097                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       106815                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       106815                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data         4342                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total         4342                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        72702                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        72702                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        28921                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1535878                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1564799                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        28921                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1535878                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1564799                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.108745                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.965124                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.999079                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.908943                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.108745                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.962464                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.108745                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.962464                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34286.486486                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34308.700021                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34088.458279                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34286.486486                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34298.854439                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34286.486486                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34298.854439                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -509,35 +604,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   66099                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               27                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                27                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               27                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1415264                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses         4338                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66082                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1481346                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1481346                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  43971004500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency    134478000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2048597500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  46019602000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  46019602000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.948507                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.999079                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908943                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.946669                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.946669                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31069.118200                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31000.839866                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31066.072342                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31066.072342                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            4                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           23                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           27                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            4                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           23                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           27                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            4                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           23                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           27                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3141                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1412123                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1415264                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         4338                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total         4338                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3141                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1478205                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1481346                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3141                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1478205                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1481346                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     97624500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  43873380000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  43971004500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data    134478000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total    134478000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2048597500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2048597500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     97624500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  45921977500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  46019602000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     97624500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  45921977500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  46019602000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.108606                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.965108                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.999079                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.908943                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.108606                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.962449                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.108606                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.962449                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31080.706781                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31069.092423                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31000.839866                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31080.706781                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31066.041246                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31080.706781                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31066.041246                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 6a275dc9a78eee2d722f334c04b2535c5d726c7d..3b002044343ef2c156f705d2bb2b244ae313ad48 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index dd29e750ea77e241284793815c1460c465074241..31662be21bb4955b721159d902b6ef69feeee0ff 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:17:45
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:09:56
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 49ae2817eb1b936ca972bfb0daea95e88f4ebba5..a0e247e5f3bba2e20f94cec8b1bdb6eb2d3519ec 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.945613                       # Nu
 sim_ticks                                945613131000                       # Number of ticks simulated
 final_tick                               945613131000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2997522                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1503443037                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215364                       # Number of bytes of host memory used
-host_seconds                                   628.97                       # Real time elapsed on the host
-sim_insts                                  1885336367                       # Number of instructions simulated
+host_inst_rate                                2494982                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3397821                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1704217996                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217680                       # Number of bytes of host memory used
+host_seconds                                   554.87                       # Real time elapsed on the host
+sim_insts                                  1384381614                       # Number of instructions simulated
+sim_ops                                    1885336367                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  8025491315                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             5561086040                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written               1123958396                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                 1411                       # Nu
 system.cpu.numCycles                       1891226263                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1885336367                       # Number of instructions executed
+system.cpu.committedInsts                  1384381614                       # Number of instructions committed
+system.cpu.committedOps                    1885336367                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
 system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
index 01aaafc037830589388fa7f167d55c8981e07b26..62f983a260962cb1fec60b53de2e7f4453c50f7a 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index df0dd80b935ae3c22aeb1fd7fabdb04b761665c2..608f1b6735688ba30cce98aeb8482bca81fc2869 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:28:26
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:19:22
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/40.perlbmk/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 117215dc5c6dfa6429f07a8357ee0888ea2c8275..70fd39037340061612e024a416348e26f57deace 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.369902                       # Nu
 sim_ticks                                2369901960000                       # Number of ticks simulated
 final_tick                               2369901960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1407810                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1780114775                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224180                       # Number of bytes of host memory used
-host_seconds                                  1331.32                       # Real time elapsed on the host
-sim_insts                                  1874244950                       # Number of instructions simulated
+host_inst_rate                                1307856                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1774200                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2243399723                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226844                       # Number of bytes of host memory used
+host_seconds                                  1056.39                       # Real time elapsed on the host
+sim_insts                                  1381604347                       # Number of instructions simulated
+sim_ops                                    1874244950                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    94696320                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 144448                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  4230336                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                 1411                       # Nu
 system.cpu.numCycles                       4739803920                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1874244950                       # Number of instructions executed
+system.cpu.committedInsts                  1381604347                       # Number of instructions committed
+system.cpu.committedOps                    1874244950                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1653698876                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses               52289415                       # Number of float alu accesses
 system.cpu.num_func_calls                    80344203                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs               1390251708                       # To
 system.cpu.icache.sampled_refs                  19803                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               70204.095743                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1392.324437                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.679846                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1390251708                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1390251708                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1390251708                       # number of overall hits
-system.cpu.icache.ReadReq_misses                19803                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 19803                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                19803                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      372036000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       372036000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      372036000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1390271511                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1390271511                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1390271511                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000014                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000014                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000014                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 18786.850477                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 18786.850477                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 18786.850477                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1392.324437                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.679846                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.679846                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1390251708                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1390251708                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1390251708                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1390251708                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1390251708                       # number of overall hits
+system.cpu.icache.overall_hits::total      1390251708                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        19803                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         19803                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        19803                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          19803                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        19803                       # number of overall misses
+system.cpu.icache.overall_misses::total         19803                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    372036000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    372036000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    372036000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    372036000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    372036000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    372036000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1390271511                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1390271511                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1390271511                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1390271511                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1390271511                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1390271511                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000014                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000014                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000014                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18786.850477                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18786.850477                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18786.850477                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           19803                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            19803                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           19803                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    312627000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    312627000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    312627000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000014                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000014                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000014                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15786.850477                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15786.850477                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        19803                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        19803                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        19803                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        19803                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        19803                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        19803                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    312627000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    312627000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    312627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    312627000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    312627000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    312627000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000014                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15786.850477                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15786.850477                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15786.850477                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1529557                       # number of replacements
 system.cpu.dcache.tagsinuse               4094.960333                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                895757409                       # To
 system.cpu.dcache.sampled_refs                1533653                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 584.067849                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              997882000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4094.960333                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999746                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              618874541                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             276862898                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits             9985                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits              9985                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               895737439                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              895737439                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              1460873                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses               72780                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1533653                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1533653                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    79725982000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    3794826000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     83520808000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    83520808000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          620335414                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         276935678                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses         9985                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses          9985                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           897271092                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          897271092                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002355                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000263                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.001709                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.001709                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 54574.204602                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 52141.055235                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54458.738711                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54458.738711                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4094.960333                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999746                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999746                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    618874541                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       618874541                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    276862898                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      276862898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data         9985                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total         9985                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data         9985                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total         9985                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     895737439                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        895737439                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    895737439                       # number of overall hits
+system.cpu.dcache.overall_hits::total       895737439                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      1460873                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       1460873                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data        72780                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total        72780                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1533653                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1533653                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1533653                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1533653                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  79725982000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  79725982000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   3794826000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   3794826000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  83520808000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  83520808000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  83520808000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  83520808000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    620335414                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    620335414                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    276935678                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data         9985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total         9985                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data         9985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total         9985                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    897271092                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    897271092                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    897271092                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    897271092                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002355                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000263                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.001709                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.001709                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54574.204602                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52141.055235                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54458.738711                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54458.738711                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   107259                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1460873                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses          72780                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1533653                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1533653                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  75343363000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3576486000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  78919849000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  78919849000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002355                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000263                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.001709                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.001709                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 51574.204602                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49141.055235                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51458.738711                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       107259                       # number of writebacks
+system.cpu.dcache.writebacks::total            107259                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1460873                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1460873                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data        72780                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total        72780                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1533653                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1533653                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1533653                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1533653                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  75343363000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  75343363000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3576486000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  78919849000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  78919849000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  78919849000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  78919849000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002355                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000263                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001709                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51574.204602                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49141.055235                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51458.738711                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51458.738711                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               1478755                       # number of replacements
 system.cpu.l2cache.tagsinuse             31934.844118                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                   75453                       # To
 system.cpu.l2cache.sampled_refs               1511475                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.049920                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         28893.420796                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1          3041.423322                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.881757                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.092817                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 67139                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              107259                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                6687                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  73826                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 73826                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1413537                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses             66093                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              1479630                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             1479630                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   73503924000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3436836000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    76940760000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   76940760000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           1480676                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          107259                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses           72780                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            1553456                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           1553456                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.954657                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.908120                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.952476                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.952476                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks  3041.423322                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     32.598415                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  28860.822381                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.092817                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000995                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.880762                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.974574                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        17546                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        49593                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          67139                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       107259                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       107259                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         6687                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         6687                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        17546                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        56280                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           73826                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        17546                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        56280                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          73826                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2257                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1411280                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1413537                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data        66093                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total        66093                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2257                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      1477373                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       1479630                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2257                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      1477373                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      1479630                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    117364000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  73386560000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  73503924000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3436836000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3436836000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    117364000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  76823396000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  76940760000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    117364000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  76823396000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  76940760000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        19803                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      1460873                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      1480676                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       107259                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       107259                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data        72780                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total        72780                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        19803                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      1533653                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      1553456                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        19803                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      1533653                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      1553456                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.113973                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.966052                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.908120                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.113973                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.963303                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.113973                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.963303                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   66099                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1413537                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses        66093                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         1479630                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        1479630                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56541480000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   2643720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  59185200000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  59185200000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.954657                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.908120                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.952476                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.952476                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        66099                       # number of writebacks
+system.cpu.l2cache.writebacks::total            66099                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2257                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1411280                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1413537                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data        66093                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total        66093                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2257                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      1477373                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      1479630                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2257                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      1477373                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      1479630                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     90280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56451200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56541480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   2643720000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   2643720000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     90280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  59094920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  59185200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     90280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  59094920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  59185200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.966052                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.908120                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963303                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.113973                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963303                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 1b963b10cf886d673ce194e864501d5f571cd092..90c413b6536eed0f76338190df0ff3dd4a7f3eb7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -202,7 +194,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
index 0aab67a06114c72c0d75b58e3a7ef81f5fc5a0eb..8786d03ec06f2dbd9aea5b9445586f3fdbf94051 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:28:56
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:15:15
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 32a07ce20401e57e136a770357292de182327453..22fcb32bda1a014afd84620b1b78d8faa1999cd3 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.046914                       # Nu
 sim_ticks                                 46914279500                       # Number of ticks simulated
 final_tick                                46914279500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 107347                       # Simulator instruction rate (inst/s)
-host_tick_rate                               57007816                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216192                       # Number of bytes of host memory used
-host_seconds                                   822.94                       # Real time elapsed on the host
+host_inst_rate                                 145791                       # Simulator instruction rate (inst/s)
+host_op_rate                                   145791                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               77424105                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218104                       # Number of bytes of host memory used
+host_seconds                                   605.94                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    11164096                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 599296                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  7712960                       # Number of bytes written to this memory
@@ -69,9 +71,10 @@ system.cpu.comNops                            8748916                       # Nu
 system.cpu.comNonSpec                            4583                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                           30791227                       # Number of Integer instructions committed
 system.cpu.comFloats                           151453                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                    88340673                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total              88340673                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                    88340673                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                      88340673                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total              88340673                       # Number of Instructions committed (Total)
 system.cpu.cpi                               1.062122                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         1.062122                       # CPI: Total CPI of All Threads
@@ -125,26 +128,39 @@ system.cpu.icache.total_refs                 12263478                       # To
 system.cpu.icache.sampled_refs                  85656                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 143.171266                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1886.858130                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.921317                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               12263478                       # number of ReadReq hits
-system.cpu.icache.demand_hits                12263478                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               12263478                       # number of overall hits
-system.cpu.icache.ReadReq_misses               116984                       # number of ReadReq misses
-system.cpu.icache.demand_misses                116984                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses               116984                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     2068004000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      2068004000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     2068004000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           12380462                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            12380462                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           12380462                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.009449                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.009449                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.009449                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 17677.665322                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 17677.665322                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 17677.665322                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1886.858130                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.921317                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.921317                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12263478                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12263478                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12263478                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12263478                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12263478                       # number of overall hits
+system.cpu.icache.overall_hits::total        12263478                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       116984                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        116984                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       116984                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         116984                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       116984                       # number of overall misses
+system.cpu.icache.overall_misses::total        116984                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   2068004000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   2068004000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   2068004000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   2068004000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   2068004000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   2068004000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12380462                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12380462                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12380462                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12380462                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12380462                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12380462                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.009449                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.009449                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.009449                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 17677.665322                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 17677.665322                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 17677.665322                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets      1596000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets  9279.069767                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits             31328                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits              31328                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits             31328                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           85656                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            85656                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           85656                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   1345401500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   1345401500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   1345401500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.006919                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.006919                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.006919                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15707.031615                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15707.031615                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15707.031615                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst        31328                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total        31328                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst        31328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total        31328                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst        31328                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total        31328                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        85656                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        85656                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        85656                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        85656                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        85656                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        85656                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1345401500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1345401500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1345401500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1345401500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1345401500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1345401500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006919                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006919                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006919                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15707.031615                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15707.031615                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15707.031615                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 200251                       # number of replacements
 system.cpu.dcache.tagsinuse               4073.105766                       # Cycle average of tags in use
@@ -181,32 +200,49 @@ system.cpu.dcache.total_refs                 34126014                       # To
 system.cpu.dcache.sampled_refs                 204347                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 167.000318                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              486265000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4073.105766                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.994411                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               20180445                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              13945569                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                34126014                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               34126014                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                96193                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              667808                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                764001                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               764001                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     4158649000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   35332073000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     39490722000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    39490722000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.004744                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.045698                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.021897                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.021897                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 43232.345389                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 52907.531806                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 51689.359045                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 51689.359045                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4073.105766                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994411                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994411                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     20180445                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20180445                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13945569                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13945569                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34126014                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34126014                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34126014                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34126014                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        96193                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         96193                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       667808                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       667808                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       764001                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         764001                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       764001                       # number of overall misses
+system.cpu.dcache.overall_misses::total        764001                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   4158649000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   4158649000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  35332073000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  35332073000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  39490722000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  39490722000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  39490722000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  39490722000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     34890015                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004744                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.045698                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.021897                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.021897                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43232.345389                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52907.531806                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51689.359045                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51689.359045                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets   6330522500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 51006.530392                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   161216                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             35426                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           524228                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits             559654                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits            559654                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           60767                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         143580                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           204347                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          204347                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2088724500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   7254420000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   9343144500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   9343144500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009825                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005857                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34372.677605                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 50525.282073                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 45721.955791                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 45721.955791                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       161216                       # number of writebacks
+system.cpu.dcache.writebacks::total            161216                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        35426                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        35426                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       524228                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       524228                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       559654                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total       559654                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       559654                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total       559654                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60767                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        60767                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143580                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143580                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       204347                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204347                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204347                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204347                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2088724500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2088724500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7254420000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7254420000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9343144500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9343144500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9343144500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9343144500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34372.677605                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50525.282073                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 45721.955791                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 45721.955791                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                148060                       # number of replacements
 system.cpu.l2cache.tagsinuse             18663.556927                       # Cycle average of tags in use
@@ -248,36 +292,75 @@ system.cpu.l2cache.total_refs                  131331                       # To
 system.cpu.l2cache.sampled_refs                173405                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.757366                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3005.792321                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15657.764606                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.091730                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.477837                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                103294                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              161216                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               12270                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 115564                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                115564                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               42939                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            131500                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               174439                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              174439                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    2242306500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   6854385000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     9096691500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    9096691500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            146233                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          161216                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          143770                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             290003                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            290003                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.293634                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.914655                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.601508                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.601508                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52220.743380                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52124.600760                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52148.266729                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52148.266729                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15657.764606                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1362.413436                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1643.378886                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.477837                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.041578                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.050152                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.569567                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        76292                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        27002                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         103294                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       161216                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       161216                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12270                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12270                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        76292                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        39272                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          115564                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        76292                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        39272                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         115564                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         9364                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        33575                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        42939                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       131500                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       131500                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         9364                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       165075                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        174439                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         9364                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       165075                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       174439                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    489614500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1752692000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2242306500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6854385000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6854385000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    489614500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8607077000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   9096691500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    489614500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8607077000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   9096691500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        85656                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        60577                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       146233                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       161216                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       161216                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143770                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143770                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        85656                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       204347                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       290003                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        85656                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       204347                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       290003                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.109321                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.554253                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.914655                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.109321                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.807817                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.109321                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.807817                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52286.896625                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52202.293373                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52124.600760                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52286.896625                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52140.402847                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52286.896625                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52140.402847                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -286,30 +369,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  120515                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          42939                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       131500                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          174439                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         174439                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1718628500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   5262711000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   6981339500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   6981339500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.293634                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.914655                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.601508                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.601508                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40024.884138                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40020.615970                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40021.666600                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40021.666600                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       120515                       # number of writebacks
+system.cpu.l2cache.writebacks::total           120515                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         9364                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        33575                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        42939                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131500                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131500                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         9364                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       165075                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       174439                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         9364                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       165075                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       174439                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    375279000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1343349500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1718628500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5262711000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5262711000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    375279000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6606060500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   6981339500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    375279000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6606060500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   6981339500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.109321                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.554253                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.914655                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.109321                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.807817                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.109321                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.807817                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40076.783426                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40010.409531                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40020.615970                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40076.783426                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40018.540058                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40076.783426                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40018.540058                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index ea038d4dadfae22d1a96ec25e36127eec15931f1..427d5ea46933b1bfe978d947401c6aa2150e5a86 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
index 9e435cc9778739a38ab6a679f2572dc4d96b2664..8276bb3687a007e012a1e4457eaf75a76ffa94fd 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:35:02
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:19:29
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 9c4b77b7d2911ca09b25a5072206b0065991ff70..a0babad489d4f46c0357cb442c450924d900d022 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.021260                       # Nu
 sim_ticks                                 21259532000                       # Number of ticks simulated
 final_tick                                21259532000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 187781                       # Simulator instruction rate (inst/s)
-host_tick_rate                               50157547                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217440                       # Number of bytes of host memory used
-host_seconds                                   423.86                       # Real time elapsed on the host
+host_inst_rate                                 240617                       # Simulator instruction rate (inst/s)
+host_op_rate                                   240617                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               64270421                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219780                       # Number of bytes of host memory used
+host_seconds                                   330.78                       # Real time elapsed on the host
 sim_insts                                    79591756                       # Number of instructions simulated
+sim_ops                                      79591756                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    11229312                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 642688                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  7713344                       # Number of bytes written to this memory
@@ -272,6 +274,7 @@ system.cpu.iew.wb_rate                       2.037162                       # in
 system.cpu.iew.wb_fanout                     0.767384                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       88340672                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         88340672                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts         8835054                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            4583                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            366565                       # The number of times a branch was mispredicted
@@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total     40775556                       # Number of insts commited each cycle
-system.cpu.commit.count                      88340672                       # Number of instructions committed
+system.cpu.commit.committedInsts             88340672                       # Number of instructions committed
+system.cpu.commit.committedOps               88340672                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       34890015                       # Number of memory references committed
 system.cpu.commit.loads                      20276638                       # Number of loads committed
@@ -308,6 +312,7 @@ system.cpu.rob.rob_writes                   195703293                       # Th
 system.cpu.timesIdled                           15923                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                          394564                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    79591756                       # Number of Instructions Simulated
+system.cpu.committedOps                      79591756                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              79591756                       # Number of Instructions Simulated
 system.cpu.cpi                               0.534214                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         0.534214                       # CPI: Total CPI of All Threads
@@ -325,26 +330,39 @@ system.cpu.icache.total_refs                 13782143                       # To
 system.cpu.icache.sampled_refs                  90426                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 152.413498                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            17839872000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1927.638696                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.941230                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               13782143                       # number of ReadReq hits
-system.cpu.icache.demand_hits                13782143                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               13782143                       # number of overall hits
-system.cpu.icache.ReadReq_misses                94908                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 94908                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                94908                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      914028500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       914028500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      914028500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           13877051                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            13877051                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           13877051                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.006839                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.006839                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.006839                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency  9630.679184                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency  9630.679184                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency  9630.679184                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1927.638696                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.941230                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.941230                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     13782143                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        13782143                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      13782143                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         13782143                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     13782143                       # number of overall hits
+system.cpu.icache.overall_hits::total        13782143                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        94908                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         94908                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        94908                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          94908                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        94908                       # number of overall misses
+system.cpu.icache.overall_misses::total         94908                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    914028500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    914028500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    914028500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    914028500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    914028500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    914028500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     13877051                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     13877051                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     13877051                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     13877051                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     13877051                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     13877051                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.006839                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.006839                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.006839                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst  9630.679184                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst  9630.679184                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst  9630.679184                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              4481                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               4481                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              4481                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           90427                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            90427                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           90427                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    542589500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    542589500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    542589500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.006516                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.006516                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.006516                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  6000.304113                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  6000.304113                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  6000.304113                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         4481                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         4481                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         4481                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         4481                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         4481                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         4481                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        90427                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        90427                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        90427                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        90427                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        90427                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        90427                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    542589500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    542589500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    542589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    542589500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    542589500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    542589500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.006516                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.006516                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.006516                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  6000.304113                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  6000.304113                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  6000.304113                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 201340                       # number of replacements
 system.cpu.dcache.tagsinuse               4076.154176                       # Cycle average of tags in use
@@ -381,34 +402,53 @@ system.cpu.dcache.total_refs                 34207250                       # To
 system.cpu.dcache.sampled_refs                 205436                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 166.510495                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              157430000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.154176                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995155                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               20628725                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              13578476                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               49                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits                34207201                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               34207201                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               257071                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1034901                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               1291972                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1291972                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     8273144500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   33900181500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     42173326000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    42173326000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           20885796                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           49                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            35499173                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           35499173                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.012308                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.070819                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.036394                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.036394                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32182.332896                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 32756.931822                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 32642.600614                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 32642.600614                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4076.154176                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995155                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995155                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     20628725                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20628725                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     13578476                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       13578476                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           49                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           49                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      34207201                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34207201                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34207201                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34207201                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       257071                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        257071                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1034901                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1034901                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      1291972                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1291972                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1291972                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1291972                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8273144500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   8273144500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  33900181500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  33900181500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  42173326000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  42173326000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  42173326000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  42173326000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20885796                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20885796                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           49                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           49                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     35499173                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     35499173                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     35499173                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     35499173                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.012308                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.070819                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.036394                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.036394                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32182.332896                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32756.931822                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 32642.600614                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 32642.600614                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs        53500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        27000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                20                       # number of cycles access was blocked
@@ -417,32 +457,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs         2675
 system.cpu.dcache.avg_blocked_cycles::no_targets        27000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   161613                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            195029                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits           891507                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1086536                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1086536                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           62042                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         143394                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           205436                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          205436                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1278233000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   4733826000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   6012059000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   6012059000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002971                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009813                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005787                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005787                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 20602.704619                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 33012.720197                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 29264.875679                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 29264.875679                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       161613                       # number of writebacks
+system.cpu.dcache.writebacks::total            161613                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       195029                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       195029                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       891507                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total       891507                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1086536                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1086536                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1086536                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1086536                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        62042                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        62042                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143394                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143394                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       205436                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       205436                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       205436                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       205436                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1278233000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1278233000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   4733826000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   4733826000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6012059000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6012059000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6012059000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6012059000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002971                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009813                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005787                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005787                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 20602.704619                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33012.720197                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 29264.875679                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 29264.875679                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                149119                       # number of replacements
 system.cpu.l2cache.tagsinuse             18923.797261                       # Cycle average of tags in use
@@ -450,36 +498,75 @@ system.cpu.l2cache.total_refs                  136861                       # To
 system.cpu.l2cache.sampled_refs                174485                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.784371                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3200.297768                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15723.499493                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.097665                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.479843                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                108391                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              161613                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               12014                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 120405                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                120405                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               44050                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            131408                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               175458                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              175458                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1516062500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   4525488500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     6041551000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    6041551000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            152441                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          161613                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          143422                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             295863                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            295863                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.288964                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.916233                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.593038                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.593038                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34416.855846                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34438.455041                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34433.032407                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34433.032407                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15723.499493                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1497.146716                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1703.151052                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.479843                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.045689                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.051976                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.577508                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        80385                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        28006                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         108391                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       161613                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       161613                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12014                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12014                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        80385                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        40020                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          120405                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        80385                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        40020                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         120405                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        10042                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        34008                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        44050                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       131408                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       131408                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        10042                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       165416                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        175458                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        10042                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       165416                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       175458                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    344615000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1171447500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1516062500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   4525488500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   4525488500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    344615000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   5696936000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   6041551000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    344615000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   5696936000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   6041551000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        90427                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        62014                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       152441                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       161613                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       161613                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143422                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143422                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        90427                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       205436                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       295863                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        90427                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       205436                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       295863                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.111051                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.548392                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.916233                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.111051                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.805195                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.111051                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.805195                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.367058                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34446.233239                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34438.455041                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.367058                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34440.054166                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.367058                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34440.054166                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -488,30 +575,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  120521                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          44050                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       131408                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          175458                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         175458                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1367587500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4118168500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   5485756000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   5485756000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.288964                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.916233                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.593038                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.593038                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31046.254257                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31338.795964                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31265.351252                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31265.351252                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       120521                       # number of writebacks
+system.cpu.l2cache.writebacks::total           120521                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        10042                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        34008                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        44050                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131408                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131408                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        10042                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       165416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       175458                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        10042                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       165416                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       175458                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    312130500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1055457000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1367587500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4118168500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4118168500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    312130500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5173625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5485756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    312130500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5173625500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5485756000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.111051                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.548392                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.916233                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.111051                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.805195                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.111051                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.805195                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31082.503485                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31035.550459                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31338.795964                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31082.503485                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31276.451492                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31082.503485                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31276.451492                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index d8535707baa480dfabbb7375ae8ec89738d33d4a..cf8e1051d9361682add65c7e635570df1a797501 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
index 160c80ddbc29489983d819067f743ce6492edb6a..0548e6bada8cdaeb983fe43d9e3acd93f598d34e 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:42:17
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:25:10
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 4fc91e26652df406aaafcf273369636afc31b10e..45c7e3698d176a96cecdb20f657bcac2b87981ed 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.044221                       # Nu
 sim_ticks                                 44221003000                       # Number of ticks simulated
 final_tick                                44221003000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3998504                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2001543652                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206876                       # Number of bytes of host memory used
-host_seconds                                    22.09                       # Real time elapsed on the host
+host_inst_rate                                5044223                       # Simulator instruction rate (inst/s)
+host_op_rate                                  5044217                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2524999281                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208636                       # Number of bytes of host memory used
+host_seconds                                    17.51                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   480454939                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              353752292                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 91652896                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                 4583                       # Nu
 system.cpu.numCycles                         88442007                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         88340673                       # Number of instructions executed
+system.cpu.committedInsts                    88340673                       # Number of instructions committed
+system.cpu.committedOps                      88340673                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
 system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
index f99b5fb55c5f75155fd3bbc5a3fac4a392e7720e..4c4894527939912adedbfa43aa78c558fd248447 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
index e74b48d2a3fde2cc3aa8e5ab200d3f7870ccbe02..471c7b55ae1ca996b41e953ffffa87a5381c6181 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:42:49
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:25:32
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/50.vortex/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 59b869a9f3bbd24475a9a460c6af803a87aaea64..c906eecdf27d81ad7f544e198c1cc055d7caa18f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.134277                       # Nu
 sim_ticks                                134276988000                       # Number of ticks simulated
 final_tick                               134276988000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1801981                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2738992827                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215584                       # Number of bytes of host memory used
-host_seconds                                    49.02                       # Real time elapsed on the host
+host_inst_rate                                2261546                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2261545                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3437525661                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217500                       # Number of bytes of host memory used
+host_seconds                                    39.06                       # Real time elapsed on the host
 sim_insts                                    88340673                       # Number of instructions simulated
+sim_ops                                      88340673                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    11121920                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 558272                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  7712384                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                 4583                       # Nu
 system.cpu.numCycles                        268553976                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         88340673                       # Number of instructions executed
+system.cpu.committedInsts                    88340673                       # Number of instructions committed
+system.cpu.committedOps                      88340673                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              78039444                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 267757                       # Number of float alu accesses
 system.cpu.num_func_calls                     3321606                       # number of times a function call or return occured
@@ -79,26 +82,39 @@ system.cpu.icache.total_refs                 88361638                       # To
 system.cpu.icache.sampled_refs                  76436                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                1156.021220                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1871.404551                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.913772                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               88361638                       # number of ReadReq hits
-system.cpu.icache.demand_hits                88361638                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               88361638                       # number of overall hits
-system.cpu.icache.ReadReq_misses                76436                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 76436                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                76436                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     1436470000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      1436470000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     1436470000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           88438074                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            88438074                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           88438074                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000864                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000864                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000864                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 18793.107960                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 18793.107960                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 18793.107960                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1871.404551                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.913772                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.913772                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     88361638                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        88361638                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      88361638                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         88361638                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     88361638                       # number of overall hits
+system.cpu.icache.overall_hits::total        88361638                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        76436                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         76436                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        76436                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          76436                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        76436                       # number of overall misses
+system.cpu.icache.overall_misses::total         76436                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   1436470000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   1436470000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   1436470000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   1436470000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   1436470000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   1436470000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     88438074                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     88438074                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     88438074                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     88438074                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     88438074                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     88438074                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000864                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000864                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000864                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 18793.107960                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 18793.107960                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 18793.107960                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           76436                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            76436                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           76436                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   1207162000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   1207162000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   1207162000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000864                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000864                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000864                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 15793.107960                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 15793.107960                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        76436                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        76436                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        76436                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        76436                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        76436                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        76436                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1207162000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   1207162000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1207162000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   1207162000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1207162000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   1207162000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000864                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 15793.107960                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 15793.107960                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 15793.107960                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 200248                       # number of replacements
 system.cpu.dcache.tagsinuse               4078.858373                       # Cycle average of tags in use
@@ -134,32 +148,49 @@ system.cpu.dcache.total_refs                 34685671                       # To
 system.cpu.dcache.sampled_refs                 204344                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 169.741568                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              943232000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4078.858373                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995815                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               20215872                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              14469799                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                34685671                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               34685671                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                60766                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              143578                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                204344                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               204344                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     2261000000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    7532210000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency      9793210000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     9793210000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           20276638                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          14613377                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            34890015                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           34890015                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.002997                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.009825                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.005857                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.005857                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 37208.307277                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 52460.753040                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 47925.116470                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 47925.116470                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4078.858373                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995815                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995815                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     20215872                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        20215872                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     14469799                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       14469799                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      34685671                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         34685671                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     34685671                       # number of overall hits
+system.cpu.dcache.overall_hits::total        34685671                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        60766                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         60766                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       143578                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       143578                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       204344                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         204344                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       204344                       # number of overall misses
+system.cpu.dcache.overall_misses::total        204344                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2261000000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2261000000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   7532210000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   7532210000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   9793210000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   9793210000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   9793210000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   9793210000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     20276638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     20276638                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     14613377                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     34890015                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     34890015                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     34890015                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     34890015                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.002997                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.009825                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.005857                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.005857                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37208.307277                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52460.753040                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47925.116470                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47925.116470                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   161222                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           60766                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         143578                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           204344                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          204344                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   2078702000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   7101476000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   9180178000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   9180178000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002997                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.009825                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005857                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005857                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34208.307277                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 49460.753040                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 44925.116470                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       161222                       # number of writebacks
+system.cpu.dcache.writebacks::total            161222                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        60766                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        60766                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       143578                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       143578                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       204344                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       204344                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       204344                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       204344                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   2078702000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   2078702000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   7101476000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   7101476000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   9180178000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   9180178000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   9180178000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   9180178000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002997                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.009825                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005857                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34208.307277                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 49460.753040                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44925.116470                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44925.116470                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                147405                       # number of replacements
 system.cpu.l2cache.tagsinuse             18614.813333                       # Cycle average of tags in use
@@ -199,36 +232,75 @@ system.cpu.l2cache.total_refs                  122958                       # To
 system.cpu.l2cache.sampled_refs                172748                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.711777                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2806.549776                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15808.263557                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.085649                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.482430                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 94901                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              161222                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits               12099                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 107000                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                107000                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               42301                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            131479                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               173780                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              173780                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    2199652000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   6836908000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     9036560000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    9036560000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            137202                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          161222                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          143578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             280780                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            280780                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.308312                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.915732                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.618919                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.618919                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15808.263557                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1305.254425                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1501.295351                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.482430                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.039833                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.045816                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.568079                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        67713                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        27188                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          94901                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       161222                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       161222                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data        12099                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total        12099                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        67713                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        39287                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          107000                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        67713                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        39287                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         107000                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         8723                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        33578                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        42301                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       131479                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       131479                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         8723                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       165057                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        173780                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         8723                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       165057                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       173780                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    453596000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1746056000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2199652000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   6836908000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   6836908000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    453596000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   8582964000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   9036560000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    453596000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   8582964000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   9036560000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        76436                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        60766                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       137202                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       161222                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       161222                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       143578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       143578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        76436                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       204344                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       280780                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        76436                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       204344                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       280780                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.114122                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.552579                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.915732                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.114122                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.807741                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.114122                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.807741                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -237,30 +309,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                  120506                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          42301                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       131479                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          173780                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         173780                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1692040000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   5259160000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   6951200000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   6951200000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.308312                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.915732                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.618919                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.618919                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks       120506                       # number of writebacks
+system.cpu.l2cache.writebacks::total           120506                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         8723                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        33578                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        42301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131479                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       131479                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         8723                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       165057                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       173780                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         8723                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       165057                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       173780                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    348920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1343120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1692040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   5259160000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   5259160000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    348920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   6602280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   6951200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    348920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   6602280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   6951200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.114122                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.552579                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.915732                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.114122                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.807741                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.114122                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.807741                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 18c9a58093ad05dd15727da97a6d7e51a3f52993..1d9e3541a4133a5457ee120e0097c782f9c6ff5c 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
index 08b53cf2fca433659d3ac64d25db1d8e1c3b3b24..e2d26e3725977795e171afbdef18deeb6fc8e5d3 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:22
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:25:27
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index b5c5ac05d42ec09d9ac0f2aa4ab677d4afd5b19f..228286404224ae0d5a1a6686c8c9e13153be844b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.031189                       # Nu
 sim_ticks                                 31189496500                       # Number of ticks simulated
 final_tick                                31189496500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  53036                       # Simulator instruction rate (inst/s)
-host_tick_rate                               16437569                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 264816                       # Number of bytes of host memory used
-host_seconds                                  1897.45                       # Real time elapsed on the host
-sim_insts                                   100634170                       # Number of instructions simulated
+host_inst_rate                                 144507                       # Simulator instruction rate (inst/s)
+host_op_rate                                   205068                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               63556485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 231932                       # Number of bytes of host memory used
+host_seconds                                   490.74                       # Real time elapsed on the host
+sim_insts                                    70914922                       # Number of instructions simulated
+sim_ops                                     100634170                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     8651712                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 350080                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  5661248                       # Number of bytes written to this memory
@@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.689926                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.519070                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      100639722                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts       70920474                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        100639722                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        11954174                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls          703033                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts            788567                       # The number of times a branch was mispredicted
@@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total     59169182                       # Number of insts commited each cycle
-system.cpu.commit.count                     100639722                       # Number of instructions committed
+system.cpu.commit.committedInsts             70920474                       # Number of instructions committed
+system.cpu.commit.committedOps              100639722                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       47865761                       # Number of memory references committed
 system.cpu.commit.loads                      27308566                       # Number of loads committed
@@ -318,12 +322,13 @@ system.cpu.rob.rob_reads                    166686934                       # Th
 system.cpu.rob.rob_writes                   227096473                       # The number of ROB writes
 system.cpu.timesIdled                           61617                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                         1306838                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   100634170                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             100634170                       # Number of Instructions Simulated
-system.cpu.cpi                               0.619859                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.619859                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.613270                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.613270                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                    70914922                       # Number of Instructions Simulated
+system.cpu.committedOps                     100634170                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total              70914922                       # Number of Instructions Simulated
+system.cpu.cpi                               0.879631                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.879631                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.136840                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.136840                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                511674990                       # number of integer regfile reads
 system.cpu.int_regfile_writes               103897673                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                       166                       # number of floating regfile reads
@@ -336,26 +341,39 @@ system.cpu.icache.total_refs                 12180358                       # To
 system.cpu.icache.sampled_refs                  28166                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 432.448981                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1805.600642                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.881641                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               12180359                       # number of ReadReq hits
-system.cpu.icache.demand_hits                12180359                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               12180359                       # number of overall hits
-system.cpu.icache.ReadReq_misses                29272                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 29272                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                29272                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      357988500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       357988500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      357988500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           12209631                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            12209631                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           12209631                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.002397                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.002397                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.002397                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 12229.724652                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 12229.724652                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 12229.724652                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1805.600642                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.881641                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.881641                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     12180359                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        12180359                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      12180359                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         12180359                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     12180359                       # number of overall hits
+system.cpu.icache.overall_hits::total        12180359                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        29272                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         29272                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        29272                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          29272                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        29272                       # number of overall misses
+system.cpu.icache.overall_misses::total         29272                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    357988500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    357988500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    357988500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    357988500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    357988500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    357988500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     12209631                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     12209631                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     12209631                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     12209631                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     12209631                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     12209631                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.002397                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.002397                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.002397                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 12229.724652                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 12229.724652                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 12229.724652                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -364,27 +382,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        1                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1063                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1063                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1063                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           28209                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            28209                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           28209                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    247071500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    247071500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    247071500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.002310                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.002310                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.002310                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  8758.605410                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  8758.605410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  8758.605410                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks            1                       # number of writebacks
+system.cpu.icache.writebacks::total                 1                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1063                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1063                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1063                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1063                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1063                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1063                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        28209                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        28209                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        28209                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        28209                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        28209                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        28209                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    247071500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    247071500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    247071500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    247071500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    247071500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    247071500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.002310                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.002310                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.002310                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst  8758.605410                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst  8758.605410                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst  8758.605410                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 157892                       # number of replacements
 system.cpu.dcache.tagsinuse               4072.334227                       # Cycle average of tags in use
@@ -392,40 +415,63 @@ system.cpu.dcache.total_refs                 44746410                       # To
 system.cpu.dcache.sampled_refs                 161988                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 276.232869                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              306594000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4072.334227                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.994222                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               26399659                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              18310286                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            18924                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             17376                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                44709945                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               44709945                       # number of overall hits
-system.cpu.dcache.ReadReq_misses               108879                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1539615                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses             26                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses               1648494                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              1648494                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     2418798500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   52283607500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       349000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     54702406000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    54702406000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           26508538                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        18950                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         17376                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            46358439                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           46358439                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.004107                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.077563                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.001372                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.035560                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.035560                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 22215.473140                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33958.884202                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 13423.076923                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33183.260600                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33183.260600                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4072.334227                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.994222                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.994222                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     26399659                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        26399659                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18310286                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18310286                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        18924                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        18924                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        17376                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        17376                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      44709945                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         44709945                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     44709945                       # number of overall hits
+system.cpu.dcache.overall_hits::total        44709945                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data       108879                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total        108879                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1539615                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1539615                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data           26                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total           26                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data      1648494                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        1648494                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      1648494                       # number of overall misses
+system.cpu.dcache.overall_misses::total       1648494                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   2418798500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   2418798500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  52283607500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  52283607500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       349000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       349000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  54702406000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  54702406000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  54702406000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  54702406000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     26508538                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     26508538                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        18950                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        18950                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        17376                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        17376                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     46358439                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46358439                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46358439                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46358439                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.004107                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.077563                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.001372                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.035560                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.035560                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 22215.473140                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33958.884202                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13423.076923                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33183.260600                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33183.260600                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       190500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -434,33 +480,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets        19050                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   123473                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits             53766                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1432695                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits           26                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1486461                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1486461                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           55113                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         106920                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           162033                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          162033                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1035745500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   3662420000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   4698165500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   4698165500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002079                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005386                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.003495                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.003495                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 18793.125034                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34253.834643                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 28995.115193                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 28995.115193                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       123473                       # number of writebacks
+system.cpu.dcache.writebacks::total            123473                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        53766                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total        53766                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1432695                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1432695                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data           26                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total           26                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1486461                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1486461                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1486461                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1486461                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        55113                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        55113                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       106920                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       106920                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       162033                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       162033                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       162033                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       162033                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1035745500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1035745500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   3662420000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   3662420000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   4698165500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   4698165500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   4698165500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   4698165500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002079                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005386                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003495                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003495                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18793.125034                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34253.834643                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 28995.115193                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 28995.115193                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                114916                       # number of replacements
 system.cpu.l2cache.tagsinuse             18304.706842                       # Cycle average of tags in use
@@ -468,40 +523,82 @@ system.cpu.l2cache.total_refs                   72481                       # To
 system.cpu.l2cache.sampled_refs                133774                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.541817                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2370.559791                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15934.147051                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.072344                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.486272                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 50571                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              123474                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits                 14                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits                4310                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  54881                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 54881                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               32667                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses               30                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses            102597                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               135264                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              135264                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1118379000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   3526118000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     4644497000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    4644497000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             83238                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          123474                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses             44                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          106907                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             190145                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            190145                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.392453                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate      0.681818                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.959685                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.711373                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.711373                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34235.742492                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34368.626763                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34336.534481                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34336.534481                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15934.147051                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    839.668596                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1530.891195                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.486272                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.025625                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.046719                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.558615                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        22667                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        27904                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          50571                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       123474                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       123474                       # number of Writeback hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           14                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::total           14                       # number of UpgradeReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4310                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4310                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        22667                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        32214                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           54881                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        22667                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        32214                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          54881                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         5494                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        27173                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        32667                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data           30                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total           30                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102597                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102597                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         5494                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       129770                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        135264                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         5494                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       129770                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       135264                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    188188000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data    930191000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1118379000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   3526118000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   3526118000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    188188000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   4456309000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   4644497000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    188188000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   4456309000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   4644497000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        28161                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        55077                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        83238                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       123474                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       123474                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data           44                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total           44                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       106907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       106907                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        28161                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       161984                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       190145                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        28161                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       161984                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       190145                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.195093                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.493364                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.681818                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.959685                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.195093                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.801129                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.195093                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.801129                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34253.367310                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34232.179001                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34368.626763                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34253.367310                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34340.055483                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34253.367310                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34340.055483                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -510,35 +607,59 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   88457                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               81                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                81                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               81                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          32586                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses           30                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       102597                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          135183                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         135183                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1012814500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency       931000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   3197894500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   4210709000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   4210709000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.391480                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate     0.681818                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.959685                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.710947                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.710947                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.277236                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 31033.333333                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31169.473766                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31148.213903                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31148.213903                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        88457                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88457                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           24                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           57                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           81                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           24                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           57                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           81                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           24                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           57                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           81                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         5470                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        27116                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        32586                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data           30                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total           30                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102597                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102597                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         5470                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       129713                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       135183                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         5470                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       129713                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       135183                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    169929500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    842885000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1012814500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data       931000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total       931000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   3197894500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   3197894500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    169929500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   4040779500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   4210709000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    169929500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   4040779500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   4210709000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.194240                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.492329                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.681818                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.959685                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.194240                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.800777                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.194240                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.800777                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31065.722121                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31084.415105                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 31033.333333                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31169.473766                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31065.722121                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31151.692583                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31065.722121                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31151.692583                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 321a621c1c552ed582ddb0935214b33cff023da5..e57dda708ab8c8c9706686b11204e327d948764e 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index cba7edc9e677b1924c349cf9215957efb56c73d1..1d79bb34d344c7a82ddbf332ecaf6805747d99d2 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:35:25
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:26:23
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 55037759404f273f3d1ee23c34a0e706c1285ce9..89b488ea90fa0279c9962f66a2ffdb90eac260ac 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.053932                       # Nu
 sim_ticks                                 53932162000                       # Number of ticks simulated
 final_tick                                53932162000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3016681                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1616735818                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217624                       # Number of bytes of host memory used
-host_seconds                                    33.36                       # Real time elapsed on the host
-sim_insts                                   100632437                       # Number of instructions simulated
+host_inst_rate                                2464229                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3496968                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1874136829                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220180                       # Number of bytes of host memory used
+host_seconds                                    28.78                       # Real time elapsed on the host
+sim_insts                                    70913189                       # Number of instructions simulated
+sim_ops                                     100632437                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   419153654                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              312580308                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 78660211                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                 1946                       # Nu
 system.cpu.numCycles                        107864325                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        100632437                       # Number of instructions executed
+system.cpu.committedInsts                    70913189                       # Number of instructions committed
+system.cpu.committedOps                     100632437                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
 system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
index 62eb4cdbf9c82929773970b3c1d3829087fcbcc8..a85bd162d8e3450d629c9763e7aa696337ebcf84 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex lendian.raw
-cwd=build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 4fb7505021fc6fd858b4c6793165376217bac04d..3a0d84b6b1831b2c5b28fede1d3b1031caff6feb 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:36:06
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:27:02
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/50.vortex/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 2fff6cef591a5dbce0bf26c655edd12dd031c7f5..0f7cee094489977fdb6596ed60071c43bf53890c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.133117                       # Nu
 sim_ticks                                133117442000                       # Number of ticks simulated
 final_tick                               133117442000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1410680                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1881780580                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226592                       # Number of bytes of host memory used
-host_seconds                                    70.74                       # Real time elapsed on the host
-sim_insts                                    99791663                       # Number of instructions simulated
+host_inst_rate                                1269489                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1800168                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2401339947                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229088                       # Number of bytes of host memory used
+host_seconds                                    55.43                       # Real time elapsed on the host
+sim_insts                                    70373636                       # Number of instructions simulated
+sim_ops                                      99791663                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     8570688                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 294208                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  5660736                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                 1946                       # Nu
 system.cpu.numCycles                        266234884                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         99791663                       # Number of instructions executed
+system.cpu.committedInsts                    70373636                       # Number of instructions committed
+system.cpu.committedOps                      99791663                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              91472788                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     56                       # Number of float alu accesses
 system.cpu.num_func_calls                     3287514                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs                 78126170                       # To
 system.cpu.icache.sampled_refs                  18908                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                4131.910831                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1736.182852                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.847746                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               78126170                       # number of ReadReq hits
-system.cpu.icache.demand_hits                78126170                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               78126170                       # number of overall hits
-system.cpu.icache.ReadReq_misses                18908                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 18908                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                18908                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      457786000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       457786000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      457786000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           78145078                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            78145078                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           78145078                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000242                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000242                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000242                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 24211.233340                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 24211.233340                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 24211.233340                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1736.182852                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.847746                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.847746                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     78126170                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        78126170                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      78126170                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         78126170                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     78126170                       # number of overall hits
+system.cpu.icache.overall_hits::total        78126170                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        18908                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         18908                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        18908                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          18908                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        18908                       # number of overall misses
+system.cpu.icache.overall_misses::total         18908                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    457786000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    457786000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    457786000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    457786000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    457786000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    457786000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     78145078                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     78145078                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     78145078                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     78145078                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     78145078                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     78145078                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000242                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000242                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000242                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 24211.233340                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 24211.233340                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 24211.233340                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           18908                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            18908                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           18908                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    401062000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    401062000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    401062000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000242                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000242                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000242                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 21211.233340                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 21211.233340                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        18908                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        18908                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        18908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        18908                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        18908                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        18908                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    401062000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    401062000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    401062000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    401062000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    401062000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    401062000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000242                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 21211.233340                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 21211.233340                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 21211.233340                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 155902                       # number of replacements
 system.cpu.dcache.tagsinuse               4076.934010                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                 46862075                       # To
 system.cpu.dcache.sampled_refs                 159998                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 292.891630                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             1079641000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4076.934010                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995345                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               27087368                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              19742869                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            15919                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             15919                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                46830237                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               46830237                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                52966                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              107032                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                159998                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               159998                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     1862630000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    5808782000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency      7671412000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     7671412000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           27140334                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          19849901                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        15919                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         15919                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            46990235                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           46990235                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.001952                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.005392                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.003405                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.003405                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35166.521920                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 54271.451529                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 47946.924337                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 47946.924337                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4076.934010                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995345                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995345                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     27087368                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        27087368                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     19742869                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       19742869                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        15919                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        15919                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        15919                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      46830237                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         46830237                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     46830237                       # number of overall hits
+system.cpu.dcache.overall_hits::total        46830237                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        52966                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         52966                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       107032                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       107032                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data       159998                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         159998                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       159998                       # number of overall misses
+system.cpu.dcache.overall_misses::total        159998                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1862630000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1862630000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5808782000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5808782000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7671412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7671412000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7671412000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7671412000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     27140334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     27140334                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     19849901                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        15919                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        15919                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     46990235                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     46990235                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     46990235                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     46990235                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001952                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005392                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.003405                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.003405                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35166.521920                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54271.451529                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 47946.924337                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 47946.924337                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   122808                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           52966                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         107032                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           159998                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          159998                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1703732000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5487686000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   7191418000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   7191418000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001952                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005392                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.003405                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.003405                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32166.521920                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51271.451529                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 44946.924337                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       122808                       # number of writebacks
+system.cpu.dcache.writebacks::total            122808                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        52966                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        52966                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       107032                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       107032                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       159998                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       159998                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       159998                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       159998                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1703732000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1703732000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5487686000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5487686000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   7191418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   7191418000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   7191418000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   7191418000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001952                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005392                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.003405                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32166.521920                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51271.451529                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 44946.924337                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44946.924337                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                113660                       # number of replacements
 system.cpu.l2cache.tagsinuse             18191.621028                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                   61800                       # To
 system.cpu.l2cache.sampled_refs                132489                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.466454                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2165.921088                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         16025.699940                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.066099                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.489066                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                 40584                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              122808                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                4405                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                  44989                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                 44989                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               31290                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            102627                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               133917                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              133917                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    1627080000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   5336604000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     6963684000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    6963684000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             71874                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          122808                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          107032                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             178906                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            178906                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.435345                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.958844                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.748533                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.748533                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 16025.699940                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst    701.722418                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1464.198671                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.489066                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.021415                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.044684                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.555164                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst        14311                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        26273                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total          40584                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       122808                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       122808                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         4405                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         4405                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst        14311                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        30678                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total           44989                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst        14311                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        30678                       # number of overall hits
+system.cpu.l2cache.overall_hits::total          44989                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         4597                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        26693                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        31290                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       102627                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       102627                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         4597                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       129320                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        133917                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         4597                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       129320                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       133917                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    239044000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1388036000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   1627080000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5336604000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5336604000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    239044000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   6724640000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   6963684000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    239044000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   6724640000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   6963684000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        18908                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        52966                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        71874                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       122808                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       122808                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       107032                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       107032                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        18908                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       159998                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       178906                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        18908                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       159998                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       178906                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.243125                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.503965                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.958844                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.243125                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.808260                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.243125                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.808260                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   88449                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          31290                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       102627                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          133917                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         133917                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1251600000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4105080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   5356680000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   5356680000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.435345                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.958844                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.748533                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.748533                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        88449                       # number of writebacks
+system.cpu.l2cache.writebacks::total            88449                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         4597                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        26693                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        31290                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       102627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       102627                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         4597                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       129320                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       133917                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         4597                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       129320                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       133917                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    183880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1067720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1251600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4105080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4105080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    183880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5172800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5356680000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    183880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5172800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5356680000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.243125                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.503965                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.958844                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.243125                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.808260                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.243125                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.808260                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 2df6b792df044a5ace67a99f2702a2c9fc033406..4295b595040ade4df9d5a1463bbd6e4d9a1143c7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
index 542479326693a01f3ceed990ff7ddf43e8105f60..7e99d8ae7b29497334a4b05f3f6f57a217706ac0 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:24:20
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:00:16
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index dc6c319986d831c7ad17e80f4ad5beb1f92dbb2a..12070ccfb5da870674be53b76ec0dad25f7fd688 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.068149                       # Nu
 sim_ticks                                 68148678500                       # Number of ticks simulated
 final_tick                                68148678500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3420916                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1712444497                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 214012                       # Number of bytes of host memory used
-host_seconds                                    39.80                       # Real time elapsed on the host
-sim_insts                                   136139203                       # Number of instructions simulated
+host_inst_rate                                3965699                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4017046                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2010855033                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211680                       # Number of bytes of host memory used
+host_seconds                                    33.89                       # Real time elapsed on the host
+sim_insts                                   134398975                       # Number of instructions simulated
+sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   685773693                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              538214332                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 89882950                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                 1946                       # Nu
 system.cpu.numCycles                        136297358                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        136139203                       # Number of instructions executed
+system.cpu.committedInsts                   134398975                       # Number of instructions committed
+system.cpu.committedOps                     136139203                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
 system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
index 5e34ae7a168715d42a5bb9bac5e2e1dd752c3108..2507c0ed40bc5bb8ea1b10ad6511347f4420cee9 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=vortex bendian.raw
-cwd=build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 787eaa97a34faab95be6ba2631a897f22b660aaa..a6a3d32b75fb66be53d0fe896bee99129441f8e0 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:24:48
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:01:00
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/50.vortex/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 168a8eefa4f81e61c0aead26a1a9f3ef5f5c95c8..b24bd2c93cbef91c9c04280517a08a34626ebe9c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.202942                       # Nu
 sim_ticks                                202941992000                       # Number of ticks simulated
 final_tick                               202941992000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1608666                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2398029397                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222724                       # Number of bytes of host memory used
-host_seconds                                    84.63                       # Real time elapsed on the host
-sim_insts                                   136139203                       # Number of instructions simulated
+host_inst_rate                                1927976                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1952939                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2911235123                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220544                       # Number of bytes of host memory used
+host_seconds                                    69.71                       # Real time elapsed on the host
+sim_insts                                   134398975                       # Number of instructions simulated
+sim_ops                                     136139203                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                     8970304                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 835264                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  5584960                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                 1946                       # Nu
 system.cpu.numCycles                        405883984                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        136139203                       # Number of instructions executed
+system.cpu.committedInsts                   134398975                       # Number of instructions committed
+system.cpu.committedOps                     136139203                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             115187758                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2326977                       # Number of float alu accesses
 system.cpu.num_func_calls                     1709332                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs                134366560                       # To
 system.cpu.icache.sampled_refs                 187024                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 718.445547                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle           144544557000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           2004.721102                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.978868                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              134366560                       # number of ReadReq hits
-system.cpu.icache.demand_hits               134366560                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              134366560                       # number of overall hits
-system.cpu.icache.ReadReq_misses               187024                       # number of ReadReq misses
-system.cpu.icache.demand_misses                187024                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses               187024                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency     3166478000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency      3166478000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency     3166478000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          134553584                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           134553584                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          134553584                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.001390                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.001390                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.001390                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 16930.864488                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 16930.864488                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 16930.864488                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    2004.721102                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.978868                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.978868                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    134366560                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       134366560                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     134366560                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        134366560                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    134366560                       # number of overall hits
+system.cpu.icache.overall_hits::total       134366560                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst       187024                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total        187024                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst       187024                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total         187024                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst       187024                       # number of overall misses
+system.cpu.icache.overall_misses::total        187024                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst   3166478000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total   3166478000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst   3166478000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total   3166478000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst   3166478000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total   3166478000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    134553584                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    134553584                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    134553584                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    134553584                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    134553584                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    134553584                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001390                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001390                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001390                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16930.864488                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 16930.864488                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 16930.864488                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          187024                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           187024                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          187024                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   2605406000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   2605406000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   2605406000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.001390                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.001390                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.001390                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 13930.864488                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 13930.864488                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       187024                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       187024                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       187024                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       187024                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       187024                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       187024                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   2605406000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   2605406000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   2605406000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   2605406000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   2605406000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   2605406000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.001390                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 13930.864488                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 13930.864488                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 13930.864488                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 146582                       # number of replacements
 system.cpu.dcache.tagsinuse               4087.617150                       # Cycle average of tags in use
@@ -102,38 +116,59 @@ system.cpu.dcache.total_refs                 57960843                       # To
 system.cpu.dcache.sampled_refs                 150678                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 384.666925                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              776708000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4087.617150                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997953                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               37185802                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              20759140                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                  15901                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                57944942                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               57944942                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                45499                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses              105164                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses                   15                       # number of SwapReq misses
-system.cpu.dcache.demand_misses                150663                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses               150663                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     1709246000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    5738404000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency         462000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency      7447650000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency     7447650000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           37231301                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          20864304                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses              15916                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            58095605                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           58095605                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.001222                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.005040                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate          0.000942                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.002593                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.002593                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 37566.671795                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 54566.239398                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency        30800                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 49432.508313                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 49432.508313                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4087.617150                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997953                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997953                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     37185802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        37185802                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20759140                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20759140                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data        15901                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total           15901                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data      57944942                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         57944942                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     57944942                       # number of overall hits
+system.cpu.dcache.overall_hits::total        57944942                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data        45499                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total         45499                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       105164                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total       105164                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data           15                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total            15                       # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data       150663                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total         150663                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data       150663                       # number of overall misses
+system.cpu.dcache.overall_misses::total        150663                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   1709246000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   1709246000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   5738404000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   5738404000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data       462000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total       462000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data   7447650000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total   7447650000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data   7447650000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total   7447650000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     37231301                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     37231301                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     20864304                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     20864304                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data        15916                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total        15916                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     58095605                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     58095605                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     58095605                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     58095605                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.001222                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.005040                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.000942                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.002593                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.002593                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 37566.671795                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54566.239398                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        30800                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 49432.508313                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 49432.508313                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -142,34 +177,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   118818                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses           45499                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         105164                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses              15                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           150663                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          150663                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   1572749000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   5422912000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency       417000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency   6995661000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency   6995661000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.001222                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.005040                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.000942                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.002593                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.002593                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34566.671795                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 51566.239398                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        27800                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 46432.508313                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       118818                       # number of writebacks
+system.cpu.dcache.writebacks::total            118818                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data        45499                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total        45499                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       105164                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       105164                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data           15                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total           15                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       150663                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       150663                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       150663                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       150663                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   1572749000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   1572749000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   5422912000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   5422912000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data       417000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total       417000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data   6995661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total   6995661000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data   6995661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total   6995661000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.001222                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.005040                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.000942                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.002593                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34566.671795                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51566.239398                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        27800                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46432.508313                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46432.508313                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                120138                       # number of replacements
 system.cpu.l2cache.tagsinuse             19734.031622                       # Cycle average of tags in use
@@ -177,36 +216,75 @@ system.cpu.l2cache.total_refs                  212003                       # To
 system.cpu.l2cache.sampled_refs                139002                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  1.525179                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          3965.924560                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         15768.107062                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.121030                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.481204                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                193942                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits              118818                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                3599                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                 197541                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                197541                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses               38581                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            101580                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses               140161                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses              140161                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency    2006212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency   5282160000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency     7288372000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency    7288372000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses            232523                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses          118818                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses          105179                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses             337702                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses            337702                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.165923                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.965782                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.415043                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.415043                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 15768.107062                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2612.732810                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data   1353.191750                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.481204                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.079734                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.041296                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.602235                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst       173973                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data        19969                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total         193942                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks       118818                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total       118818                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data         3599                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total         3599                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst       173973                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data        23568                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total          197541                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst       173973                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data        23568                       # number of overall hits
+system.cpu.l2cache.overall_hits::total         197541                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst        13051                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data        25530                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total        38581                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       101580                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       101580                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst        13051                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       127110                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total        140161                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst        13051                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data       127110                       # number of overall misses
+system.cpu.l2cache.overall_misses::total       140161                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    678652000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data   1327560000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total   2006212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data   5282160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total   5282160000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    678652000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data   6609720000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total   7288372000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    678652000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data   6609720000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total   7288372000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst       187024                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data        45499                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total       232523                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks       118818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total       118818                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data       105179                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total       105179                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst       187024                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data       150678                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total       337702                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst       187024                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data       150678                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total       337702                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.069782                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.561111                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.965782                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.069782                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.843587                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.069782                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.843587                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -215,30 +293,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                   87265                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses          38581                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       101580                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses          140161                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses         140161                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1543240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency   4063200000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency   5606440000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency   5606440000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.165923                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.965782                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.415043                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.415043                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks        87265                       # number of writebacks
+system.cpu.l2cache.writebacks::total            87265                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        13051                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        25530                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total        38581                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       101580                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       101580                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        13051                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       127110                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total       140161                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        13051                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       127110                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total       140161                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    522040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data   1021200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total   1543240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   4063200000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   4063200000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    522040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   5084400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total   5606440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    522040000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   5084400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total   5606440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.069782                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.561111                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.965782                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.069782                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.843587                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.069782                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.843587                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 0d09e2e146643957baab9839d8565e43cd1038ee..1037754155bf70572b4110c639f91b0d67b59656 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -202,7 +194,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
index 8bc14bb8a3ebe784a9b2242b133ab72825785ca8..d36129661f0bd5755c13265ba262c8cbd65addf3 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:42:50
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:25:39
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index bf815a6e18bfc739f14650f0a4a7867c260e49ca..d5a78ee7652f690bc5928dc96db3b7927e6f524f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.009857                       # Nu
 sim_ticks                                1009857089500                       # Number of ticks simulated
 final_tick                               1009857089500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 102085                       # Simulator instruction rate (inst/s)
-host_tick_rate                               56650413                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208040                       # Number of bytes of host memory used
-host_seconds                                 17826.12                       # Real time elapsed on the host
+host_inst_rate                                 137029                       # Simulator instruction rate (inst/s)
+host_op_rate                                   137029                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               76042102                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209964                       # Number of bytes of host memory used
+host_seconds                                 13280.24                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
+sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   172617984                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  54912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 74938304                       # Number of bytes written to this memory
@@ -69,9 +71,10 @@ system.cpu.comNops                           83736345                       # Nu
 system.cpu.comNonSpec                              29                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                          916086844                       # Number of Integer instructions committed
 system.cpu.comFloats                              190                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                  1819780127                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total            1819780127                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                  1819780127                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                    1819780127                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total            1819780127                       # Number of Instructions committed (Total)
 system.cpu.cpi                               1.109867                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         1.109867                       # CPI: Total CPI of All Threads
@@ -125,26 +128,39 @@ system.cpu.icache.total_refs                233079667                       # To
 system.cpu.icache.sampled_refs                    858                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               271654.623543                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            664.479191                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.324453                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              233079667                       # number of ReadReq hits
-system.cpu.icache.demand_hits               233079667                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              233079667                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1062                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1062                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1062                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       58337000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        58337000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       58337000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          233080729                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           233080729                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          233080729                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54931.261770                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54931.261770                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54931.261770                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     664.479191                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.324453                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.324453                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    233079667                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       233079667                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     233079667                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        233079667                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    233079667                       # number of overall hits
+system.cpu.icache.overall_hits::total       233079667                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1062                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1062                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1062                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1062                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1062                       # number of overall misses
+system.cpu.icache.overall_misses::total          1062                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     58337000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     58337000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     58337000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     58337000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     58337000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     58337000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    233080729                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    233080729                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    233080729                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    233080729                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    233080729                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    233080729                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000005                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000005                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000005                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54931.261770                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54931.261770                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54931.261770                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        83500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -153,27 +169,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets 27833.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               204                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                204                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               204                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             858                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              858                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             858                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     45872500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     45872500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     45872500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000004                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000004                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000004                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53464.452214                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53464.452214                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53464.452214                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          204                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          204                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          204                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          204                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          204                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          204                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          858                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          858                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          858                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          858                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          858                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          858                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     45872500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     45872500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     45872500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     45872500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     45872500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     45872500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53464.452214                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53464.452214                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53464.452214                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9107352                       # number of replacements
 system.cpu.dcache.tagsinuse               4082.611665                       # Cycle average of tags in use
@@ -181,32 +200,49 @@ system.cpu.dcache.total_refs                595070081                       # To
 system.cpu.dcache.sampled_refs                9111448                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  65.310155                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            12612838000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4082.611665                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.996731                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              437271428                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             157798653                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               595070081                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              595070081                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              7324235                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             2929849                       # number of WriteReq misses
-system.cpu.dcache.demand_misses              10254084                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses             10254084                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   180892053500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency  110288339500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency    291180393000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   291180393000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.016474                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.018229                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.016940                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.016940                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24697.740242                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 37643.011466                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 28396.528934                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 28396.528934                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4082.611665                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.996731                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.996731                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    437271428                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       437271428                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    157798653                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      157798653                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     595070081                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        595070081                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    595070081                       # number of overall hits
+system.cpu.dcache.overall_hits::total       595070081                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7324235                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7324235                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      2929849                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      2929849                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data     10254084                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       10254084                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     10254084                       # number of overall misses
+system.cpu.dcache.overall_misses::total      10254084                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 180892053500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 180892053500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 110288339500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 110288339500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 291180393000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 291180393000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 291180393000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 291180393000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016474                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.018229                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.016940                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.016940                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24697.740242                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37643.011466                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 28396.528934                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 28396.528934                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs     10999000                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets   8091026500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs              2761                       # number of cycles access was blocked
@@ -215,32 +251,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  3983.701557
 system.cpu.dcache.avg_blocked_cycles::no_targets 38714.156866                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3058572                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits            101953                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          1040683                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            1142636                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           1142636                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7222282                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1889166                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9111448                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9111448                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156087671000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  59191835500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 215279506500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 215279506500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011754                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.015052                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.015052                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21611.960181                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 31332.257462                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23627.364882                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23627.364882                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      3058572                       # number of writebacks
+system.cpu.dcache.writebacks::total           3058572                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data       101953                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total       101953                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      1040683                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      1040683                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      1142636                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      1142636                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      1142636                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      1142636                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222282                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7222282                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889166                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889166                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9111448                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9111448                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9111448                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9111448                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156087671000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 156087671000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  59191835500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  59191835500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 215279506500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 215279506500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 215279506500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 215279506500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011754                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015052                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21611.960181                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31332.257462                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23627.364882                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23627.364882                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2686299                       # number of replacements
 system.cpu.l2cache.tagsinuse             26355.239368                       # Cycle average of tags in use
@@ -248,36 +292,72 @@ system.cpu.l2cache.total_refs                 7564573                       # To
 system.cpu.l2cache.sampled_refs               2710943                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.790384                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          223979031000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15511.274798                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10843.964569                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.473367                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.330932                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5414817                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3058572                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits             1000333                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6415150                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6415150                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1807881                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            889275                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2697156                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2697156                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   94453509000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  46507390000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency   140960899000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency  140960899000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7222698                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3058572                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1889608                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9112306                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9112306                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.250305                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.470613                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.295990                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.295990                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52245.423786                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52298.096764                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52262.790510                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52262.790510                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 10843.964569                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     26.537327                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15484.737472                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.330932                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000810                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.472557                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.804298                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      5414817                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5414817                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3058572                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3058572                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1000333                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1000333                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      6415150                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6415150                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      6415150                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6415150                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          858                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1807023                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1807881                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       889275                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       889275                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          858                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2696298                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2697156                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          858                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2696298                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2697156                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     44903500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  94408605500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94453509000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46507390000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46507390000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     44903500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 140915995500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 140960899000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     44903500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 140915995500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 140960899000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          858                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7221840                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7222698                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3058572                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3058572                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889608                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889608                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          858                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9111448                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9112306                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          858                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9111448                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9112306                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250216                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.470613                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.295924                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.295924                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52335.081585                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52245.381215                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52298.096764                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52335.081585                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52262.767506                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52335.081585                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52262.767506                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs       580500                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs               70                       # number of cycles access was blocked
@@ -286,30 +366,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8292.857143
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1170911                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1807881                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       889275                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2697156                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2697156                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  72354298500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  35671113500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 108025412000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 108025412000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250305                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.470613                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.295990                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.295990                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40021.604575                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40112.578786                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40051.599537                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40051.599537                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks      1170911                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1170911                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          858                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1807023                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1807881                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       889275                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       889275                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          858                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2696298                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2697156                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          858                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2696298                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2697156                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     34440500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  72319858000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  72354298500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35671113500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35671113500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     34440500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107990971500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 108025412000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     34440500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107990971500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 108025412000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250216                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.470613                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.295924                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.295924                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40140.442890                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40021.548149                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40112.578786                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40140.442890                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40051.571265                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40140.442890                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40051.571265                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 4951679e2c2e613c12a03bec262632306c37f6d0..66f7d63e234724240dd0ac6ec786ddbb07a0c4aa 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
index 35ea78ab1edc31a4cbef82048c193a61c5e54c4d..17636478ef82d4cec658b2133d1b045f554eabff 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:43:49
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:26:22
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 3e098da07623204b3df1371dd62f0cf1a67ea61f..a211c592b59aa3e34434cfab3bc83e8fe87d14c5 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.615292                       # Nu
 sim_ticks                                615292058500                       # Number of ticks simulated
 final_tick                               615292058500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 151558                       # Simulator instruction rate (inst/s)
-host_tick_rate                               53715526                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208624                       # Number of bytes of host memory used
-host_seconds                                 11454.64                       # Real time elapsed on the host
+host_inst_rate                                 195644                       # Simulator instruction rate (inst/s)
+host_op_rate                                   195644                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               69340417                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211040                       # Number of bytes of host memory used
+host_seconds                                  8873.50                       # Real time elapsed on the host
 sim_insts                                  1736043781                       # Number of instructions simulated
+sim_ops                                    1736043781                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   173080384                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  60288                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 74996480                       # Number of bytes written to this memory
@@ -272,6 +274,7 @@ system.cpu.iew.wb_rate                       1.916228                       # in
 system.cpu.iew.wb_fanout                     0.790955                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts     1819780126                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1819780126                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       736139047                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              29                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts          19443221                       # The number of times a branch was mispredicted
@@ -292,7 +295,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total   1119336917                       # Number of insts commited each cycle
-system.cpu.commit.count                    1819780126                       # Number of instructions committed
+system.cpu.commit.committedInsts           1819780126                       # Number of instructions committed
+system.cpu.commit.committedOps             1819780126                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      605324165                       # Number of memory references committed
 system.cpu.commit.loads                     444595663                       # Number of loads committed
@@ -308,6 +312,7 @@ system.cpu.rob.rob_writes                  5217723058                       # Th
 system.cpu.timesIdled                          398057                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                         5523098                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                  1736043781                       # Number of Instructions Simulated
+system.cpu.committedOps                    1736043781                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total            1736043781                       # Number of Instructions Simulated
 system.cpu.cpi                               0.708844                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         0.708844                       # CPI: Total CPI of All Threads
@@ -325,26 +330,39 @@ system.cpu.icache.total_refs                385399748                       # To
 system.cpu.icache.sampled_refs                    942                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               409129.244161                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            746.155324                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.364334                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              385399748                       # number of ReadReq hits
-system.cpu.icache.demand_hits               385399748                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              385399748                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1348                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1348                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1348                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       47398000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        47398000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       47398000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          385401096                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           385401096                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          385401096                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000003                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000003                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000003                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35161.721068                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35161.721068                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35161.721068                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     746.155324                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.364334                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.364334                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    385399748                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       385399748                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     385399748                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        385399748                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    385399748                       # number of overall hits
+system.cpu.icache.overall_hits::total       385399748                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1348                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1348                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1348                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1348                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1348                       # number of overall misses
+system.cpu.icache.overall_misses::total          1348                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     47398000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     47398000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     47398000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     47398000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     47398000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     47398000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    385401096                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    385401096                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    385401096                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    385401096                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    385401096                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    385401096                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000003                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000003                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000003                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35161.721068                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35161.721068                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35161.721068                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -353,27 +371,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               406                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                406                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               406                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             942                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              942                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             942                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     33448000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     33448000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     33448000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000002                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000002                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000002                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35507.430998                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35507.430998                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35507.430998                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          406                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          406                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          406                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          406                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          406                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          406                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          942                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          942                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          942                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          942                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          942                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          942                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     33448000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     33448000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     33448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     33448000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     33448000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     33448000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000002                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35507.430998                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35507.430998                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35507.430998                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9159821                       # number of replacements
 system.cpu.dcache.tagsinuse               4086.961398                       # Cycle average of tags in use
@@ -381,38 +402,59 @@ system.cpu.dcache.total_refs                693411949                       # To
 system.cpu.dcache.sampled_refs                9163917                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  75.667637                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             5157991000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4086.961398                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997793                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              537597174                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             155814773                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                2                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits               693411947                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              693411947                       # number of overall hits
-system.cpu.dcache.ReadReq_misses             10313435                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             4913729                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses              15227164                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses             15227164                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   172073260500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency  137521396881                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        38500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency    309594657381                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   309594657381                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          547910609                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses            3                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           708639111                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          708639111                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.018823                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.030572                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.333333                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.021488                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.021488                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 16684.379210                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 27987.175703                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        38500                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 20331.734615                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 20331.734615                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4086.961398                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997793                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997793                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    537597174                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       537597174                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    155814773                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      155814773                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            2                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            2                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data     693411947                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        693411947                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    693411947                       # number of overall hits
+system.cpu.dcache.overall_hits::total       693411947                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     10313435                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      10313435                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      4913729                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      4913729                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data     15227164                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       15227164                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     15227164                       # number of overall misses
+system.cpu.dcache.overall_misses::total      15227164                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 172073260500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 172073260500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 137521396881                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 137521396881                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        38500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        38500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 309594657381                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 309594657381                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 309594657381                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 309594657381                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    547910609                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    547910609                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total            3                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    708639111                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    708639111                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    708639111                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    708639111                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.018823                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.030572                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.333333                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.021488                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.021488                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 16684.379210                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27987.175703                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38500                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20331.734615                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20331.734615                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs    119268264                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets   2148368000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs             37813                       # number of cycles access was blocked
@@ -421,36 +463,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  3154.160315
 system.cpu.dcache.avg_blocked_cycles::no_targets 32994.455792                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3077535                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           3034555                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          3028693                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            6063248                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           6063248                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7278880                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1885036                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9163916                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9163916                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  81039107500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  38640356536                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 119679464036                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 119679464036                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.013285                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011728                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.333333                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.012932                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.012932                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11133.458375                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 20498.471401                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35500                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 13059.860439                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 13059.860439                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      3077535                       # number of writebacks
+system.cpu.dcache.writebacks::total           3077535                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      3034555                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      3034555                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3028693                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3028693                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      6063248                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      6063248                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      6063248                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      6063248                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7278880                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7278880                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1885036                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1885036                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9163916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9163916                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9163916                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9163916                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  81039107500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  81039107500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  38640356536                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  38640356536                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        35500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        35500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 119679464036                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 119679464036                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 119679464036                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 119679464036                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.013285                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011728                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.333333                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.012932                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.012932                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11133.458375                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 20498.471401                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        35500                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 13059.860439                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 13059.860439                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2693797                       # number of replacements
 system.cpu.l2cache.tagsinuse             26669.588705                       # Cycle average of tags in use
@@ -458,36 +510,72 @@ system.cpu.l2cache.total_refs                 7633154                       # To
 system.cpu.l2cache.sampled_refs               2718439                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.807918                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          126954186500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15903.024773                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10766.563932                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.485322                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.328569                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5458962                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3077535                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits             1001516                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6460478                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6460478                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1820852                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            883529                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2704381                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2704381                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   62524059000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  30450873000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency    92974932000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency   92974932000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7279814                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3077535                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1885045                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9164859                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9164859                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.250123                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.468704                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.295082                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.295082                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34337.803951                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34465.052081                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34379.376279                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34379.376279                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 10766.563932                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     21.661075                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15881.363698                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.328569                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000661                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.484661                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.813891                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      5458962                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5458962                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3077535                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3077535                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1001516                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1001516                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      6460478                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6460478                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      6460478                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6460478                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          942                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1819910                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1820852                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       883529                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       883529                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          942                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2703439                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2704381                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          942                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2703439                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2704381                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32355500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  62491703500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  62524059000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  30450873000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  30450873000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32355500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data  92942576500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total  92974932000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32355500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data  92942576500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total  92974932000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          942                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7278872                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7279814                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3077535                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3077535                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1885045                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1885045                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          942                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9163917                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9164859                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          942                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9163917                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9164859                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250026                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.468704                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.295009                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.295009                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34347.664544                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34337.798847                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34465.052081                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34347.664544                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34379.387329                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34347.664544                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34379.387329                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs     17570000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs             1704                       # number of cycles access was blocked
@@ -496,30 +584,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs 10311.032864
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1171820                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1820852                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       883529                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2704381                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2704381                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  56737753000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  27632234500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  84369987500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  84369987500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250123                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.468704                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.295082                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.295082                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31160.002570                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31274.847232                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31197.522649                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31197.522649                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks      1171820                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1171820                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          942                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1819910                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1820852                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       883529                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       883529                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          942                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2703439                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2704381                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          942                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2703439                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2704381                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     29342500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  56708410500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  56737753000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  27632234500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  27632234500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     29342500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  84340645000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  84369987500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     29342500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  84340645000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  84369987500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250026                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.468704                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.295009                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.295009                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31149.150743                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31160.008187                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31274.847232                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31149.150743                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31197.539504                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31149.150743                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31197.539504                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 52ac7c9204b583866a99146ec165a202c12456cd..d36004a3ff185547c0cbdbb564280f9ae88d72c0 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
index 3465b9fda5e4159f91fd9bf3486007bbb235e857..632f371aaf95951c63f6dd0818e7122b89331169 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:45:21
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:29:07
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 1f32f6942886e9d9ecb17de1334426a3cd04d19d..2d84c17baa6ae96364e3fe869d46ee503d97326e 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.913189                       # Nu
 sim_ticks                                913189263000                       # Number of ticks simulated
 final_tick                               913189263000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4221832                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2118570165                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 198896                       # Number of bytes of host memory used
-host_seconds                                   431.04                       # Real time elapsed on the host
+host_inst_rate                                5189226                       # Simulator instruction rate (inst/s)
+host_op_rate                                  5189226                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2604020675                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 200656                       # Number of bytes of host memory used
+host_seconds                                   350.68                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
+sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  9280309971                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             7305514036                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                827777307                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   29                       # Nu
 system.cpu.numCycles                       1826378527                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1819780127                       # Number of instructions executed
+system.cpu.committedInsts                  1819780127                       # Number of instructions committed
+system.cpu.committedOps                    1819780127                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
 system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
index b74c065090ae56785fbe89a681efc5afc39f26fd..70d2dba0c07dca18d9b88bb1b1b607c1f287b912 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
index 5e40861f71e74d86e4a9a9bffd3f9565d7550aef..91c7dc82f5de3da893529a11445a8be37a407bd3 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:52:43
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:35:09
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/60.bzip2/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 99a9118585c3945d53f921133e0fb89eaa9c7c92..52ac717c25932bc639af9aa6d9a86e14a62982dd 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.663444                       # Nu
 sim_ticks                                2663443716000                       # Number of ticks simulated
 final_tick                               2663443716000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1948044                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2851171142                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207608                       # Number of bytes of host memory used
-host_seconds                                   934.16                       # Real time elapsed on the host
+host_inst_rate                                2433308                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2433308                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3561407770                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209524                       # Number of bytes of host memory used
+host_seconds                                   747.86                       # Real time elapsed on the host
 sim_insts                                  1819780127                       # Number of instructions simulated
+sim_ops                                    1819780127                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   172614208                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  51328                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 74939072                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   29                       # Nu
 system.cpu.numCycles                       5326887432                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1819780127                       # Number of instructions executed
+system.cpu.committedInsts                  1819780127                       # Number of instructions committed
+system.cpu.committedOps                    1819780127                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1725565901                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 805526                       # Number of float alu accesses
 system.cpu.num_func_calls                    33534877                       # number of times a function call or return occured
@@ -79,26 +82,39 @@ system.cpu.icache.total_refs               1826377708                       # To
 system.cpu.icache.sampled_refs                    802                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               2277278.937656                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            612.356766                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.299002                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1826377708                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1826377708                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1826377708                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  802                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   802                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  802                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       44912000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        44912000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       44912000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1826378510                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1826378510                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1826378510                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     612.356766                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.299002                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.299002                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1826377708                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1826377708                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1826377708                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1826377708                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1826377708                       # number of overall hits
+system.cpu.icache.overall_hits::total      1826377708                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           802                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            802                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          802                       # number of overall misses
+system.cpu.icache.overall_misses::total           802                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     44912000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     44912000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     44912000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     44912000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     44912000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     44912000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1826378510                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1826378510                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1826378510                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1826378510                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1826378510                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1826378510                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -107,26 +123,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             802                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              802                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             802                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     42506000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     42506000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     42506000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          802                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          802                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          802                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     42506000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     42506000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     42506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     42506000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     42506000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     42506000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9107638                       # number of replacements
 system.cpu.dcache.tagsinuse               4079.504248                       # Cycle average of tags in use
@@ -134,32 +148,49 @@ system.cpu.dcache.total_refs                596212431                       # To
 system.cpu.dcache.sampled_refs                9111734                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  65.433476                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            40989969000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4079.504248                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.995973                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              437373249                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             158839182                       # number of WriteReq hits
-system.cpu.dcache.demand_hits               596212431                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              596212431                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              7222414                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1889320                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               9111734                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              9111734                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   177010400000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   63798266000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency    240808666000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   240808666000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          444595663                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         160728502                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           605324165                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          605324165                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.016245                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.011755                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.015053                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.015053                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24508.481513                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33767.845574                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 26428.412638                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 26428.412638                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4079.504248                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.995973                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.995973                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    437373249                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       437373249                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    158839182                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      158839182                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data     596212431                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        596212431                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    596212431                       # number of overall hits
+system.cpu.dcache.overall_hits::total       596212431                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7222414                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7222414                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1889320                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1889320                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9111734                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9111734                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9111734                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9111734                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 177010400000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 177010400000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  63798266000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  63798266000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 240808666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 240808666000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 240808666000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 240808666000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    444595663                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    160728502                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    605324165                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    605324165                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.016245                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.011755                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.015053                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.015053                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24508.481513                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33767.845574                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26428.412638                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26428.412638                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -168,30 +199,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3058802                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7222414                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1889320                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9111734                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9111734                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155343158000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  58130306000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 213473464000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 213473464000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.016245                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.011755                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.015053                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.015053                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21508.481513                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30767.845574                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23428.412638                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      3058802                       # number of writebacks
+system.cpu.dcache.writebacks::total           3058802                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222414                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7222414                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889320                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889320                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9111734                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9111734                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9111734                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9111734                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155343158000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 155343158000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  58130306000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  58130306000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213473464000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 213473464000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213473464000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 213473464000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.016245                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.011755                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.015053                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21508.481513                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30767.845574                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23428.412638                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23428.412638                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2686269                       # number of replacements
 system.cpu.l2cache.tagsinuse             26040.087196                       # Cycle average of tags in use
@@ -199,36 +232,72 @@ system.cpu.l2cache.total_refs                 7565346                       # To
 system.cpu.l2cache.sampled_refs               2710912                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.790701                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          582065656000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15312.508302                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10727.578894                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.467301                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.327380                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5415352                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3058802                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits             1000087                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6415439                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6415439                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1807864                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            889233                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2697097                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2697097                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   94008928000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  46240116000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency   140249044000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency  140249044000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7223216                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3058802                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1889320                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9112536                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9112536                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.250285                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.470663                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.295977                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.295977                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 10727.578894                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     29.806952                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15282.701350                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.327380                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000910                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.466391                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.794680                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      5415352                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5415352                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3058802                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3058802                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data      1000087                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total      1000087                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      6415439                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6415439                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      6415439                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6415439                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          802                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1807062                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1807864                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       889233                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       889233                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          802                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2696295                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2697097                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          802                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2696295                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2697097                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     41704000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  93967224000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94008928000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46240116000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46240116000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     41704000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 140207340000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 140249044000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     41704000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 140207340000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 140249044000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          802                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7222414                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7223216                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3058802                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3058802                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889320                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889320                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          802                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9111734                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9112536                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          802                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9111734                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9112536                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250202                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.470663                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.295915                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.295915                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -237,30 +306,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1170923                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1807864                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       889233                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2697097                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2697097                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  72314560000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  35569320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 107883880000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 107883880000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250285                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.470663                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.295977                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.295977                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks      1170923                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1170923                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          802                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1807062                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1807864                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       889233                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       889233                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          802                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2696295                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2697097                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          802                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2696295                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2697097                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     32080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  72282480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  72314560000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35569320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35569320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     32080000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107851800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 107883880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     32080000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107851800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 107883880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250202                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.470663                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.295915                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.295915                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 5b9d120fe835d4a0e4d2dabe77ba94c506435bbe..51e908aa2aeb84901148c47380277ccaac44df16 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
index 90c937ca7c7af05a67516451f75144bb22093f00..4a2c0420601920ccea350e808d789ffb0fabcfda 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:28:08
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 8595a64e29cb753b09e1eb0986fb25e783507f94..1d3623ac5294239da4ebf691db39d20aed2ec84c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.483300                       # Nu
 sim_ticks                                483300356500                       # Number of ticks simulated
 final_tick                               483300356500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  96252                       # Simulator instruction rate (inst/s)
-host_tick_rate                               26997552                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 256412                       # Number of bytes of host memory used
-host_seconds                                 17901.64                       # Real time elapsed on the host
-sim_insts                                  1723073849                       # Number of instructions simulated
+host_inst_rate                                 175200                       # Simulator instruction rate (inst/s)
+host_op_rate                                   195449                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               54820940                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 223460                       # Number of bytes of host memory used
+host_seconds                                  8815.98                       # Real time elapsed on the host
+sim_insts                                  1544563036                       # Number of instructions simulated
+sim_ops                                    1723073849                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   188191232                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  45952                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 77928320                       # Number of bytes written to this memory
@@ -282,7 +284,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       2.025916                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.632400                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts     1723073867                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts     1544563054                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps       1723073867                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       464107908                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             503                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts          18315306                       # The number of times a branch was mispredicted
@@ -303,7 +306,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    888130278                       # Number of insts commited each cycle
-system.cpu.commit.count                    1723073867                       # Number of instructions committed
+system.cpu.commit.committedInsts           1544563054                       # Number of instructions committed
+system.cpu.commit.committedOps             1723073867                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                      660773817                       # Number of memory references committed
 system.cpu.commit.loads                     485926771                       # Number of loads committed
@@ -318,12 +322,13 @@ system.cpu.rob.rob_reads                   2976436889                       # Th
 system.cpu.rob.rob_writes                  4442782654                       # The number of ROB writes
 system.cpu.timesIdled                          920078                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                        10281556                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                  1723073849                       # Number of Instructions Simulated
-system.cpu.committedInsts_total            1723073849                       # Number of Instructions Simulated
-system.cpu.cpi                               0.560975                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.560975                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.782612                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.782612                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                  1544563036                       # Number of Instructions Simulated
+system.cpu.committedOps                    1723073849                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total            1544563036                       # Number of Instructions Simulated
+system.cpu.cpi                               0.625809                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         0.625809                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               1.597933                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         1.597933                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               9941434858                       # number of integer regfile reads
 system.cpu.int_regfile_writes              1939754373                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        96                       # number of floating regfile reads
@@ -336,26 +341,39 @@ system.cpu.icache.total_refs                285077321                       # To
 system.cpu.icache.sampled_refs                    746                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               382141.180965                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            609.966952                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.297835                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              285077321                       # number of ReadReq hits
-system.cpu.icache.demand_hits               285077321                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              285077321                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 1018                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  1018                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 1018                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       35270500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        35270500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       35270500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          285078339                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           285078339                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          285078339                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000004                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000004                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000004                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34646.856582                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34646.856582                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34646.856582                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     609.966952                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.297835                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.297835                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    285077321                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       285077321                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     285077321                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        285077321                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    285077321                       # number of overall hits
+system.cpu.icache.overall_hits::total       285077321                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         1018                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          1018                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         1018                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           1018                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         1018                       # number of overall misses
+system.cpu.icache.overall_misses::total          1018                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     35270500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     35270500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     35270500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     35270500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     35270500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     35270500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    285078339                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    285078339                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    285078339                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    285078339                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    285078339                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    285078339                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000004                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000004                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000004                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34646.856582                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34646.856582                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34646.856582                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -364,27 +382,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               272                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                272                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               272                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             746                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              746                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             746                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     25653000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     25653000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     25653000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000003                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000003                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000003                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34387.399464                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34387.399464                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34387.399464                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          272                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          272                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          272                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          272                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          272                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          272                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          746                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          746                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          746                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          746                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          746                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          746                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     25653000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     25653000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     25653000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     25653000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     25653000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     25653000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000003                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34387.399464                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34387.399464                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34387.399464                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9570609                       # number of replacements
 system.cpu.dcache.tagsinuse               4087.729265                       # Cycle average of tags in use
@@ -392,40 +413,63 @@ system.cpu.dcache.total_refs                666885051                       # To
 system.cpu.dcache.sampled_refs                9574705                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  69.650715                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle             3484295000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4087.729265                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997981                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              499489564                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             167395365                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               60                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits                62                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               666884929                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              666884929                       # number of overall hits
-system.cpu.dcache.ReadReq_misses             10445560                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             5190682                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              3                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses              15636242                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses             15636242                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   184478558500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency  128511717246                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency       113500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency    312990275746                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   312990275746                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          509935124                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           63                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses            62                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           682521171                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          682521171                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.020484                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.030076                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.047619                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.022910                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.022910                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 17660.954367                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 24758.156490                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency 37833.333333                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 20016.975674                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 20016.975674                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4087.729265                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997981                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997981                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    499489564                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       499489564                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    167395365                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      167395365                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           60                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           60                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           62                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           62                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     666884929                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        666884929                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    666884929                       # number of overall hits
+system.cpu.dcache.overall_hits::total       666884929                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data     10445560                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total      10445560                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      5190682                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      5190682                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            3                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            3                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data     15636242                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total       15636242                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data     15636242                       # number of overall misses
+system.cpu.dcache.overall_misses::total      15636242                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 184478558500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 184478558500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data 128511717246                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total 128511717246                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data       113500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total       113500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 312990275746                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 312990275746                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 312990275746                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 312990275746                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    509935124                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    509935124                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           63                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           62                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           62                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    682521171                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    682521171                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    682521171                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    682521171                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.020484                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.030076                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.047619                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.022910                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.022910                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 17660.954367                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 24758.156490                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 37833.333333                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 20016.975674                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 20016.975674                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs    266779202                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets       225500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs             90534                       # number of cycles access was blocked
@@ -434,33 +478,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs  2946.729428
 system.cpu.dcache.avg_blocked_cycles::no_targets 16107.142857                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3128454                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits           2763491                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits          3298046                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            3                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits            6061537                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits           6061537                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7682069                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1892636                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9574705                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9574705                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  92052400500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  45263240996                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 137315641496                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 137315641496                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.015065                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010966                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.014028                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.014028                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 11982.761480                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 23915.449667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 14341.501017                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 14341.501017                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      3128454                       # number of writebacks
+system.cpu.dcache.writebacks::total           3128454                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data      2763491                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total      2763491                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data      3298046                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total      3298046                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            3                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data      6061537                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total      6061537                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data      6061537                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total      6061537                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7682069                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7682069                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1892636                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1892636                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9574705                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9574705                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9574705                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9574705                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  92052400500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  92052400500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  45263240996                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  45263240996                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 137315641496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 137315641496                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 137315641496                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 137315641496                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.015065                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010966                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.014028                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.014028                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11982.761480                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 23915.449667                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 14341.501017                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 14341.501017                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2928111                       # number of replacements
 system.cpu.l2cache.tagsinuse             26779.513847                       # Cycle average of tags in use
@@ -468,36 +521,75 @@ system.cpu.l2cache.total_refs                 7850665                       # To
 system.cpu.l2cache.sampled_refs               2955434                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.656349                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          102043879500                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15980.141778                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         10799.372069                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.487675                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.329571                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5654844                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3128454                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              980108                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6634952                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6634952                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             2027970                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            912529                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2940499                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2940499                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   69622687500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  31651212500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency   101273900000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency  101273900000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7682814                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3128454                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1892637                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9575451                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9575451                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.263962                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.482147                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.307087                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.307087                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34331.221616                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34685.157951                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34441.059154                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34441.059154                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 10799.372069                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     11.094827                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15969.046951                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.329571                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000339                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.487337                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.817246                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           27                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      5654817                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5654844                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3128454                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3128454                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       980108                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       980108                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           27                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      6634925                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6634952                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           27                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      6634925                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6634952                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          719                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      2027251                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      2027970                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       912529                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       912529                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          719                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2939780                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2940499                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          719                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2939780                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2940499                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     24699000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  69597988500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  69622687500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  31651212500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  31651212500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     24699000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 101249201000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 101273900000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     24699000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 101249201000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 101273900000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          746                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7682068                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7682814                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3128454                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3128454                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1892637                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1892637                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          746                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9574705                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9575451                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          746                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9574705                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9575451                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.963807                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.263894                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.482147                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.963807                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.307036                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.963807                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.307036                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34351.877608                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34331.214290                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34685.157951                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34351.877608                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34441.080965                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34351.877608                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34441.080965                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs     56425000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs             6634                       # number of cycles access was blocked
@@ -506,31 +598,53 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs  8505.426590
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1217630                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               11                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                11                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               11                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        2027959                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       912529                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2940488                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2940488                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  63243262500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  28812389000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency  92055651500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency  92055651500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.263960                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.482147                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.307086                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.307086                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31185.671160                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31574.217367                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31306.249677                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31306.249677                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks      1217630                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1217630                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            1                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           10                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           11                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            1                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           11                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            1                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           11                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          718                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      2027241                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      2027959                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       912529                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       912529                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          718                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2939770                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2940488                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          718                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2939770                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2940488                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     22382500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  63220880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  63243262500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  28812389000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  28812389000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     22382500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data  92033269000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total  92055651500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     22382500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data  92033269000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total  92055651500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.962466                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.263893                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.482147                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.962466                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.307035                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.962466                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.307035                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31173.398329                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31185.675507                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31574.217367                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31173.398329                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31306.282124                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31173.398329                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31306.282124                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index bbede2479c62fa86ebdf7ec9d75a8e35545da55a..6c19f0c57ec2c0ac47423e4e898e9ddb1e680727 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index e599bde0bd983334868549cad5c4ef01305372fa..1bac004a30bcc31e4d96db305f12e77a8c613545 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:37:28
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:28:58
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index e23300649aeb014a733ec1bc0ed7a02bc0c1d72d..1bd7f49d7f27519df7298c1e27b258f3e420ae2b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.861538                       # Nu
 sim_ticks                                861538205000                       # Number of ticks simulated
 final_tick                               861538205000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3027828                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1513916118                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210380                       # Number of bytes of host memory used
-host_seconds                                   569.08                       # Real time elapsed on the host
-sim_insts                                  1723073862                       # Number of instructions simulated
+host_inst_rate                                3097767                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3455787                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1727895925                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 212936                       # Number of bytes of host memory used
+host_seconds                                   498.61                       # Real time elapsed on the host
+sim_insts                                  1544563049                       # Number of instructions simulated
+sim_ops                                    1723073862                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  7759650064                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             6178262392                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                624158392                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                   46                       # Nu
 system.cpu.numCycles                       1723076411                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1723073862                       # Number of instructions executed
+system.cpu.committedInsts                  1544563049                       # Number of instructions committed
+system.cpu.committedOps                    1723073862                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
index 71abd898d7a4976cc82a435efac12603c1bb95f5..9736169e40e1d98969c4e86f29cb1bb7d5bcdec7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index 8198567b7138e69b5be4aa1f67cc1a54f3ae7b99..424d2bbd8dad00f7181cc0f2bbb193f53e86aad4 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:45:39
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:33:49
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/60.bzip2/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 04e3122e612426f9672d53aa3c358d9733b7f6e3..e00ec713c2c75ef22af1ba5e0023ba57d996b288 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.431420                       # Nu
 sim_ticks                                2431419954000                       # Number of ticks simulated
 final_tick                               2431419954000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1410228                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1996689457                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219344                       # Number of bytes of host memory used
-host_seconds                                  1217.73                       # Real time elapsed on the host
-sim_insts                                  1717270343                       # Number of instructions simulated
+host_inst_rate                                1647360                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1838469                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2603021191                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221840                       # Number of bytes of host memory used
+host_seconds                                   934.08                       # Real time elapsed on the host
+sim_insts                                  1538759609                       # Number of instructions simulated
+sim_ops                                    1717270343                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   172766016                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  39424                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 75006720                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                   46                       # Nu
 system.cpu.numCycles                       4862839908                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       1717270343                       # Number of instructions executed
+system.cpu.committedInsts                  1538759609                       # Number of instructions committed
+system.cpu.committedOps                    1717270343                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            1536941850                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     36                       # Number of float alu accesses
 system.cpu.num_func_calls                    27330134                       # number of times a function call or return occured
@@ -89,26 +92,39 @@ system.cpu.icache.total_refs               1544564961                       # To
 system.cpu.icache.sampled_refs                    638                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               2420948.214734                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            514.872896                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.251403                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             1544564961                       # number of ReadReq hits
-system.cpu.icache.demand_hits              1544564961                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             1544564961                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  638                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   638                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  638                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       34804000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        34804000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       34804000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         1544565599                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          1544565599                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         1544565599                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54551.724138                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54551.724138                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54551.724138                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     514.872896                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.251403                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.251403                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   1544564961                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      1544564961                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    1544564961                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       1544564961                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   1544564961                       # number of overall hits
+system.cpu.icache.overall_hits::total      1544564961                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          638                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           638                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          638                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            638                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          638                       # number of overall misses
+system.cpu.icache.overall_misses::total           638                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     34804000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     34804000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     34804000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     34804000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     34804000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     34804000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   1544565599                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   1544565599                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   1544565599                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   1544565599                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   1544565599                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   1544565599                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54551.724138                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54551.724138                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54551.724138                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -117,26 +133,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             638                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              638                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             638                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     32890000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     32890000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     32890000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 51551.724138                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 51551.724138                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          638                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          638                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          638                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          638                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          638                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          638                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     32890000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     32890000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     32890000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     32890000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     32890000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     32890000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51551.724138                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9111140                       # number of replacements
 system.cpu.dcache.tagsinuse               4083.719979                       # Cycle average of tags in use
@@ -144,36 +158,57 @@ system.cpu.dcache.total_refs                645855060                       # To
 system.cpu.dcache.sampled_refs                9115236                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  70.854453                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            25923025000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4083.719979                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997002                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits              475158040                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             170696898                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               61                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits                61                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits               645854938                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits              645854938                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              7226087                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1889149                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               9115236                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              9115236                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   177140908000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   63824222000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency    240965130000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   240965130000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses          482384127                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         172586047                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           61                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses            61                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses           654970174                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses          654970174                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.014980                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.010946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.013917                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.013917                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24514.084594                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33784.641656                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 26435.424162                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 26435.424162                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4083.719979                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997002                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997002                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data    475158040                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total       475158040                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    170696898                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      170696898                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           61                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           61                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           61                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           61                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data     645854938                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total        645854938                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data    645854938                       # number of overall hits
+system.cpu.dcache.overall_hits::total       645854938                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7226087                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7226087                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1889149                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1889149                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9115236                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9115236                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9115236                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9115236                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 177140908000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 177140908000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  63824222000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  63824222000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 240965130000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 240965130000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 240965130000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 240965130000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data    482384127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total    482384127                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    172586047                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           61                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           61                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data    654970174                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total    654970174                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data    654970174                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total    654970174                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.014980                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.010946                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.013917                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.013917                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24514.084594                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33784.641656                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26435.424162                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26435.424162                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,30 +217,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3061985                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7226087                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1889149                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9115236                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9115236                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 155462647000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  58156775000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 213619422000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 213619422000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.014980                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.010946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.013917                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.013917                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21514.084594                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30784.641656                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23435.424162                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      3061985                       # number of writebacks
+system.cpu.dcache.writebacks::total           3061985                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7226087                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889149                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889149                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9115236                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9115236                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9115236                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9115236                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 155462647000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 155462647000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  58156775000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  58156775000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 213619422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 213619422000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 213619422000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 213619422000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.014980                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.010946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.013917                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21514.084594                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30784.641656                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23435.424162                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23435.424162                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2687066                       # number of replacements
 system.cpu.l2cache.tagsinuse             26134.517233                       # Cycle average of tags in use
@@ -213,36 +250,75 @@ system.cpu.l2cache.total_refs                 7569171                       # To
 system.cpu.l2cache.sampled_refs               2714383                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.788542                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          538044123000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15027.621217                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11106.896016                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.458607                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.338956                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5417164                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3061985                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              999241                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6416405                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6416405                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1809561                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            889908                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2699469                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2699469                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   94097172000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  46275216000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency   140372388000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency  140372388000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7226725                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3061985                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1889149                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9115874                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9115874                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.250398                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.471063                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.296128                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.296128                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 11106.896016                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     11.181020                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15016.440197                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.338956                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000341                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.458265                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.797562                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           22                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data      5417142                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5417164                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3061985                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3061985                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       999241                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       999241                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           22                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data      6416383                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6416405                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           22                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data      6416383                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6416405                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          616                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1808945                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1809561                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       889908                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       889908                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          616                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2698853                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2699469                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          616                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2698853                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2699469                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     32032000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  94065140000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94097172000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46275216000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46275216000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     32032000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 140340356000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 140372388000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     32032000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 140340356000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 140372388000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          638                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7226087                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7226725                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3061985                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3061985                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889149                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889149                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          638                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9115236                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9115874                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          638                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9115236                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9115874                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.965517                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.250335                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.471063                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.965517                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.296082                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.965517                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.296082                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -251,30 +327,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1171980                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1809561                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       889908                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2699469                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2699469                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  72382440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  35596320000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 107978760000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 107978760000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.250398                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471063                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.296128                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.296128                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks      1171980                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1171980                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          616                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1808945                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1809561                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       889908                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       889908                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          616                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2698853                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2699469                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          616                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2698853                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2699469                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     24640000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  72357800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  72382440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35596320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35596320000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     24640000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 107954120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 107978760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     24640000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 107954120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 107978760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.250335                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.471063                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.296082                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.965517                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.296082                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index fe30d10a3681d4040bf883f9ef29ece668a9ed6f..6cebafbf045dbf18fca1684a5803a3fb25377da7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +97,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +121,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index a5a0064e6c5300721df15656289a74ea4a48b142..23e0a7dabe52d0eb23bf50cfaeb0dd71f62eae3b 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:13:31
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:34:58
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 6725100b83d1267356e952a33315ac92df9a2282..c4996594d0e61bd09f6181cf31f6ecd9caa471f8 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.846007                       # Nu
 sim_ticks                                2846007259500                       # Number of ticks simulated
 final_tick                               2846007259500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2006575                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1218454030                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 204704                       # Number of bytes of host memory used
-host_seconds                                  2335.75                       # Real time elapsed on the host
-sim_insts                                  4686862651                       # Number of instructions simulated
+host_inst_rate                                1815306                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2828411                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1717498350                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210188                       # Number of bytes of host memory used
+host_seconds                                  1657.07                       # Real time elapsed on the host
+sim_insts                                  3008081057                       # Number of instructions simulated
+sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                 37129731755                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read            32105863408                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written               1544656790                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   46                       # Nu
 system.cpu.numCycles                       5692014520                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       4686862651                       # Number of instructions executed
+system.cpu.committedInsts                  3008081057                       # Number of instructions committed
+system.cpu.committedOps                    4686862651                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index e57f67518afbc12d1c555705ce07147ce6c5d07c..a21cde2b27bdefc8504cee03a6b7d1fe66f6452e 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +104,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +118,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +149,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +171,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=bzip2 input.source 1
-cwd=build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -191,7 +203,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index 5d52328851a55b3e4a1e9d4d4bcf9868eebec0c9..0e700a5756066c8a32c3341bc386ac24af32c58c 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 07:30:19
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:48:34
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/60.bzip2/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 spec_init
index 94c5d24c6fd5d15c33d5805c6aec48d7cd63490b..aefb42b3b588dffe820411708766a83dd12f83da 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  5.923548                       # Nu
 sim_ticks                                5923548078000                       # Number of ticks simulated
 final_tick                               5923548078000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1176749                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1487248019                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213688                       # Number of bytes of host memory used
-host_seconds                                  3982.89                       # Real time elapsed on the host
-sim_insts                                  4686862651                       # Number of instructions simulated
+host_inst_rate                                1064786                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1659033                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2096788716                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219100                       # Number of bytes of host memory used
+host_seconds                                  2825.06                       # Real time elapsed on the host
+sim_insts                                  3008081057                       # Number of instructions simulated
+sim_ops                                    4686862651                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   173910080                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  43200                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 75176384                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   46                       # Nu
 system.cpu.numCycles                      11847096156                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                       4686862651                       # Number of instructions executed
+system.cpu.committedInsts                  3008081057                       # Number of instructions committed
+system.cpu.committedOps                    4686862651                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses            4686862580                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -47,26 +50,39 @@ system.cpu.icache.total_refs               4013232252                       # To
 system.cpu.icache.sampled_refs                    675                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               5945529.262222                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            555.713137                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.271344                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits             4013232252                       # number of ReadReq hits
-system.cpu.icache.demand_hits              4013232252                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits             4013232252                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  675                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   675                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  675                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       37800000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        37800000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       37800000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses         4013232927                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses          4013232927                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses         4013232927                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000000                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000000                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000000                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     555.713137                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.271344                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.271344                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst   4013232252                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total      4013232252                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst    4013232252                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total       4013232252                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst   4013232252                       # number of overall hits
+system.cpu.icache.overall_hits::total      4013232252                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           675                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            675                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          675                       # number of overall misses
+system.cpu.icache.overall_misses::total           675                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     37800000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     37800000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     37800000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     37800000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     37800000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     37800000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst   4013232927                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total   4013232927                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst   4013232927                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total   4013232927                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst   4013232927                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total   4013232927                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000000                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000000                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000000                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -75,26 +91,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             675                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              675                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             675                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     35775000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     35775000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     35775000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000000                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000000                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000000                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          675                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          675                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          675                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     35775000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     35775000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     35775000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     35775000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     35775000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     35775000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000000                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                9108581                       # number of replacements
 system.cpu.dcache.tagsinuse               4084.662246                       # Cycle average of tags in use
@@ -102,32 +116,49 @@ system.cpu.dcache.total_refs               1668600409                       # To
 system.cpu.dcache.sampled_refs                9112677                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                 183.107599                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle            58862779000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           4084.662246                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.997232                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits             1231961899                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits             436638510                       # number of WriteReq hits
-system.cpu.dcache.demand_hits              1668600409                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits             1668600409                       # number of overall hits
-system.cpu.dcache.ReadReq_misses              7222850                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses             1889827                       # number of WriteReq misses
-system.cpu.dcache.demand_misses               9112677                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses              9112677                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency   177808540000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency   63869078000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency    241677618000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency   241677618000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses         1239184749                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses         438528337                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses          1677713086                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses         1677713086                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.005829                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.004309                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.005432                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.005432                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 24617.504171                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33796.256483                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 26521.034159                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 26521.034159                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    4084.662246                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.997232                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.997232                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data   1231961899                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total      1231961899                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data    436638510                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total      436638510                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data    1668600409                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total       1668600409                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data   1668600409                       # number of overall hits
+system.cpu.dcache.overall_hits::total      1668600409                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data      7222850                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total       7222850                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data      1889827                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total      1889827                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data      9112677                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total        9112677                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data      9112677                       # number of overall misses
+system.cpu.dcache.overall_misses::total       9112677                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data 177808540000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total 177808540000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  63869078000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total  63869078000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data 241677618000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total 241677618000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data 241677618000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total 241677618000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data   1239184749                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total   1239184749                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data    438528337                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total    438528337                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data   1677713086                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total   1677713086                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data   1677713086                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total   1677713086                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.005829                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.004309                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.005432                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.005432                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24617.504171                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33796.256483                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26521.034159                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26521.034159                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -136,30 +167,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  3053391                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         7222850                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses        1889827                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          9112677                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         9112677                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency 156139990000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency  58199597000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency 214339587000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency 214339587000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.005829                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.004309                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.005432                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.005432                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 21617.504171                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 30796.256483                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23521.034159                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      3053391                       # number of writebacks
+system.cpu.dcache.writebacks::total           3053391                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      7222850                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      7222850                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data      1889827                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total      1889827                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      9112677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      9112677                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      9112677                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      9112677                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 156139990000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 156139990000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  58199597000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total  58199597000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 214339587000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 214339587000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 214339587000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 214339587000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.005829                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.004309                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.005432                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21617.504171                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 30796.256483                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23521.034159                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23521.034159                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements               2706631                       # number of replacements
 system.cpu.l2cache.tagsinuse             26507.350069                       # Cycle average of tags in use
@@ -167,36 +200,72 @@ system.cpu.l2cache.total_refs                 7537629                       # To
 system.cpu.l2cache.sampled_refs               2732923                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.758083                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle          1324806325000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0         15478.805498                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1         11028.544571                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.472376                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.336564                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits               5396930                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits             3053391                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits              999077                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                6396007                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits               6396007                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses             1826595                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses            890750                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses              2717345                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses             2717345                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency   94982940000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency  46319000000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency   141301940000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency  141301940000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses           7223525                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses         3053391                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses         1889827                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses            9113352                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses           9113352                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.252868                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.471339                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.298172                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.298172                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks 11028.544571                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst     19.163936                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data  15459.641562                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.336564                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.000585                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.471791                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.808940                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.data      5396930                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total        5396930                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks      3053391                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total      3053391                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       999077                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total       999077                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.data      6396007                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total         6396007                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.data      6396007                       # number of overall hits
+system.cpu.l2cache.overall_hits::total        6396007                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          675                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data      1825920                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total      1826595                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data       890750                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total       890750                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          675                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data      2716670                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total       2717345                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          675                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data      2716670                       # number of overall misses
+system.cpu.l2cache.overall_misses::total      2717345                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     35100000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data  94947840000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total  94982940000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data  46319000000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total  46319000000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     35100000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data 141266840000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total 141301940000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     35100000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data 141266840000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total 141301940000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          675                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data      7222850                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total      7223525                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks      3053391                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total      3053391                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data      1889827                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total      1889827                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          675                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data      9112677                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total      9113352                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          675                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data      9112677                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total      9113352                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.252798                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.471339                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.298120                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.298120                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -205,30 +274,44 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                 1174631                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses        1826595                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses       890750                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses         2717345                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses        2717345                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency  73063800000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency  35630000000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency 108693800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency 108693800000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.252868                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.471339                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.298172                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.298172                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.writebacks::writebacks      1174631                       # number of writebacks
+system.cpu.l2cache.writebacks::total          1174631                       # number of writebacks
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          675                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data      1825920                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total      1826595                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       890750                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total       890750                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          675                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data      2716670                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total      2717345                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          675                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data      2716670                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total      2717345                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     27000000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data  73036800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total  73063800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data  35630000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total  35630000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     27000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 108666800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total 108693800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     27000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 108666800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total 108693800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.252798                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.471339                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.298120                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.298120                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 64fd65cd8f6c69313bc7efeac49e8d53e156cc22..1763cd3d7fbf17c4f42b76a4ac8bbb37e6b11867 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -202,7 +194,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
 egid=100
 env=
 errout=cerr
index ab1cbef0e10959df79127588d1e94f78f4c0c0c2..ddac6bec8f2979af78d9e1a5939315fdc79bd75e 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 05:57:18
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:36:18
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/inorder-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index db43e1bd883b9a14f1af070a6c75983e0bb173fd..7525585e330a5a338e7339d6bd27b0421454e53b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.041834                       # Nu
 sim_ticks                                 41833966000                       # Number of ticks simulated
 final_tick                                41833966000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 111295                       # Simulator instruction rate (inst/s)
-host_tick_rate                               50660994                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211656                       # Number of bytes of host memory used
-host_seconds                                   825.76                       # Real time elapsed on the host
+host_inst_rate                                 151560                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151560                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68989742                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213560                       # Number of bytes of host memory used
+host_seconds                                   606.38                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
+sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      316032                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 178816                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -68,9 +70,10 @@ system.cpu.comNops                            7723346                       # Nu
 system.cpu.comNonSpec                             389                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                           43665352                       # Number of Integer instructions committed
 system.cpu.comFloats                          3775974                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                    91903056                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total              91903056                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                    91903056                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                      91903056                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total              91903056                       # Number of Instructions committed (Total)
 system.cpu.cpi                               0.910393                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         0.910393                       # CPI: Total CPI of All Threads
@@ -124,26 +127,39 @@ system.cpu.icache.total_refs                  9979713                       # To
 system.cpu.icache.sampled_refs                   9436                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                1057.621132                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1491.782957                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.728410                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                9979713                       # number of ReadReq hits
-system.cpu.icache.demand_hits                 9979713                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                9979713                       # number of overall hits
-system.cpu.icache.ReadReq_misses                11486                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 11486                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                11486                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      291407500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       291407500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      291407500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses            9991199                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses             9991199                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses            9991199                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.001150                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.001150                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.001150                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 25370.668640                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 25370.668640                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 25370.668640                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1491.782957                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.728410                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.728410                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst      9979713                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total         9979713                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst       9979713                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total          9979713                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst      9979713                       # number of overall hits
+system.cpu.icache.overall_hits::total         9979713                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        11486                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11486                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11486                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11486                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11486                       # number of overall misses
+system.cpu.icache.overall_misses::total         11486                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    291407500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    291407500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    291407500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    291407500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    291407500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    291407500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst      9991199                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total      9991199                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst      9991199                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total      9991199                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst      9991199                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total      9991199                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.001150                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.001150                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.001150                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 25370.668640                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 25370.668640                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 25370.668640                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        69500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets        17375                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              2050                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               2050                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              2050                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            9436                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             9436                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            9436                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    222700000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    222700000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    222700000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000944                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000944                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000944                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23601.102162                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23601.102162                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23601.102162                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         2050                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         2050                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         2050                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         2050                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         2050                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         2050                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         9436                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         9436                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         9436                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         9436                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         9436                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         9436                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    222700000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    222700000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    222700000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    222700000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    222700000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    222700000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000944                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000944                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000944                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23601.102162                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23601.102162                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23601.102162                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.tagsinuse               1441.532122                       # Cycle average of tags in use
@@ -180,32 +199,49 @@ system.cpu.dcache.total_refs                 26491206                       # To
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               11916.871795                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1441.532122                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.351937                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               19995645                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               6495561                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                26491206                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               26491206                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  553                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                5542                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  6095                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 6095                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       28393500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     303801000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       332194500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      332194500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000028                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000852                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000230                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000230                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 51344.484629                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 54817.935763                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54502.789171                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54502.789171                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1441.532122                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.351937                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.351937                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     19995645                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        19995645                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6495561                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6495561                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26491206                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26491206                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26491206                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26491206                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          553                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           553                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         5542                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         5542                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         6095                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           6095                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         6095                       # number of overall misses
+system.cpu.dcache.overall_misses::total          6095                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     28393500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     28393500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    303801000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    303801000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    332194500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    332194500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    332194500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    332194500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000028                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000852                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000230                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000230                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51344.484629                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 54817.935763                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54502.789171                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54502.789171                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets     41047000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -214,32 +250,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 49814.320388                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      107                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                78                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             3794                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               3872                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              3872                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             2223                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            2223                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     23213000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     92997500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    116210500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    116210500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48869.473684                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53202.231121                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52276.428250                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52276.428250                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
+system.cpu.dcache.writebacks::total               107                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           78                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           78                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         3794                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         3794                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         3872                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         3872                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         3872                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         3872                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2223                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     23213000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     23213000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     92997500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     92997500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    116210500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    116210500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    116210500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    116210500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48869.473684                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53202.231121                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52276.428250                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52276.428250                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2189.253602                       # Cycle average of tags in use
@@ -247,36 +291,75 @@ system.cpu.l2cache.total_refs                    6704                       # To
 system.cpu.l2cache.sampled_refs                  3282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.042657                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2171.415543                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            17.838059                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.066266                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000544                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  6695                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 107                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   6721                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  6721                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3216                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1722                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 4938                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                4938                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     168327500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     90565000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      258892500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     258892500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              9911                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              11659                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             11659                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.324488                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.985126                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.423535                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.423535                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52340.640547                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52592.915215                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52428.614824                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52428.614824                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks    17.838059                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1820.375269                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    351.040274                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000544                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.055553                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.010713                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.066811                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         6642                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           6695                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         6642                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            6721                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         6642                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           6721                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2794                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3216                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1722                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1722                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2794                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2144                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          4938                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2794                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         4938                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    146193000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     22134500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    168327500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     90565000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     90565000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    146193000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    112699500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    258892500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    146193000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    112699500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    258892500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         9436                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         9911                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         9436                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2223                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        11659                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         9436                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2223                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        11659                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.296100                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.296100                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964462                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.296100                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52323.908375                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52451.421801                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52592.915215                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52323.908375                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52565.065299                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52323.908375                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52565.065299                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -285,30 +368,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3216                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1722                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            4938                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           4938                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    129053500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     69344000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    198397500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    198397500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.324488                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985126                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.423535                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.423535                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40128.575871                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40269.454123                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40177.703524                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40177.703524                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2794                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3216                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2794                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2144                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         4938                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2794                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         4938                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    112072000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16981500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    129053500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     69344000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     69344000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    112072000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     86325500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    198397500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    112072000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     86325500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    198397500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.296100                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.296100                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.296100                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40111.667860                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40240.521327                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40269.454123                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40111.667860                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40263.759328                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40111.667860                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40263.759328                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index a6f9e5430e8b9c5b949d22d776bb49ad4b42e208..10359186bdb59d5f8717fb79a9101ec4b9029cdc 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -497,7 +490,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
 egid=100
 env=
 errout=cerr
index 9901dc40bc4e0b56e1d73ab287a2ede26d62e99a..f5b2c31fdd9ace2e54b122ad01d1db86d760b4c3 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 06:08:28
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:45:24
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/o3-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 55d9dc21f99067e2f5274a97bb9cda273ca9177b..221154573d314f7c5cc4637fe5f6ecb1c0f2ae69 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.029167                       # Nu
 sim_ticks                                 29167093500                       # Number of ticks simulated
 final_tick                                29167093500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 155660                       # Simulator instruction rate (inst/s)
-host_tick_rate                               53933893                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212576                       # Number of bytes of host memory used
-host_seconds                                   540.79                       # Real time elapsed on the host
+host_inst_rate                                 198361                       # Simulator instruction rate (inst/s)
+host_op_rate                                   198361                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               68729352                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 214912                       # Number of bytes of host memory used
+host_seconds                                   424.38                       # Real time elapsed on the host
 sim_insts                                    84179709                       # Number of instructions simulated
+sim_ops                                      84179709                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      332416                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 193856                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -271,6 +273,7 @@ system.cpu.iew.wb_rate                       1.710877                       # in
 system.cpu.iew.wb_fanout                     0.725137                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts       91903055                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps         91903055                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts        40723267                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             389                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           1895854                       # The number of times a branch was mispredicted
@@ -291,7 +294,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total     52161479                       # Number of insts commited each cycle
-system.cpu.commit.count                      91903055                       # Number of instructions committed
+system.cpu.commit.committedInsts             91903055                       # Number of instructions committed
+system.cpu.commit.committedOps               91903055                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       26497301                       # Number of memory references committed
 system.cpu.commit.loads                      19996198                       # Number of loads committed
@@ -307,6 +311,7 @@ system.cpu.rob.rob_writes                   271380444                       # Th
 system.cpu.timesIdled                            2277                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           93138                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                    84179709                       # Number of Instructions Simulated
+system.cpu.committedOps                      84179709                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total              84179709                       # Number of Instructions Simulated
 system.cpu.cpi                               0.692972                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         0.692972                       # CPI: Total CPI of All Threads
@@ -324,26 +329,39 @@ system.cpu.icache.total_refs                 18592194                       # To
 system.cpu.icache.sampled_refs                  10628                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                1749.359616                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1593.002324                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.777833                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               18592194                       # number of ReadReq hits
-system.cpu.icache.demand_hits                18592194                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               18592194                       # number of overall hits
-system.cpu.icache.ReadReq_misses                11853                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 11853                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                11853                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      188036500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       188036500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      188036500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           18604047                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            18604047                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           18604047                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000637                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000637                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000637                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 15864.042858                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 15864.042858                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 15864.042858                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1593.002324                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.777833                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.777833                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     18592194                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        18592194                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      18592194                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         18592194                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     18592194                       # number of overall hits
+system.cpu.icache.overall_hits::total        18592194                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        11853                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         11853                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        11853                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          11853                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        11853                       # number of overall misses
+system.cpu.icache.overall_misses::total         11853                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    188036500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    188036500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    188036500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    188036500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    188036500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    188036500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     18604047                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     18604047                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     18604047                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     18604047                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     18604047                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     18604047                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000637                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000637                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000637                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 15864.042858                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 15864.042858                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 15864.042858                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -352,27 +370,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1225                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1225                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1225                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           10628                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            10628                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           10628                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    124769000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    124769000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    124769000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000571                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000571                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000571                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11739.649981                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11739.649981                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11739.649981                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1225                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1225                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1225                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1225                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1225                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1225                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        10628                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        10628                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        10628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        10628                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        10628                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        10628                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    124769000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    124769000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    124769000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    124769000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    124769000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    124769000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000571                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000571                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000571                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11739.649981                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11739.649981                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11739.649981                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    159                       # number of replacements
 system.cpu.dcache.tagsinuse               1462.507461                       # Cycle average of tags in use
@@ -380,38 +401,59 @@ system.cpu.dcache.total_refs                 30399158                       # To
 system.cpu.dcache.sampled_refs                   2246                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               13534.798753                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1462.507461                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.357057                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               23906051                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               6493055                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               52                       # number of LoadLockedReq hits
-system.cpu.dcache.demand_hits                30399106                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               30399106                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  938                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                8048                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              1                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                  8986                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 8986                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       28163500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     289889000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        38000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       318052500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      318052500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           23906989                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           53                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            30408092                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           30408092                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000039                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.001238                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.018868                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000296                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000296                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 30025.053305                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 36020.004970                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        38000                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35394.224349                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35394.224349                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1462.507461                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.357057                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.357057                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     23906051                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23906051                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6493055                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6493055                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           52                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           52                       # number of LoadLockedReq hits
+system.cpu.dcache.demand_hits::cpu.data      30399106                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         30399106                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     30399106                       # number of overall hits
+system.cpu.dcache.overall_hits::total        30399106                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          938                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           938                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         8048                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         8048                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            1                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            1                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data         8986                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           8986                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         8986                       # number of overall misses
+system.cpu.dcache.overall_misses::total          8986                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     28163500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     28163500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    289889000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    289889000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        38000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        38000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    318052500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    318052500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    318052500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    318052500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     23906989                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23906989                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           53                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           53                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     30408092                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     30408092                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     30408092                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     30408092                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000039                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001238                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.018868                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000296                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000296                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30025.053305                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36020.004970                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38000                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35394.224349                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35394.224349                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs         2500                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 1                       # number of cycles access was blocked
@@ -420,36 +462,46 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs         2500
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      108                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               424                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6317                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               6741                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              6741                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             514                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1731                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses            1                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             2245                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            2245                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     16469500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     61655000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency        35000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     78124500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     78124500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000266                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate     0.018868                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000074                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000074                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32041.828794                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35618.139804                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency        35000                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34799.331849                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34799.331849                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          108                       # number of writebacks
+system.cpu.dcache.writebacks::total               108                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          424                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          424                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6317                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6317                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         6741                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         6741                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         6741                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         6741                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          514                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          514                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1731                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1731                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total            1                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2245                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2245                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2245                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2245                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     16469500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     16469500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     61655000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     61655000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data        35000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total        35000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     78124500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     78124500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     78124500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     78124500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000266                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.018868                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000074                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000074                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32041.828794                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35618.139804                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data        35000                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34799.331849                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34799.331849                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2400.275766                       # Cycle average of tags in use
@@ -457,36 +509,75 @@ system.cpu.l2cache.total_refs                    7666                       # To
 system.cpu.l2cache.sampled_refs                  3556                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.155793                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2382.642182                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            17.633584                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.072712                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000538                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  7655                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 108                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  25                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   7680                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  7680                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3488                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1706                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 5194                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                5194                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     119792500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     59244000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      179036500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     179036500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             11143                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             108                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1731                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              12874                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             12874                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.313022                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.985557                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.403449                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.403449                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34344.180046                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34726.846424                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34469.869080                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34469.869080                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks    17.633584                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2000.487710                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    382.154472                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000538                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.061050                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.011662                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.073251                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         7599                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           56                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           7655                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          108                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          108                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           25                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           25                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         7599                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           81                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            7680                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         7599                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           81                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           7680                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3029                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          459                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3488                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1706                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1706                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3029                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2165                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5194                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3029                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2165                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5194                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    103998000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     15794500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    119792500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     59244000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     59244000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    103998000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     75038500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    179036500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    103998000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     75038500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    179036500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        10628                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          515                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        11143                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          108                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          108                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1731                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1731                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        10628                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2246                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        12874                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        10628                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2246                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        12874                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.285002                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.891262                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985557                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.285002                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.963936                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.285002                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.963936                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34334.103665                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34410.675381                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34726.846424                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34334.103665                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34659.815242                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34334.103665                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34659.815242                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -495,30 +586,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3488                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1706                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            5194                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           5194                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    108490000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     53828000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    162318000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    162318000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.313022                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985557                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.403449                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.403449                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31103.784404                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31552.168816                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31251.058914                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31251.058914                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3029                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          459                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3488                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1706                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1706                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3029                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2165                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5194                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3029                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2165                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5194                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     94144500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     14345500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    108490000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     53828000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     53828000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     94144500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     68173500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    162318000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     94144500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     68173500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    162318000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.285002                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.891262                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985557                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.285002                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963936                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.285002                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963936                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31081.049851                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31253.812636                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31552.168816                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31081.049851                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31488.914550                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31081.049851                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31488.914550                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index c3b5c01048678e96c3d98f4405d543bdb33d8f56..452e0175b954ca8b6427b9a679956df8ff564117 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic
 egid=100
 env=
 errout=cerr
index 887ca3f4e4703452d0189debc85bd1e713cee047..b6a6db44413ffaefd4b299d5d766e4322fded14a 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 06:10:21
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:46:35
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-atomic/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index af93195e124733e7ac182d641c7306c872debe4d..defa21ce1bf698924f863bde88d61d47b11afcd2 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.045952                       # Nu
 sim_ticks                                 45951567500                       # Number of ticks simulated
 final_tick                                45951567500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                4191883                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2095941744                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 202544                       # Number of bytes of host memory used
-host_seconds                                    21.92                       # Real time elapsed on the host
+host_inst_rate                                5286635                       # Simulator instruction rate (inst/s)
+host_op_rate                                  5286630                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2643314521                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 204308                       # Number of bytes of host memory used
+host_seconds                                    17.38                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
+sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   475949877                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              367612356                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 30920974                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                  389                       # Nu
 system.cpu.numCycles                         91903136                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91903056                       # Number of instructions executed
+system.cpu.committedInsts                    91903056                       # Number of instructions committed
+system.cpu.committedOps                      91903056                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
 system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
index 2fe44f969583e2656e6245f7ef6fd12dbab2bdb4..16b0989b3d264554839b0bd0b88eeeb5637a23a7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
+cwd=build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
 egid=100
 env=
 errout=cerr
index 84097b1db3bcbed91ef717881c4013aa5e679230..1373e7148e9a8dd56b6fe30af462959d8ed0baec 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 06:10:54
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:47:03
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink  build/ALPHA_SE/tests/opt/long/70.twolf/alpha/tru64/simple-timing/smred.sv2
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/long/se/70.twolf/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index ba87aad33450ed7f494f589aa8aea2c1825c8d6c..244f3ca51e90084a329c669fc605fb8d91278f1e 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.118740                       # Nu
 sim_ticks                                118740049000                       # Number of ticks simulated
 final_tick                               118740049000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2095418                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2707308980                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211256                       # Number of bytes of host memory used
-host_seconds                                    43.86                       # Real time elapsed on the host
+host_inst_rate                                2598987                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2598985                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3357924345                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 213168                       # Number of bytes of host memory used
+host_seconds                                    35.36                       # Real time elapsed on the host
 sim_insts                                    91903056                       # Number of instructions simulated
+sim_ops                                      91903056                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      304960                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 167744                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls                  389                       # Nu
 system.cpu.numCycles                        237480098                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         91903056                       # Number of instructions executed
+system.cpu.committedInsts                    91903056                       # Number of instructions committed
+system.cpu.committedOps                      91903056                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              79581109                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                6862064                       # Number of float alu accesses
 system.cpu.num_func_calls                     2059216                       # number of times a function call or return occured
@@ -78,26 +81,39 @@ system.cpu.icache.total_refs                 91894580                       # To
 system.cpu.icache.sampled_refs                   8510                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               10798.423032                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1418.037996                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.692401                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               91894580                       # number of ReadReq hits
-system.cpu.icache.demand_hits                91894580                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               91894580                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 8510                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  8510                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 8510                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      229222000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       229222000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      229222000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           91903090                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            91903090                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           91903090                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000093                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000093                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000093                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 26935.605170                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 26935.605170                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 26935.605170                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1418.037996                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.692401                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.692401                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     91894580                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        91894580                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      91894580                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         91894580                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     91894580                       # number of overall hits
+system.cpu.icache.overall_hits::total        91894580                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         8510                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          8510                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         8510                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           8510                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         8510                       # number of overall misses
+system.cpu.icache.overall_misses::total          8510                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    229222000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    229222000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    229222000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    229222000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    229222000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    229222000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     91903090                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     91903090                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     91903090                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     91903090                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     91903090                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     91903090                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000093                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000093                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000093                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26935.605170                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26935.605170                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26935.605170                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            8510                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             8510                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            8510                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    203692000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    203692000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    203692000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000093                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000093                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000093                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23935.605170                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23935.605170                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         8510                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         8510                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         8510                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         8510                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         8510                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         8510                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    203692000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    203692000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    203692000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    203692000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    203692000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    203692000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000093                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23935.605170                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23935.605170                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23935.605170                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                    157                       # number of replacements
 system.cpu.dcache.tagsinuse               1442.028823                       # Cycle average of tags in use
@@ -133,32 +147,49 @@ system.cpu.dcache.total_refs                 26495078                       # To
 system.cpu.dcache.sampled_refs                   2223                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               11918.613585                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1442.028823                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.352058                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               19995723                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits               6499355                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                26495078                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               26495078                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  475                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                1748                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  2223                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 2223                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       24374000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      96796000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       121170000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      121170000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           19996198                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses           6501103                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            26497301                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           26497301                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000024                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000269                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000084                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000084                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 51313.684211                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55375.286041                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54507.422402                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54507.422402                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1442.028823                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.352058                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.352058                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     19995723                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        19995723                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      6499355                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total        6499355                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      26495078                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         26495078                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     26495078                       # number of overall hits
+system.cpu.dcache.overall_hits::total        26495078                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          475                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           475                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1748                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2223                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2223                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2223                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2223                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24374000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24374000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     96796000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     96796000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    121170000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    121170000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    121170000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    121170000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     19996198                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total      6501103                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     26497301                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     26497301                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000024                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000269                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000084                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000084                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51313.684211                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55375.286041                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54507.422402                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54507.422402                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -167,30 +198,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                      107                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             475                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1748                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             2223                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            2223                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     22949000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     91552000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    114501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    114501000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000024                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000269                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000084                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000084                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 48313.684211                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52375.286041                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51507.422402                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks          107                       # number of writebacks
+system.cpu.dcache.writebacks::total               107                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          475                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          475                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1748                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1748                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2223                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2223                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2223                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2223                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     22949000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     22949000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     91552000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     91552000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    114501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    114501000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    114501000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    114501000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000024                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000269                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000084                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 48313.684211                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52375.286041                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51507.422402                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51507.422402                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2074.048594                       # Cycle average of tags in use
@@ -198,36 +231,75 @@ system.cpu.l2cache.total_refs                    5951                       # To
 system.cpu.l2cache.sampled_refs                  3109                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  1.914120                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2056.253411                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1            17.795183                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.062752                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000543                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  5942                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                 107                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                  26                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   5968                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  5968                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3043                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1722                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 4765                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                4765                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     158236000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     89544000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      247780000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     247780000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              8985                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses             107                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1748                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              10733                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             10733                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.338676                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.985126                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.443958                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.443958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks    17.795183                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1704.999565                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    351.253845                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000543                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.052032                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.010719                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.063295                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         5889                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           53                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           5942                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks          107                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total          107                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data           26                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total           26                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         5889                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           79                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            5968                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         5889                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           79                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           5968                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2621                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          422                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3043                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1722                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1722                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2621                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         2144                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          4765                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2621                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         2144                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         4765                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    136292000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     21944000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    158236000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     89544000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     89544000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    136292000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data    111488000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    247780000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    136292000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data    111488000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    247780000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         8510                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          475                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         8985                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total          107                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1748                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         8510                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         2223                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        10733                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         8510                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         2223                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        10733                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.307991                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.888421                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.985126                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.307991                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.964462                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.307991                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.964462                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -236,30 +308,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3043                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1722                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            4765                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           4765                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    121720000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     68880000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    190600000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    190600000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.338676                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.985126                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.443958                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.443958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2621                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          422                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3043                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1722                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2621                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         2144                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         4765                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2621                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         2144                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         4765                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    104840000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     16880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    121720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     68880000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     68880000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    104840000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     85760000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    190600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    104840000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     85760000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    190600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.888421                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.985126                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.307991                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.964462                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index ce56be1efbfe4132a463a9a917fa7a190571e79e..eef0e971dfae69086cbf4a7fe64828c90cbd9c1c 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -529,12 +508,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
index 442ecd78f54b9bbc4187dd32a38a87c89405cdcb..d10088405a687ed1be0a295dc4bfa3e5e4487f7c 100755 (executable)
@@ -1,14 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 00:18:20
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
-Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
-Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:37:09
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 83e315e2a47fd91d79bc95c71685768edb8d74da..98dddaff096111475146cdb04f2f4a4b446c6169 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.105851                       # Nu
 sim_ticks                                105850842000                       # Number of ticks simulated
 final_tick                               105850842000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46914                       # Simulator instruction rate (inst/s)
-host_tick_rate                               26320721                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 259812                       # Number of bytes of host memory used
-host_seconds                                  4021.58                       # Real time elapsed on the host
-sim_insts                                   188667627                       # Number of instructions simulated
+host_inst_rate                                 122767                       # Simulator instruction rate (inst/s)
+host_op_rate                                   134419                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               75414821                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 227032                       # Number of bytes of host memory used
+host_seconds                                  1403.58                       # Real time elapsed on the host
+sim_insts                                   172314144                       # Number of instructions simulated
+sim_ops                                     188667627                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      239936                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 128320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -280,7 +282,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.155893                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.599323                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      188682015                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      172328532                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        188682015                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       146244510                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls         1636018                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           9791900                       # The number of times a branch was mispredicted
@@ -301,7 +304,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    188552607                       # Number of insts commited each cycle
-system.cpu.commit.count                     188682015                       # Number of instructions committed
+system.cpu.commit.committedInsts            172328532                       # Number of instructions committed
+system.cpu.commit.committedOps              188682015                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       42498565                       # Number of memory references committed
 system.cpu.commit.loads                      29851708                       # Number of loads committed
@@ -316,12 +320,13 @@ system.cpu.rob.rob_reads                    519029825                       # Th
 system.cpu.rob.rob_writes                   693007050                       # The number of ROB writes
 system.cpu.timesIdled                            1719                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           58483                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   188667627                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             188667627                       # Number of Instructions Simulated
-system.cpu.cpi                               1.122088                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         1.122088                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.891196                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.891196                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   172314144                       # Number of Instructions Simulated
+system.cpu.committedOps                     188667627                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             172314144                       # Number of Instructions Simulated
+system.cpu.cpi                               1.228580                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.228580                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.813948                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.813948                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads               1111988877                       # number of integer regfile reads
 system.cpu.int_regfile_writes               407368356                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   2928539                       # number of floating regfile reads
@@ -334,26 +339,39 @@ system.cpu.icache.total_refs                 40615441                       # To
 system.cpu.icache.sampled_refs                   3640                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               11158.088187                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1329.301324                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.649073                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               40615441                       # number of ReadReq hits
-system.cpu.icache.demand_hits                40615441                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               40615441                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 4234                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  4234                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 4234                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      101275500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       101275500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      101275500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           40619675                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            40619675                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           40619675                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000104                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000104                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000104                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23919.579594                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23919.579594                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23919.579594                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1329.301324                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.649073                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.649073                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     40615441                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        40615441                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      40615441                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         40615441                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     40615441                       # number of overall hits
+system.cpu.icache.overall_hits::total        40615441                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4234                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4234                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4234                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4234                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4234                       # number of overall misses
+system.cpu.icache.overall_misses::total          4234                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    101275500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    101275500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    101275500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    101275500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    101275500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    101275500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     40619675                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     40619675                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     40619675                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     40619675                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     40619675                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     40619675                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000104                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000104                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000104                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23919.579594                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23919.579594                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23919.579594                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -362,27 +380,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               594                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                594                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               594                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            3640                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             3640                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            3640                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     74572500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     74572500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     74572500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000090                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000090                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000090                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 20486.950549                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 20486.950549                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 20486.950549                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          594                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          594                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          594                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          594                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          594                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          594                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3640                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         3640                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         3640                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         3640                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         3640                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         3640                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     74572500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     74572500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     74572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     74572500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     74572500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     74572500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000090                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000090                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000090                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 20486.950549                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 20486.950549                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20486.950549                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     53                       # number of replacements
 system.cpu.dcache.tagsinuse               1403.723956                       # Cycle average of tags in use
@@ -390,40 +411,63 @@ system.cpu.dcache.total_refs                 48643693                       # To
 system.cpu.dcache.sampled_refs                   1846                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               26350.862947                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1403.723956                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.342706                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               36234545                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              12356727                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            27791                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             24630                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                48591272                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               48591272                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                 1808                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                7560                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                  9368                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 9368                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       59529000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency     237156500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        63500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency       296685500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      296685500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           36236353                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        27793                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         24630                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            48600640                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           48600640                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000050                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000611                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.000072                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.000193                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000193                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 32925.331858                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 31369.907407                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        31750                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 31670.100342                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 31670.100342                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1403.723956                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.342706                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.342706                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     36234545                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        36234545                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12356727                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12356727                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        27791                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        27791                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        24630                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        24630                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      48591272                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         48591272                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     48591272                       # number of overall hits
+system.cpu.dcache.overall_hits::total        48591272                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data         1808                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total          1808                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         7560                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         7560                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data         9368                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           9368                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         9368                       # number of overall misses
+system.cpu.dcache.overall_misses::total          9368                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     59529000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     59529000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data    237156500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total    237156500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        63500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        63500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    296685500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    296685500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    296685500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    296685500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     36236353                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     36236353                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        27793                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        27793                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        24630                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        24630                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     48600640                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     48600640                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     48600640                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     48600640                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000050                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000611                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.000072                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000193                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000193                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 32925.331858                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 31369.907407                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        31750                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 31670.100342                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 31670.100342                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets        20000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -432,33 +476,42 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets        20000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                       18                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits              1053                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits             6469                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits               7522                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits              7522                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             755                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1091                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1846                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1846                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     24116500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     38344000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     62460500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     62460500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000021                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000088                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000038                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000038                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 31942.384106                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35145.737855                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 33835.590466                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 33835.590466                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks           18                       # number of writebacks
+system.cpu.dcache.writebacks::total                18                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data         1053                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total         1053                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data         6469                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total         6469                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data         7522                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total         7522                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data         7522                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total         7522                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          755                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          755                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1091                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1091                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1846                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1846                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1846                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1846                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     24116500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     24116500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     38344000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     38344000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     62460500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     62460500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     62460500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     62460500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000088                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000038                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000038                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31942.384106                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35145.737855                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 33835.590466                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 33835.590466                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              1923.480613                       # Cycle average of tags in use
@@ -466,36 +519,75 @@ system.cpu.l2cache.total_refs                    1714                       # To
 system.cpu.l2cache.sampled_refs                  2676                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.640508                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1919.476269                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             4.004344                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.058578                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000122                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  1714                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                  18                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                   9                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   1723                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  1723                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                2681                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1082                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 3763                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                3763                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      91922000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     37184000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      129106000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     129106000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              4395                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses              18                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1091                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               5486                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              5486                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.610011                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.991751                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.685928                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.685928                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34286.460276                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34365.988909                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34309.327664                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34309.327664                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     4.004344                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1392.392495                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    527.083774                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000122                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.042492                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.016085                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.058700                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         1633                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           81                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           1714                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           18                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           18                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            9                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            9                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1633                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           90                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            1723                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1633                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           90                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1723                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2007                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          674                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2681                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1082                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1082                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2007                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1756                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3763                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2007                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1756                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3763                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     68771500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     23150500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     91922000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     37184000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     37184000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     68771500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     60334500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    129106000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     68771500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     60334500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    129106000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         3640                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          755                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         4395                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           18                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           18                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1091                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         3640                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1846                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         5486                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         3640                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1846                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         5486                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.551374                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.892715                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.991751                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.551374                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.951246                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.551374                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.951246                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34265.819631                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34347.922849                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34365.988909                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34265.819631                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34359.054670                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34265.819631                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34359.054670                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -504,31 +596,51 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits               14                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                14                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits               14                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           2667                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1082                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            3749                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           3749                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     82895000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     33590000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    116485000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    116485000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.606826                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.991751                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.683376                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.683376                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.739783                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31044.362292                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31070.952254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31070.952254                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst            2                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data           12                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total           14                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst            2                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data           12                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total           14                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst            2                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data           12                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total           14                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2005                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          662                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2667                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1082                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2005                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1744                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3749                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2005                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1744                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3749                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     62251500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     20643500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     82895000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     33590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     33590000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     62251500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     54233500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    116485000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     62251500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     54233500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    116485000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.550824                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.876821                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.991751                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.550824                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.944745                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.550824                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.944745                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31048.129676                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31183.534743                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31044.362292                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31048.129676                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31097.190367                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31048.129676                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31097.190367                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 01def30a39c975e33d432b362eeb52c2acfe5ffb..8e458b7936aa3cb56c2c4059a7dbbd9ae8339618 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +95,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index f2a9f066114bc889acce8f8702c67a7ad9c9e703..36b361cbcde3da2d557208685b8ec8efa7a87232 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:50:48
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:37:27
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sav
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-atomic/smred.sv2
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 079a70f111434a22a498dc62c78779ec137b07d9..5d6608220b3a67aa54955603b3edd02c66f5024c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.103107                       # Nu
 sim_ticks                                103106771000                       # Number of ticks simulated
 final_tick                               103106771000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3006793                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1643182108                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213456                       # Number of bytes of host memory used
-host_seconds                                    62.75                       # Real time elapsed on the host
-sim_insts                                   188670900                       # Number of instructions simulated
+host_inst_rate                                3118510                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3414466                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1865971013                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216012                       # Number of bytes of host memory used
+host_seconds                                    55.26                       # Real time elapsed on the host
+sim_insts                                   172317417                       # Number of instructions simulated
+sim_ops                                     188670900                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   869973902                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              759440240                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 45252940                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                  400                       # Nu
 system.cpu.numCycles                        206213543                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        188670900                       # Number of instructions executed
+system.cpu.committedInsts                   172317417                       # Number of instructions committed
+system.cpu.committedOps                     188670900                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
index 3f54c6512eb624f1111ba96fbdeb334c5f7835e4..f90360da8d10a8a7b0bca8744d7f69a94b91787f 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +177,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
+cwd=build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
 egid=100
 env=
 errout=cerr
index b217637427dc71e3d458615756563111262348d5..322e5b2f2983d8445c8653e9a8b00a9de757b02d 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 09:52:01
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 16:38:33
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sav
-Couldn't unlink  build/ARM_SE/tests/opt/long/70.twolf/arm/linux/simple-timing/smred.sv2
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/long/se/70.twolf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index d861ddab18865db8d41f04c6d83675010371c59b..f86e3b0575acc069ad319dc43d258870356f9c6f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.232077                       # Nu
 sim_ticks                                232077154000                       # Number of ticks simulated
 final_tick                               232077154000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1497030                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1846187485                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222460                       # Number of bytes of host memory used
-host_seconds                                   125.71                       # Real time elapsed on the host
-sim_insts                                   188185929                       # Number of instructions simulated
+host_inst_rate                                1867609                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2045232                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2522247357                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 224952                       # Number of bytes of host memory used
+host_seconds                                    92.01                       # Real time elapsed on the host
+sim_insts                                   171842491                       # Number of instructions simulated
+sim_ops                                     188185929                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      220992                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 110656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls                  400                       # Nu
 system.cpu.numCycles                        464154308                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        188185929                       # Number of instructions executed
+system.cpu.committedInsts                   171842491                       # Number of instructions committed
+system.cpu.committedOps                     188185929                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             150106226                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1752310                       # Number of float alu accesses
 system.cpu.num_func_calls                     3504894                       # number of times a function call or return occured
@@ -88,26 +91,39 @@ system.cpu.icache.total_refs                189857010                       # To
 system.cpu.icache.sampled_refs                   3051                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               62227.797443                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1147.981155                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.560538                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              189857010                       # number of ReadReq hits
-system.cpu.icache.demand_hits               189857010                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              189857010                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 3051                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  3051                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 3051                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      115332000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       115332000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      115332000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          189860061                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           189860061                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          189860061                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000016                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000016                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000016                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 37801.376598                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 37801.376598                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 37801.376598                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1147.981155                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.560538                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.560538                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    189857010                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       189857010                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     189857010                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        189857010                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    189857010                       # number of overall hits
+system.cpu.icache.overall_hits::total       189857010                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         3051                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          3051                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         3051                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           3051                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         3051                       # number of overall misses
+system.cpu.icache.overall_misses::total          3051                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    115332000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    115332000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    115332000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    115332000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    115332000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    115332000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    189860061                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    189860061                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    189860061                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    189860061                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    189860061                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    189860061                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000016                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000016                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000016                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 37801.376598                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 37801.376598                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 37801.376598                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            3051                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             3051                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            3051                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    106179000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    106179000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    106179000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000016                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000016                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34801.376598                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34801.376598                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         3051                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         3051                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         3051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         3051                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         3051                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         3051                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    106179000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    106179000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    106179000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    106179000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    106179000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000016                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34801.376598                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     40                       # number of replacements
 system.cpu.dcache.tagsinuse               1363.604315                       # Cycle average of tags in use
@@ -143,36 +157,57 @@ system.cpu.dcache.total_refs                 42007359                       # To
 system.cpu.dcache.sampled_refs                   1789                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               23480.916154                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1363.604315                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.332911                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               29599358                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              12363187                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits            22407                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits             22407                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                41962545                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               41962545                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  689                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                1100                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  1789                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 1789                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       36190000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      61264000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        97454000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       97454000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           29600047                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          12364287                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses        22407                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses         22407                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            41964334                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           41964334                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000023                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000089                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000043                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000043                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 52525.399129                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55694.545455                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54474.007826                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54474.007826                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1363.604315                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.332911                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     29599358                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        29599358                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     12363187                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       12363187                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data        22407                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total        22407                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data      41962545                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41962545                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41962545                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41962545                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          689                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           689                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1100                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1100                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1789                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1789                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1789                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1789                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     36190000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     36190000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     61264000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     61264000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     97454000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     97454000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     97454000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     97454000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     29600047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     29600047                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     41964334                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     41964334                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     41964334                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     41964334                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000023                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000089                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000043                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000043                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52525.399129                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55694.545455                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54474.007826                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54474.007826                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -181,30 +216,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                       16                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             689                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1100                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1789                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1789                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     34123000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     57964000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     92087000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     92087000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000023                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000089                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000043                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000043                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 49525.399129                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52694.545455                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 51474.007826                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks           16                       # number of writebacks
+system.cpu.dcache.writebacks::total                16                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          689                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          689                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1100                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1789                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1789                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1789                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     34123000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     34123000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57964000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     57964000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     92087000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     92087000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     92087000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     92087000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000023                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000089                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000043                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49525.399129                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52694.545455                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51474.007826                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              1675.648030                       # Cycle average of tags in use
@@ -212,36 +249,75 @@ system.cpu.l2cache.total_refs                    1379                       # To
 system.cpu.l2cache.sampled_refs                  2369                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.582102                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          1672.609981                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             3.038048                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.051044                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000093                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  1379                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                  16                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   1387                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  1387                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                2361                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1092                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 3453                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                3453                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     122772000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     56784000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      179556000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     179556000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              3740                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses              16                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1100                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               4840                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              4840                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.631283                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.992727                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.713430                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.713430                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     3.038048                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1169.027734                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    503.582248                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000093                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.035676                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.015368                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.051137                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         1322                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           57                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           1379                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           16                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           16                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1322                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           65                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            1387                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1322                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           65                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1387                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         1729                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          632                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         2361                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1092                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1092                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         1729                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1724                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          3453                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         1729                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1724                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         3453                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     89908000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     32864000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    122772000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56784000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     56784000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     89908000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     89648000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    179556000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     89908000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     89648000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    179556000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         3051                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          689                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         3740                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           16                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1100                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1100                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         3051                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1789                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         4840                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         3051                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1789                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         4840                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.566699                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.917271                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.992727                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.566699                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.963667                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.566699                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.963667                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -250,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           2361                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1092                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            3453                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           3453                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     94440000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     43680000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    138120000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    138120000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.631283                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.992727                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.713430                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.713430                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         1729                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          632                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         2361                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1092                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         1729                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1724                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         3453                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         1729                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1724                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         3453                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     69160000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     25280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     94440000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     43680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     43680000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     69160000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     68960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    138120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     69160000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     68960000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    138120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.917271                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.992727                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.566699                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.963667                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 5551fc7185d47cc48749520729be16ef8b1618c7..bf42eae33f6914348e9da2131f0f1a93d2d2ee65 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -64,7 +77,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
+cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
 egid=100
 env=
 errout=cerr
index 5a1dc45d3acb53878414575da3d7911748a2065b..288eec929ab03d7234387a509f1525189003fe96 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:25:10
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:01:49
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic
-Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-atomic/smred.sv2
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index fabf573ddb32715bb9d39f2c631e2a3de3781ee5..acb9c3a660d3256082d22665ce47c3f7209a69d0 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.096723                       # Nu
 sim_ticks                                 96722951500                       # Number of ticks simulated
 final_tick                                96722951500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3381365                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1690691780                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 210080                       # Number of bytes of host memory used
-host_seconds                                    57.21                       # Real time elapsed on the host
-sim_insts                                   193444769                       # Number of instructions simulated
+host_inst_rate                                4190258                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4190262                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2095142285                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207744                       # Number of bytes of host memory used
+host_seconds                                    46.17                       # Real time elapsed on the host
+sim_insts                                   193444531                       # Number of instructions simulated
+sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                   997245606                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read              773782192                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 72065412                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  401                       # Nu
 system.cpu.numCycles                        193445904                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        193444769                       # Number of instructions executed
+system.cpu.committedInsts                   193444531                       # Number of instructions committed
+system.cpu.committedOps                     193444769                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
 system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
index 2d0b36d347bf1656056f4c7915a1df6797f05315..4355111bc114ba6b359e0fd2bd794fd88d7a6f4b 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -167,7 +159,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
+cwd=build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
 egid=100
 env=
 errout=cerr
index e7f89f9a000e65d816b62126ab1435149a180d70..cb4fa44405fb23e89dc0e263206e84916401cf01 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 06:26:18
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 14:02:21
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing
-Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sav
-Couldn't unlink  build/SPARC_SE/tests/opt/long/70.twolf/sparc/linux/simple-timing/smred.sv2
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/long/se/70.twolf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 16bfeed42c5cb153215461f31edea0e84d57f879..fba3d7989fad91b16ae168181f1a219851d97fb3 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.270577                       # Nu
 sim_ticks                                270576960000                       # Number of ticks simulated
 final_tick                               270576960000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1675606                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2343719954                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218792                       # Number of bytes of host memory used
-host_seconds                                   115.45                       # Real time elapsed on the host
-sim_insts                                   193444769                       # Number of instructions simulated
+host_inst_rate                                2083715                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2083717                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2914556895                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216616                       # Number of bytes of host memory used
+host_seconds                                    92.84                       # Real time elapsed on the host
+sim_insts                                   193444531                       # Number of instructions simulated
+sim_ops                                     193444769                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      331072                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 230208                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls                  401                       # Nu
 system.cpu.numCycles                        541153920                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        193444769                       # Number of instructions executed
+system.cpu.committedInsts                   193444531                       # Number of instructions committed
+system.cpu.committedOps                     193444769                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             167974818                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                1970372                       # Number of float alu accesses
 system.cpu.num_func_calls                     1957920                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu.icache.total_refs                193433261                       # To
 system.cpu.icache.sampled_refs                  12288                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               15741.639079                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1591.571713                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.777135                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              193433261                       # number of ReadReq hits
-system.cpu.icache.demand_hits               193433261                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              193433261                       # number of overall hits
-system.cpu.icache.ReadReq_misses                12288                       # number of ReadReq misses
-system.cpu.icache.demand_misses                 12288                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                12288                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      323106000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       323106000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      323106000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          193445549                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           193445549                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          193445549                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000064                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000064                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000064                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 26294.433594                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 26294.433594                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 26294.433594                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1591.571713                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.777135                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.777135                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    193433261                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       193433261                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     193433261                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        193433261                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    193433261                       # number of overall hits
+system.cpu.icache.overall_hits::total       193433261                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst        12288                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total         12288                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst        12288                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total          12288                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst        12288                       # number of overall misses
+system.cpu.icache.overall_misses::total         12288                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    323106000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    323106000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    323106000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    323106000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    323106000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    323106000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    193445549                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    193445549                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    193445549                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    193445549                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    193445549                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    193445549                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000064                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000064                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000064                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 26294.433594                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 26294.433594                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 26294.433594                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses           12288                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses            12288                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses           12288                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    286242000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    286242000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    286242000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000064                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000064                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000064                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 23294.433594                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst        12288                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total        12288                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst        12288                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total        12288                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst        12288                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total        12288                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    286242000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    286242000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    286242000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    286242000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    286242000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    286242000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000064                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 23294.433594                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 23294.433594                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 23294.433594                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      2                       # number of replacements
 system.cpu.dcache.tagsinuse               1237.197455                       # Cycle average of tags in use
@@ -101,38 +115,59 @@ system.cpu.dcache.total_refs                 76732338                       # To
 system.cpu.dcache.sampled_refs                   1576                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               48688.031726                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1237.197455                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.302050                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               57734571                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              18975362                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                  22405                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                76709933                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               76709933                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  498                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                1077                       # number of WriteReq misses
-system.cpu.dcache.SwapReq_misses                    1                       # number of SwapReq misses
-system.cpu.dcache.demand_misses                  1575                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 1575                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       27888000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      60312000                       # number of WriteReq miss cycles
-system.cpu.dcache.SwapReq_miss_latency          56000                       # number of SwapReq miss cycles
-system.cpu.dcache.demand_miss_latency        88200000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       88200000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           57735069                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          18976439                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses              22406                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            76711508                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           76711508                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000009                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000057                       # miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_miss_rate          0.000045                       # miss rate for SwapReq accesses
-system.cpu.dcache.demand_miss_rate           0.000021                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000021                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.SwapReq_avg_miss_latency        56000                       # average SwapReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1237.197455                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.302050                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.302050                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     57734571                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        57734571                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18975362                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18975362                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data        22405                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total           22405                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data      76709933                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         76709933                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     76709933                       # number of overall hits
+system.cpu.dcache.overall_hits::total        76709933                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           498                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1077                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1077                       # number of WriteReq misses
+system.cpu.dcache.SwapReq_misses::cpu.data            1                       # number of SwapReq misses
+system.cpu.dcache.SwapReq_misses::total             1                       # number of SwapReq misses
+system.cpu.dcache.demand_misses::cpu.data         1575                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1575                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1575                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1575                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     27888000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     27888000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     60312000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     60312000                       # number of WriteReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::cpu.data        56000                       # number of SwapReq miss cycles
+system.cpu.dcache.SwapReq_miss_latency::total        56000                       # number of SwapReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     88200000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     88200000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     88200000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     88200000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     57735069                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     57735069                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18976439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18976439                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data        22406                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total        22406                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     76711508                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     76711508                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     76711508                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     76711508                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000009                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000057                       # miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_miss_rate::cpu.data     0.000045                       # miss rate for SwapReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000021                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000021                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.SwapReq_avg_miss_latency::cpu.data        56000                       # average SwapReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -141,34 +176,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        2                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             498                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1077                       # number of WriteReq MSHR misses
-system.cpu.dcache.SwapReq_mshr_misses               1                       # number of SwapReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1575                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1575                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     26394000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     57081000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.SwapReq_mshr_miss_latency        53000                       # number of SwapReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     83475000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     83475000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000009                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000057                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.SwapReq_mshr_miss_rate     0.000045                       # mshr miss rate for SwapReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000021                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000021                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.SwapReq_avg_mshr_miss_latency        53000                       # average SwapReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks            2                       # number of writebacks
+system.cpu.dcache.writebacks::total                 2                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          498                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1077                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1077                       # number of WriteReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::cpu.data            1                       # number of SwapReq MSHR misses
+system.cpu.dcache.SwapReq_mshr_misses::total            1                       # number of SwapReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1575                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1575                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1575                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1575                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     26394000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     26394000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     57081000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     57081000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::cpu.data        53000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.SwapReq_mshr_miss_latency::total        53000                       # number of SwapReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     83475000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     83475000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     83475000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     83475000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000009                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000057                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.SwapReq_mshr_miss_rate::cpu.data     0.000045                       # mshr miss rate for SwapReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000021                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.SwapReq_avg_mshr_miss_latency::cpu.data        53000                       # average SwapReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2678.327135                       # Cycle average of tags in use
@@ -176,35 +215,70 @@ system.cpu.l2cache.total_refs                    8691                       # To
 system.cpu.l2cache.sampled_refs                  4097                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  2.121308                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2678.326682                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             0.000454                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.081736                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  8691                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                   2                       # number of Writeback hits
-system.cpu.l2cache.demand_hits                   8691                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  8691                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                4095                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1078                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 5173                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                5173                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     212940000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     56056000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      268996000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     268996000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses             12786                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses               2                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1078                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses              13864                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses             13864                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.320272                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.373125                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.373125                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     0.000454                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2275.271466                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    403.055215                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000000                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.069436                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.012300                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.081736                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         8691                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           8691                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks            2                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total            2                       # number of Writeback hits
+system.cpu.l2cache.demand_hits::cpu.inst         8691                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            8691                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         8691                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           8691                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3597                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          498                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         4095                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1078                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1078                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3597                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1576                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5173                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3597                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1576                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5173                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    187044000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     25896000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    212940000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     56056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     56056000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    187044000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     81952000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    268996000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    187044000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     81952000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    268996000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst        12288                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          498                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total        12786                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks            2                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total            2                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1078                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1078                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst        12288                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1576                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total        13864                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst        12288                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1576                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total        13864                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.292725                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.292725                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.292725                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -213,30 +287,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           4095                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1078                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            5173                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           5173                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    163800000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     43120000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    206920000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    206920000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.320272                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.373125                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.373125                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3597                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          498                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         4095                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1078                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1078                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3597                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1576                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5173                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3597                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1576                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5173                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    143880000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     19920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    163800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     43120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     43120000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    143880000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     63040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    206920000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    143880000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     63040000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    206920000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.292725                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 9f72e3b54d91e2f8dcdd7cfe499b7e4e29b5f782..82a282d9673891b812485fb0fb53947cbca740e5 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -442,20 +435,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -494,20 +480,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -531,12 +510,12 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
+cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
 egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
index 0b6a80ec206995ed69c45ec509b013956b147f52..99b3e7f21b7b0945cd14bd062caff7a978fb4065 100755 (executable)
@@ -1,14 +1,10 @@
-Redirecting stdout to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb  9 2012 12:45:55
-gem5 started Feb  9 2012 12:46:40
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
-Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
-Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:02:46
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 2a68affc2a18ca5bc68f608e080b0365e23f1c77..0aeabdea406eaa2bd5bcf737ea496e50c68b10e3 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.096266                       # Nu
 sim_ticks                                 96266258000                       # Number of ticks simulated
 final_tick                                96266258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  60515                       # Simulator instruction rate (inst/s)
-host_tick_rate                               26316743                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 262352                       # Number of bytes of host memory used
-host_seconds                                  3657.99                       # Real time elapsed on the host
-sim_insts                                   221363017                       # Number of instructions simulated
+host_inst_rate                                  89516                       # Simulator instruction rate (inst/s)
+host_op_rate                                   150037                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               65247901                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 229524                       # Number of bytes of host memory used
+host_seconds                                  1475.39                       # Real time elapsed on the host
+sim_insts                                   132071227                       # Number of instructions simulated
+sim_ops                                     221363017                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      339712                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 214912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       1.457634                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.601730                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts      221363017                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts      132071227                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps        221363017                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts       174222633                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls            1246                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts           2892920                       # The number of times a branch was mispredicted
@@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total    168869292                       # Number of insts commited each cycle
-system.cpu.commit.count                     221363017                       # Number of instructions committed
+system.cpu.commit.committedInsts            132071227                       # Number of instructions committed
+system.cpu.commit.committedOps              221363017                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                       77165306                       # Number of memory references committed
 system.cpu.commit.loads                      56649590                       # Number of loads committed
@@ -271,12 +275,13 @@ system.cpu.rob.rob_reads                    560089335                       # Th
 system.cpu.rob.rob_writes                   814800236                       # The number of ROB writes
 system.cpu.timesIdled                            1747                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           80351                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                   221363017                       # Number of Instructions Simulated
-system.cpu.committedInsts_total             221363017                       # Number of Instructions Simulated
-system.cpu.cpi                               0.869759                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         0.869759                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               1.149744                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         1.149744                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                   132071227                       # Number of Instructions Simulated
+system.cpu.committedOps                     221363017                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total             132071227                       # Number of Instructions Simulated
+system.cpu.cpi                               1.457793                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         1.457793                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.685968                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.685968                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                530367480                       # number of integer regfile reads
 system.cpu.int_regfile_writes               288604591                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                   3608788                       # number of floating regfile reads
@@ -289,26 +294,39 @@ system.cpu.icache.total_refs                 28751182                       # To
 system.cpu.icache.sampled_refs                   6167                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                4662.101832                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1597.649860                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.780102                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits               28751182                       # number of ReadReq hits
-system.cpu.icache.demand_hits                28751182                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits               28751182                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 7479                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  7479                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 7479                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      173725000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       173725000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      173725000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses           28758661                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses            28758661                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses           28758661                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000260                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000260                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000260                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 23228.372777                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 23228.372777                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 23228.372777                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1597.649860                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.780102                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.780102                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     28751182                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total        28751182                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst      28751182                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total         28751182                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst     28751182                       # number of overall hits
+system.cpu.icache.overall_hits::total        28751182                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         7479                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          7479                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         7479                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           7479                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         7479                       # number of overall misses
+system.cpu.icache.overall_misses::total          7479                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    173725000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    173725000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    173725000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    173725000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    173725000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    173725000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     28758661                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total     28758661                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst     28758661                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total     28758661                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     28758661                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total     28758661                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000260                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000260                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000260                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 23228.372777                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 23228.372777                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 23228.372777                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -317,27 +335,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits              1119                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits               1119                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits              1119                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            6360                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             6360                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            6360                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    125233500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    125233500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    125233500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000221                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000221                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000221                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 19690.801887                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 19690.801887                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 19690.801887                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst         1119                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total         1119                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst         1119                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total         1119                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst         1119                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total         1119                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         6360                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         6360                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         6360                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         6360                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         6360                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         6360                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    125233500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    125233500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    125233500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    125233500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    125233500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    125233500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000221                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000221                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000221                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19690.801887                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19690.801887                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19690.801887                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     56                       # number of replacements
 system.cpu.dcache.tagsinuse               1415.486536                       # Cycle average of tags in use
@@ -345,32 +366,49 @@ system.cpu.dcache.total_refs                 72938173                       # To
 system.cpu.dcache.sampled_refs                   1987                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               36707.686462                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1415.486536                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.345578                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               52423955                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              20513973                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                72937928                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               72937928                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  771                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                1757                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  2528                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 2528                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       24605500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      66582500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        91188000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       91188000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           52424726                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            72940456                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           72940456                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000015                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000086                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000035                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000035                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 31913.748379                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 37895.560615                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 36071.202532                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 36071.202532                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1415.486536                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.345578                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.345578                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     52423955                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        52423955                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20513973                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20513973                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      72937928                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         72937928                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     72937928                       # number of overall hits
+system.cpu.dcache.overall_hits::total        72937928                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          771                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           771                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1757                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1757                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         2528                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           2528                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         2528                       # number of overall misses
+system.cpu.dcache.overall_misses::total          2528                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     24605500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     24605500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     66582500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     66582500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     91188000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     91188000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     91188000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     91188000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     52424726                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     52424726                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     72940456                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     72940456                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     72940456                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     72940456                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000015                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000086                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000035                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000035                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31913.748379                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37895.560615                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36071.202532                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36071.202532                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -379,32 +417,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                       13                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits               344                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits                2                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                346                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               346                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             427                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1755                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             2182                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            2182                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     14039500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     61244500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency     75284000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency     75284000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000008                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000086                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000030                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000030                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 32879.391101                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 34897.150997                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 34502.291476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 34502.291476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks           13                       # number of writebacks
+system.cpu.dcache.writebacks::total                13                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          344                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total          344                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data            2                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total            2                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          346                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          346                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          346                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          346                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          427                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          427                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1755                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1755                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         2182                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         2182                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         2182                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         2182                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     14039500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     14039500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     61244500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     61244500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     75284000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total     75284000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     75284000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total     75284000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000008                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000086                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000030                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000030                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 32879.391101                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 34897.150997                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 34502.291476                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 34502.291476                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2496.824684                       # Cycle average of tags in use
@@ -412,39 +458,80 @@ system.cpu.l2cache.total_refs                    2842                       # To
 system.cpu.l2cache.sampled_refs                  3755                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.756858                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2494.880189                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             1.944495                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.076138                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000059                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  2840                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                  13                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                   8                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   2848                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  2848                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3753                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses              193                       # number of UpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses              1555                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 5308                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                5308                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     128533500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     53066500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      181600000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     181600000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              6593                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses              13                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses            193                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1563                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               8156                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              8156                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.569240                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate             1                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.994882                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.650809                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.650809                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34248.201439                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34126.366559                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34212.509420                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34212.509420                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     1.944495                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   2209.976363                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    284.903826                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000059                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.067443                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.008695                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.076197                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         2809                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           31                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           2840                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks           13                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total           13                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            8                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            8                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         2809                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           39                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            2848                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         2809                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           39                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           2848                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         3358                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          395                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3753                       # number of ReadReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data          193                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::total          193                       # number of UpgradeReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1555                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1555                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         3358                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1950                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          5308                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         3358                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1950                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         5308                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    115037500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     13496000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    128533500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     53066500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     53066500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    115037500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     66562500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    181600000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    115037500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     66562500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    181600000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         6167                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          426                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         6593                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total           13                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::cpu.data          193                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.UpgradeReq_accesses::total          193                       # number of UpgradeReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1563                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1563                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         6167                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1989                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         8156                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         6167                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1989                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         8156                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.544511                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.927230                       # miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data            1                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.994882                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.544511                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980392                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.544511                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980392                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34257.742704                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34167.088608                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34126.366559                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34257.742704                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34134.615385                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34257.742704                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34134.615385                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -453,34 +540,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3753                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses          193                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1555                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            5308                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           5308                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    116413500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency      5983000                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     48232500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    164646000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    164646000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.569240                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate            1                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.994882                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.650809                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.650809                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31018.784972                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency        31000                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31017.684887                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31018.462698                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31018.462698                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         3358                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          395                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3753                       # number of ReadReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data          193                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::total          193                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1555                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1555                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         3358                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1950                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         5308                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         3358                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1950                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         5308                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    104175500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12238000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    116413500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data      5983000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total      5983000                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     48232500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     48232500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    104175500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     60470500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    164646000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    104175500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     60470500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    164646000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.544511                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.927230                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.994882                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.544511                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980392                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.544511                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980392                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31023.079214                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30982.278481                       # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data        31000                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31017.684887                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31023.079214                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31010.512821                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31023.079214                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31010.512821                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 4d9868de9b2f4543fc05a85638e86cc22abcd2ee..1355f971ac1467335c57457544ba46cf844afa8d 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -64,7 +97,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
+cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic
 egid=100
 env=
 errout=cerr
@@ -88,7 +121,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index 3217ab20001b8dc27497b05d745a80c83d2c75c7..d61c2b9aa891f94b23223a58b41bfe71c99d5f1e 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 08:24:02
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:27:33
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sav
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-atomic/smred.sv2
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 39967f660d14e050aa697a74a0ce6c22ec8801ba..0e7ef2e195a1713e73eae56322aaa9bc45a25c32 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.131393                       # Nu
 sim_ticks                                131393100000                       # Number of ticks simulated
 final_tick                               131393100000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1953897                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1159762651                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211876                       # Number of bytes of host memory used
-host_seconds                                   113.29                       # Real time elapsed on the host
-sim_insts                                   221363018                       # Number of instructions simulated
+host_inst_rate                                1741959                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2919677                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1733014386                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217356                       # Number of bytes of host memory used
+host_seconds                                    75.82                       # Real time elapsed on the host
+sim_insts                                   132071228                       # Number of instructions simulated
+sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                  1698379042                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read             1387955288                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 99822189                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                  400                       # Nu
 system.cpu.numCycles                        262786201                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        221363018                       # Number of instructions executed
+system.cpu.committedInsts                   132071228                       # Number of instructions committed
+system.cpu.committedOps                     221363018                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index d7a51039869b7c1e2974423632c5147e8492b71c..62a1aa7b09b3053c37501e6a1a0615b0420ff715 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +104,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +118,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +149,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +171,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -167,7 +179,7 @@ type=ExeTracer
 [system.cpu.workload]
 type=LiveProcess
 cmd=twolf smred
-cwd=build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
+cwd=build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
 egid=100
 env=
 errout=cerr
@@ -191,7 +203,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index a3170a4074c4284b814f7913d6194b927a1cbed6..fff65e67f31cd7a4ac02319de2a4d3b9af6a6ea4 100755 (executable)
@@ -1,12 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 08:26:06
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 15:28:59
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sav
-Couldn't unlink  build/X86_SE/tests/opt/long/70.twolf/x86/linux/simple-timing/smred.sv2
+command line: build/X86/gem5.fast -d build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/long/se/70.twolf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
index 1c9d2c1e6cb3c78278fda3b4ed6d401438bf8cb6..6e37255884c2be4ca0d7c21223edcb89de4b9e9a 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.250961                       # Nu
 sim_ticks                                250960631000                       # Number of ticks simulated
 final_tick                               250960631000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1263573                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1432520595                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220856                       # Number of bytes of host memory used
-host_seconds                                   175.19                       # Real time elapsed on the host
-sim_insts                                   221363018                       # Number of instructions simulated
+host_inst_rate                                1043901                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1749670                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1983612036                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 226268                       # Number of bytes of host memory used
+host_seconds                                   126.52                       # Real time elapsed on the host
+sim_insts                                   132071228                       # Number of instructions simulated
+sim_ops                                     221363018                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                      303040                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 181760                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls                  400                       # Nu
 system.cpu.numCycles                        501921262                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        221363018                       # Number of instructions executed
+system.cpu.committedInsts                   132071228                       # Number of instructions committed
+system.cpu.committedOps                     221363018                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             220339607                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                2162459                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu.icache.total_refs                173489718                       # To
 system.cpu.icache.sampled_refs                   4694                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs               36959.888794                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0           1455.289108                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.710590                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits              173489718                       # number of ReadReq hits
-system.cpu.icache.demand_hits               173489718                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits              173489718                       # number of overall hits
-system.cpu.icache.ReadReq_misses                 4694                       # number of ReadReq misses
-system.cpu.icache.demand_misses                  4694                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                 4694                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency      185041500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency       185041500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency      185041500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses          173494412                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses           173494412                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses          173494412                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.000027                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.000027                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.000027                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 39420.856412                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 39420.856412                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 39420.856412                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst    1455.289108                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.710590                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.710590                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    173489718                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total       173489718                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst     173489718                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total        173489718                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst    173489718                       # number of overall hits
+system.cpu.icache.overall_hits::total       173489718                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst         4694                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total          4694                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst         4694                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total           4694                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst         4694                       # number of overall misses
+system.cpu.icache.overall_misses::total          4694                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst    185041500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total    185041500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst    185041500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total    185041500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst    185041500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total    185041500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    173494412                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total    173494412                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst    173494412                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total    173494412                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    173494412                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total    173494412                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000027                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.000027                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.000027                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 39420.856412                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 39420.856412                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 39420.856412                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses            4694                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses             4694                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses            4694                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency    170928000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency    170928000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency    170928000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000027                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.000027                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.000027                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 36414.145718                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 36414.145718                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst         4694                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total         4694                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst         4694                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total         4694                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst         4694                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total         4694                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst    170928000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total    170928000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst    170928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total    170928000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst    170928000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total    170928000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000027                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36414.145718                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36414.145718                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36414.145718                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                     41                       # number of replacements
 system.cpu.dcache.tagsinuse               1363.451495                       # Cycle average of tags in use
@@ -101,32 +115,49 @@ system.cpu.dcache.total_refs                 77195833                       # To
 system.cpu.dcache.sampled_refs                   1905                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs               40522.746982                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0           1363.451495                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.332874                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits               56681681                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits              20514152                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                77195833                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits               77195833                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  327                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                1578                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  1905                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 1905                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency       18020000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      88242000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency       106262000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency      106262000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses           56682008                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses          20515730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses            77197738                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses           77197738                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.000006                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.000077                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.000025                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.000025                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 55107.033639                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55920.152091                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 55780.577428                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 55780.577428                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data    1363.451495                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.332874                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.332874                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     56681681                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        56681681                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     20514152                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       20514152                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data      77195833                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         77195833                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     77195833                       # number of overall hits
+system.cpu.dcache.overall_hits::total        77195833                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          327                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           327                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data         1578                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total         1578                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1905                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1905                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1905                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1905                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     18020000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total     18020000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     88242000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     88242000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data    106262000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total    106262000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data    106262000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total    106262000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     56682008                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     56682008                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     20515730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     20515730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data     77197738                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     77197738                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     77197738                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     77197738                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.000006                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.000077                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.000025                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.000025                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55107.033639                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55920.152091                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55780.577428                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55780.577428                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -135,30 +166,32 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        7                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             327                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses           1578                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses             1905                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses            1905                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency     17038500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency     83508000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency    100546500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency    100546500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.000006                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000077                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.000025                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.000025                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52105.504587                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 52920.152091                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52780.314961                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks            7                       # number of writebacks
+system.cpu.dcache.writebacks::total                 7                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          327                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          327                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data         1578                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total         1578                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data         1905                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total         1905                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data         1905                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total         1905                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data     17038500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total     17038500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     83508000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total     83508000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data    100546500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total    100546500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data    100546500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total    100546500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.000006                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000077                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.000025                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52105.504587                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52920.152091                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52780.314961                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52780.314961                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse              2058.168190                       # Cycle average of tags in use
@@ -166,36 +199,75 @@ system.cpu.l2cache.total_refs                    1861                       # To
 system.cpu.l2cache.sampled_refs                  3164                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.588180                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0          2058.146434                       # Average occupied blocks per context
-system.cpu.l2cache.occ_blocks::1             0.021756                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.062810                       # Average percentage of cache occupancy
-system.cpu.l2cache.occ_percent::1            0.000001                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                  1861                       # number of ReadReq hits
-system.cpu.l2cache.Writeback_hits                   7                       # number of Writeback hits
-system.cpu.l2cache.ReadExReq_hits                   3                       # number of ReadExReq hits
-system.cpu.l2cache.demand_hits                   1864                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                  1864                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                3160                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses              1575                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                 4735                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                4735                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency     164335500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency     81900000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency      246235500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency     246235500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses              5021                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.Writeback_accesses               7                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses            1578                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses               6599                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses              6599                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.629357                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate       0.998099                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.717533                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.717533                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52004.905063                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52003.273495                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52003.273495                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::writebacks     0.021756                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.inst   1829.968899                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    228.177535                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::writebacks     0.000001                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.inst     0.055846                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.006963                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.062810                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst         1854                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data            7                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total           1861                       # number of ReadReq hits
+system.cpu.l2cache.Writeback_hits::writebacks            7                       # number of Writeback hits
+system.cpu.l2cache.Writeback_hits::total            7                       # number of Writeback hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data            3                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::total            3                       # number of ReadExReq hits
+system.cpu.l2cache.demand_hits::cpu.inst         1854                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           10                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total            1864                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst         1854                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           10                       # number of overall hits
+system.cpu.l2cache.overall_hits::total           1864                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst         2840                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          320                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total         3160                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data         1575                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total         1575                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst         2840                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data         1895                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total          4735                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst         2840                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data         1895                       # number of overall misses
+system.cpu.l2cache.overall_misses::total         4735                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst    147694000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data     16641500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total    164335500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     81900000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total     81900000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst    147694000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     98541500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total    246235500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst    147694000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     98541500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total    246235500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst         4694                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          327                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total         5021                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::writebacks            7                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_accesses::total            7                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data         1578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total         1578                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst         4694                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data         1905                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total         6599                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst         4694                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data         1905                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total         6599                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.605028                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.978593                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.998099                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.605028                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.994751                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.605028                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.994751                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52004.929577                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52004.687500                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52004.929577                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000.791557                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52004.929577                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000.791557                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -204,30 +276,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses           3160                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses         1575                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses            4735                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses           4735                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency    126400000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency     63000000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency    189400000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency    189400000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.629357                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate     0.998099                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.717533                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.717533                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst         2840                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          320                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total         3160                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data         1575                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total         1575                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst         2840                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data         1895                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total         4735                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst         2840                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data         1895                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total         4735                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst    113600000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data     12800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total    126400000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     63000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     63000000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    113600000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     75800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total    189400000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    113600000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     75800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total    189400000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.978593                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.998099                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.605028                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.994751                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index bd95bae4949c3156e99298eb8f9e33d3972b957c..ab088d9ce1f0e644df87e063826e5c3fdf446005 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -71,6 +72,7 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu0.tracer
 width=1
+workload=
 dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
@@ -85,20 +87,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -121,20 +116,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -180,6 +168,7 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu1.tracer
 width=1
+workload=
 dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
@@ -194,20 +183,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -230,20 +212,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -327,20 +302,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -359,20 +327,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -398,7 +359,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -468,7 +428,6 @@ pio=system.iobus.port[25]
 type=TsunamiCChip
 pio_addr=8803072344064
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
@@ -550,7 +509,6 @@ fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -567,7 +525,6 @@ fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -584,7 +541,6 @@ fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -601,7 +557,6 @@ fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -618,7 +573,6 @@ fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -635,7 +589,6 @@ fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -652,7 +605,6 @@ fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -669,7 +621,6 @@ fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -686,7 +637,6 @@ fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -703,7 +653,6 @@ fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -720,7 +669,6 @@ fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -737,7 +685,6 @@ fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -754,7 +701,6 @@ fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -771,7 +717,6 @@ fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -788,7 +733,6 @@ fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -805,7 +749,6 @@ fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -822,7 +765,6 @@ fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -839,7 +781,6 @@ fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -856,7 +797,6 @@ fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -872,7 +812,6 @@ type=BadDevice
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
-platform=system.tsunami
 system=system
 pio=system.iobus.port[22]
 
@@ -937,7 +876,6 @@ type=TsunamiIO
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=1000
-platform=system.tsunami
 system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
@@ -948,7 +886,6 @@ pio=system.iobus.port[23]
 type=TsunamiPChip
 pio_addr=8802535473152
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[2]
index dbef4ddb709e70d8dc43dbc17983b284bc4ae7d3..78e7255208bb19a29e53e91e629e67e3c7f1538e 100755 (executable)
@@ -1,12 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:39
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
 gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
index c3dae46840a1dc092d026974088203c0783aa230..a6953794db5d630b67d1d69283fcee27ca453473 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.870336                       # Nu
 sim_ticks                                1870335522500                       # Number of ticks simulated
 final_tick                               1870335522500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3272042                       # Simulator instruction rate (inst/s)
-host_tick_rate                            96902915749                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 296264                       # Number of bytes of host memory used
-host_seconds                                    19.30                       # Real time elapsed on the host
+host_inst_rate                                4204751                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4204746                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                           124525337361                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 293604                       # Number of bytes of host memory used
+host_seconds                                    15.02                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
+sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    72297472                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 995008                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10452352                       # Number of bytes written to this memory
@@ -25,102 +27,111 @@ system.l2c.total_refs                         2341203                       # To
 system.l2c.sampled_refs                       1087985                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.151871                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                     990121000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 10019.673951                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   266.115685                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23831.931773                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.152888                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.004061                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.363646                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1620505                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     137130                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        23831.931773                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3683.485712                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          6336.188239                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           152.381317                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data           113.734368                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.363646                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.056206                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.096683                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.002325                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.001735                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.520595                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             871618                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             748887                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             101445                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              35685                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1757635                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   811846                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          811846                       # number of Writeback hits
 system.l2c.Writeback_hits::total               811846                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     134                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                      39                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data             134                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              39                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 173                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                    15                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                     9                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            15                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data             9                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                24                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   164417                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    14126                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data           164417                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            14126                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               178543                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1784922                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      151256                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              871618                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              913304                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              101445                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               49811                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1936178                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1784922                       # number of overall hits
-system.l2c.overall_hits::1                     151256                       # number of overall hits
-system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             871618                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             913304                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             101445                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              49811                       # number of overall hits
 system.l2c.overall_hits::total                1936178                       # number of overall hits
-system.l2c.ReadReq_misses::0                   956917                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     4511                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            13362                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           943555                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             2185                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             2326                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               961428                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  2441                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                   567                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2441                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           567                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              3008                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                  65                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                 101                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           65                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          101                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total             166                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                 117481                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                   9826                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data         117481                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           9826                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             127307                       # number of ReadExReq misses
-system.l2c.demand_misses::0                   1074398                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     14337                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             13362                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data           1061036                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              2185                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             12152                       # number of demand (read+write) misses
 system.l2c.demand_misses::total               1088735                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                  1074398                       # number of overall misses
-system.l2c.overall_misses::1                    14337                       # number of overall misses
-system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            13362                       # number of overall misses
+system.l2c.overall_misses::cpu0.data          1061036                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             2185                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            12152                       # number of overall misses
 system.l2c.overall_misses::total              1088735                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2577422                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 141641                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         884980                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1692442                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         103630                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          38011                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2719063                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               811846                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       811846                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           811846                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2575                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                 606                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2575                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          606                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            3181                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0                80                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               110                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           80                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          110                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total           190                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               281898                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                23952                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       281898                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        23952                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           305850                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2859320                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  165593                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          884980                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1974340                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          103630                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           61963                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             3024913                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2859320                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 165593                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         884980                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1974340                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         103630                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          61963                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            3024913                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.371269                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.031848                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.947961                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.935644                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.812500                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.918182                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.416750                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.410237                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.375753                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.086580                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.375753                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.086580                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2        no_value                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2       no_value                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015099                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.557511                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.021085                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.061193                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.947961                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.935644                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.812500                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.918182                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.416750                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.410237                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015099                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.537413                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.021085                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.196117                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015099                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.537413                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.021085                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.196117                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -129,28 +140,8 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          121798                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          no_value                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         no_value                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              121798                       # number of writebacks
+system.l2c.writebacks::total                   121798                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41695                       # number of replacements
 system.iocache.tagsinuse                     0.435437                       # Cycle average of tags in use
@@ -158,50 +149,29 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     41711                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.435437                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.027215                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  175                       # number of ReadReq misses
+system.iocache.occ_blocks::tsunami.ide       0.435437                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.027215                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.027215                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41727                       # number of demand (read+write) misses
+system.iocache.demand_misses::tsunami.ide        41727                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41727                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41727                       # number of overall misses
+system.iocache.overall_misses::tsunami.ide        41727                       # number of overall misses
 system.iocache.overall_misses::total            41727                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                175                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::tsunami.ide          175                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            175                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41727                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41727                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41727                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41727                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41727                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41727                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -210,26 +180,8 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41520                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -278,7 +230,8 @@ system.cpu0.itb.data_accesses                       0                       # DT
 system.cpu0.numCycles                      3740670933                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.num_insts                        57222076                       # Number of instructions executed
+system.cpu0.committedInsts                   57222076                       # Number of instructions committed
+system.cpu0.committedOps                     57222076                       # Number of ops (including micro ops) committed
 system.cpu0.num_int_alu_accesses             53249924                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                299810                       # Number of float alu accesses
 system.cpu0.num_func_calls                    1399585                       # number of times a function call or return occured
@@ -422,47 +375,30 @@ system.cpu0.icache.total_refs                56345132                       # To
 system.cpu0.icache.sampled_refs                884916                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                 63.672859                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           511.244754                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.998525                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0           56345132                       # number of ReadReq hits
+system.cpu0.icache.occ_blocks::cpu0.inst   511.244754                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.998525                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.998525                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     56345132                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       56345132                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0            56345132                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu0.inst     56345132                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::total        56345132                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0           56345132                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu0.inst     56345132                       # number of overall hits
 system.cpu0.icache.overall_hits::total       56345132                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0           885000                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu0.inst       885000                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total       885000                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0            885000                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu0.inst       885000                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total        885000                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0           885000                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu0.inst       885000                       # number of overall misses
 system.cpu0.icache.overall_misses::total       885000                       # number of overall misses
-system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0       57230132                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     57230132                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total     57230132                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0        57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu0.inst     57230132                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::total     57230132                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0       57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     57230132                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     57230132                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.015464                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.015464                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.015464                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.015464                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.015464                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.015464                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -471,26 +407,8 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                      95                       # number of writebacks
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.writebacks::writebacks           95                       # number of writebacks
+system.cpu0.icache.writebacks::total               95                       # number of writebacks
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements               1978962                       # number of replacements
 system.cpu0.dcache.tagsinuse               504.827058                       # Cycle average of tags in use
@@ -498,68 +416,51 @@ system.cpu0.dcache.total_refs                13123502                       # To
 system.cpu0.dcache.sampled_refs               1979474                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                  6.629793                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           504.827058                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.985990                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            7298106                       # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   504.827058                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.985990                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.985990                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7298106                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        7298106                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           5462265                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5462265                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total       5462265                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       172138                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       172138                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       172138                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::       186635                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       186635                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       186635                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0            12760371                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data     12760371                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::total        12760371                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0           12760371                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu0.data     12760371                       # number of overall hits
 system.cpu0.dcache.overall_hits::total       12760371                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0          1683563                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1683563                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      1683563                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0          285996                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       285996                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total       285996                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0        16159                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16159                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total        16159                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0          703                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          703                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total          703                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0           1969559                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data      1969559                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total       1969559                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0          1969559                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu0.data      1969559                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      1969559                       # number of overall misses
-system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        8981669                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8981669                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      8981669                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::      5748261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5748261                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5748261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       188297                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       188297                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       188297                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       187338                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       187338                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       187338                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     14729930                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total     14729930                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14729930                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14729930                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.187444                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.049753                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085817                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.003753                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.133711                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.133711                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.187444                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049753                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085817                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.003753                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.133711                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.133711                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -568,26 +469,8 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  771740                       # number of writebacks
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks       771740                       # number of writebacks
+system.cpu0.dcache.writebacks::total           771740                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
@@ -624,7 +507,8 @@ system.cpu1.itb.data_accesses                       0                       # DT
 system.cpu1.numCycles                      3740248881                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.num_insts                         5931958                       # Number of instructions executed
+system.cpu1.committedInsts                    5931958                       # Number of instructions committed
+system.cpu1.committedOps                      5931958                       # Number of ops (including micro ops) committed
 system.cpu1.num_int_alu_accesses              5550578                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                 28590                       # Number of float alu accesses
 system.cpu1.num_func_calls                     182742                       # number of times a function call or return occured
@@ -720,47 +604,30 @@ system.cpu1.icache.total_refs                 5832136                       # To
 system.cpu1.icache.sampled_refs                103603                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                 56.293119                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle          1868933059000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           427.126317                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.834231                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0            5832136                       # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst   427.126317                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.834231                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.834231                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      5832136                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        5832136                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0             5832136                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::cpu1.inst      5832136                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::total         5832136                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0            5832136                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::cpu1.inst      5832136                       # number of overall hits
 system.cpu1.icache.overall_hits::total        5832136                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0           103630                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::cpu1.inst       103630                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total       103630                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0            103630                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst       103630                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total        103630                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0           103630                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst       103630                       # number of overall misses
 system.cpu1.icache.overall_misses::total       103630                       # number of overall misses
-system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0        5935766                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      5935766                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total      5935766                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0         5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::cpu1.inst      5935766                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::total      5935766                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0        5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      5935766                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      5935766                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.017459                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.017459                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.017459                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.017459                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.017459                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.017459                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -769,26 +636,8 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                      15                       # number of writebacks
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks           15                       # number of writebacks
+system.cpu1.icache.writebacks::total               15                       # number of writebacks
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                 62338                       # number of replacements
 system.cpu1.dcache.tagsinuse               391.951263                       # Cycle average of tags in use
@@ -796,68 +645,51 @@ system.cpu1.dcache.total_refs                 1834544                       # To
 system.cpu1.dcache.sampled_refs                 62657                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                 29.279155                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1851267520500                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           391.951263                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.765530                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            1109315                       # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data   391.951263                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.765530                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.765530                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1109315                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        1109315                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0            707444                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       707444                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total        707444                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0        15129                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        15129                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        15129                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::        15613                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        15613                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        15613                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0             1816759                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data      1816759                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total         1816759                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0            1816759                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data      1816759                       # number of overall hits
 system.cpu1.dcache.overall_hits::total        1816759                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0            41650                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data        41650                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total        41650                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0           25861                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        25861                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total        25861                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0         1289                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data         1289                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total         1289                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0          732                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          732                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total          732                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0             67511                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data        67511                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total         67511                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0            67511                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data        67511                       # number of overall misses
 system.cpu1.dcache.overall_misses::total        67511                       # number of overall misses
-system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        1150965                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1150965                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      1150965                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::       733305                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data       733305                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total       733305                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0        16418                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        16418                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        16418                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0        16345                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        16345                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        16345                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0         1884270                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data      1884270                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total      1884270                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0        1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      1884270                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1884270                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.036187                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.035266                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.078511                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.044784                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.035829                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.035829                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.036187                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.035266                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.078511                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.044784                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.035829                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.035829                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -866,26 +698,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                   39996                       # number of writebacks
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks        39996                       # number of writebacks
+system.cpu1.dcache.writebacks::total            39996                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b72ae72cb4b69d6f763e10cfb06b65c05ce0f0ae..435421de905c5b339a072aa925fc65da431baec1 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -71,6 +72,7 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
+workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
@@ -85,20 +87,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -121,20 +116,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -218,20 +206,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -250,20 +231,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -289,7 +263,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -359,7 +332,6 @@ pio=system.iobus.port[25]
 type=TsunamiCChip
 pio_addr=8803072344064
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
@@ -441,7 +413,6 @@ fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -458,7 +429,6 @@ fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -475,7 +445,6 @@ fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -492,7 +461,6 @@ fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -509,7 +477,6 @@ fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -526,7 +493,6 @@ fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -543,7 +509,6 @@ fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -560,7 +525,6 @@ fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -577,7 +541,6 @@ fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -594,7 +557,6 @@ fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -611,7 +573,6 @@ fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -628,7 +589,6 @@ fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -645,7 +605,6 @@ fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -662,7 +621,6 @@ fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -679,7 +637,6 @@ fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -696,7 +653,6 @@ fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -713,7 +669,6 @@ fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -730,7 +685,6 @@ fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -747,7 +701,6 @@ fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -763,7 +716,6 @@ type=BadDevice
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
-platform=system.tsunami
 system=system
 pio=system.iobus.port[22]
 
@@ -828,7 +780,6 @@ type=TsunamiIO
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=1000
-platform=system.tsunami
 system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
@@ -839,7 +790,6 @@ pio=system.iobus.port[23]
 type=TsunamiPChip
 pio_addr=8802535473152
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[2]
index 9b658d14ce4081002e94d980aa182c32f2631c72..484a5fec915fd0085998e31a60e767ac800faab0 100755 (executable)
@@ -1,12 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:39
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
 gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1829332258000 because m5_exit instruction encountered
index 7f4c99b34e1456f4c495d7408547a2bc2bfc47c7..d300de39a265e7ebd64268c09113dfcfb3186548 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332258000                       # Number of ticks simulated
 final_tick                               1829332258000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3300922                       # Simulator instruction rate (inst/s)
-host_tick_rate                           100577077281                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 294216                       # Number of bytes of host memory used
-host_seconds                                    18.19                       # Real time elapsed on the host
+host_inst_rate                                4111639                       # Simulator instruction rate (inst/s)
+host_op_rate                                  4111633                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                           125278906724                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 291412                       # Number of bytes of host memory used
+host_seconds                                    14.60                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
+sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    71650816                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 955904                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10156864                       # Number of bytes written to this memory
@@ -25,67 +27,64 @@ system.l2c.total_refs                         2291835                       # To
 system.l2c.sampled_refs                       1077848                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.126306                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                     765422500                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 10193.605493                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 23613.410409                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.155542                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.360312                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1699395                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        23613.410409                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3680.391656                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6513.213838                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.360312                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.056158                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.099384                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.515854                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst              905267                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              794128                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1699395                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   825291                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          825291                       # number of Writeback hits
 system.l2c.Writeback_hits::total               825291                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                       1                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data                1                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   1                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   185383                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            185383                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               185383                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1884778                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               905267                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               979511                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1884778                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1884778                       # number of overall hits
-system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              905267                       # number of overall hits
+system.l2c.overall_hits::cpu.data              979511                       # number of overall hits
 system.l2c.overall_hits::total                1884778                       # number of overall hits
-system.l2c.ReadReq_misses::0                   959629                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             14936                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            944693                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               959629                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                    12                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data             12                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                12                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 118859                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          118859                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             118859                       # number of ReadExReq misses
-system.l2c.demand_misses::0                   1078488                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              14936                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data            1063552                       # number of demand (read+write) misses
 system.l2c.demand_misses::total               1078488                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                  1078488                       # number of overall misses
-system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             14936                       # number of overall misses
+system.l2c.overall_misses::cpu.data           1063552                       # number of overall misses
 system.l2c.overall_misses::total              1078488                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2659024                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          920203                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1738821                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2659024                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               825291                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       825291                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           825291                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               304242                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        304242                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           304242                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2963266                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           920203                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          2043063                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2963266                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2963266                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          920203                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         2043063                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2963266                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.360895                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.923077                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.390673                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.363952                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.363952                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1        no_value                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1       no_value                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.inst       0.016231                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.543295                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.923077                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.390673                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.016231                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.520567                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.016231                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.520567                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -94,26 +93,8 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          117189                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          no_value                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      no_value                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         no_value                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              117189                       # number of writebacks
+system.l2c.writebacks::total                   117189                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41686                       # number of replacements
 system.iocache.tagsinuse                     1.225570                       # Cycle average of tags in use
@@ -121,50 +102,29 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     41702                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 1.225570                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.076598                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  174                       # number of ReadReq misses
+system.iocache.occ_blocks::tsunami.ide       1.225570                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.076598                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.076598                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
+system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41726                       # number of overall misses
+system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
 system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -173,26 +133,8 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41512                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -241,7 +183,8 @@ system.cpu.itb.data_accesses                        0                       # DT
 system.cpu.numCycles                       3658664408                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         60038305                       # Number of instructions executed
+system.cpu.committedInsts                    60038305                       # Number of instructions committed
+system.cpu.committedOps                      60038305                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              55913521                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324460                       # Number of float alu accesses
 system.cpu.num_func_calls                     1484182                       # number of times a function call or return occured
@@ -380,47 +323,30 @@ system.cpu.icache.total_refs                 59129922                       # To
 system.cpu.icache.sampled_refs                 920106                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  64.264250                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            511.215243                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0            59129922                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     511.215243                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.998467                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.998467                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     59129922                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        59129922                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0             59129922                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst      59129922                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total         59129922                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0            59129922                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst     59129922                       # number of overall hits
 system.cpu.icache.overall_hits::total        59129922                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            920221                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       920221                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        920221                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             920221                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       920221                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         920221                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            920221                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       920221                       # number of overall misses
 system.cpu.icache.overall_misses::total        920221                       # number of overall misses
-system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0        60050143                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst     60050143                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     60050143                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0         60050143                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst     60050143                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total     60050143                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0        60050143                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60050143                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60050143                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.015324                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.015324                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.015324                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.015324                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.015324                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.015324                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -429,26 +355,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      108                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks          108                       # number of writebacks
+system.cpu.icache.writebacks::total               108                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                2042700                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997802                       # Cycle average of tags in use
@@ -456,65 +364,48 @@ system.cpu.dcache.total_refs                 14038433                       # To
 system.cpu.dcache.sampled_refs                2043212                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   6.870767                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.997802                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0             7807782                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7807782                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7807782                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            5848212                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848212                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        5848212                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::       183141                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183141                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       183141                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         199282                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199282                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199282                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             13655994                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      13655994                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         13655994                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            13655994                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     13655994                       # number of overall hits
 system.cpu.dcache.overall_hits::total        13655994                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1721705                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1721705                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1721705                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           304362                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304362                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       304362                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        17162                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17162                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        17162                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0            2026067                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      2026067                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        2026067                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           2026067                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      2026067                       # number of overall misses
 system.cpu.dcache.overall_misses::total       2026067                       # number of overall misses
-system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0         9529487                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data      9529487                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      9529487                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        6152574                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152574                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6152574                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       200303                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200303                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       200303                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       199282                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199282                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       199282                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     15682061                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     15682061                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15682061                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15682061                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.180671                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.049469                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085680                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.129196                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.129196                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.180671                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049469                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085680                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.129196                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.129196                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -523,26 +414,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   825183                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       825183                       # number of writebacks
+system.cpu.dcache.writebacks::total            825183                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 1a4bf8750e479cc41e1342408a4218b398b00f73..110cfac39692f7b8df81382b5fcb447da3354c29 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -68,6 +69,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu0.tracer
+workload=
 dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
@@ -82,20 +84,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -118,20 +113,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -174,6 +162,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu1.tracer
+workload=
 dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
@@ -188,20 +177,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -224,20 +206,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -321,20 +296,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -353,20 +321,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -392,7 +353,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -462,7 +422,6 @@ pio=system.iobus.port[25]
 type=TsunamiCChip
 pio_addr=8803072344064
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
@@ -544,7 +503,6 @@ fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -561,7 +519,6 @@ fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -578,7 +535,6 @@ fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -595,7 +551,6 @@ fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -612,7 +567,6 @@ fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -629,7 +583,6 @@ fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -646,7 +599,6 @@ fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -663,7 +615,6 @@ fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -680,7 +631,6 @@ fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -697,7 +647,6 @@ fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -714,7 +663,6 @@ fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -731,7 +679,6 @@ fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -748,7 +695,6 @@ fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -765,7 +711,6 @@ fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -782,7 +727,6 @@ fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -799,7 +743,6 @@ fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -816,7 +759,6 @@ fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -833,7 +775,6 @@ fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -850,7 +791,6 @@ fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -866,7 +806,6 @@ type=BadDevice
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
-platform=system.tsunami
 system=system
 pio=system.iobus.port[22]
 
@@ -931,7 +870,6 @@ type=TsunamiIO
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=1000
-platform=system.tsunami
 system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
@@ -942,7 +880,6 @@ pio=system.iobus.port[23]
 type=TsunamiPChip
 pio_addr=8802535473152
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[2]
index 3af3fc1ddfc45c92d3ab7d76f13f34e7887b03ec..b1f6452666a9bd13bb1ce9b8b8df9c14173320a4 100755 (executable)
@@ -1,12 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:23:09
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:02
 gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 562628000
index 628ea2e3eaa657557020e701d6a32b398d063524..565674386c3d78d1a9a522fd11bb6fb153109e1e 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.958647                       # Nu
 sim_ticks                                1958647095000                       # Number of ticks simulated
 final_tick                               1958647095000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1643366                       # Simulator instruction rate (inst/s)
-host_tick_rate                            54228566310                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 293036                       # Number of bytes of host memory used
-host_seconds                                    36.12                       # Real time elapsed on the host
+host_inst_rate                                1989502                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1989500                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            65650485361                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 290388                       # Number of bytes of host memory used
+host_seconds                                    29.83                       # Real time elapsed on the host
 sim_insts                                    59355643                       # Number of instructions simulated
+sim_ops                                      59355643                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    30050624                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 971200                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10333120                       # Number of bytes written to this memory
@@ -25,122 +27,153 @@ system.l2c.total_refs                         2371449                       # To
 system.l2c.sampled_refs                        427769                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          5.543761                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                   10882116000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 10867.929163                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                   199.983935                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 23419.887612                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.165831                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.003052                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.357359                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1659395                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     119191                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        23419.887612                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          3728.336055                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          7139.593108                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst           100.838318                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data            99.145617                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.357359                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.056890                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.108942                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.001539                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.001513                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.526242                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst             901389                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             758006                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst              86187                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data              33004                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1778586                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   816294                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          816294                       # number of Writeback hits
 system.l2c.Writeback_hits::total               816294                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     172                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                      53                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data             172                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data              53                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 225                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                    18                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                    19                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data            18                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data            19                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total                37                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                   170288                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    12569                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data           170288                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            12569                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               182857                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1829683                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      131760                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              901389                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              928294                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst               86187                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data               45573                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1961443                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1829683                       # number of overall hits
-system.l2c.overall_hits::1                     131760                       # number of overall hits
-system.l2c.overall_hits::2                          0                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             901389                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             928294                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst              86187                       # number of overall hits
+system.l2c.overall_hits::cpu1.data              45573                       # number of overall hits
 system.l2c.overall_hits::total                1961443                       # number of overall hits
-system.l2c.ReadReq_misses::0                   302827                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     1953                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst            14371                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data           288456                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst              815                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             1138                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               304780                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  2453                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                   495                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          2453                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data           495                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2948                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                  15                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                  74                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data           15                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data           74                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total              89                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                 117546                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                   6196                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data         117546                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data           6196                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             123742                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    420373                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                      8149                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst             14371                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            406002                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               815                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data              7334                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                428522                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   420373                       # number of overall misses
-system.l2c.overall_misses::1                     8149                       # number of overall misses
-system.l2c.overall_misses::2                        0                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst            14371                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           406002                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              815                       # number of overall misses
+system.l2c.overall_misses::cpu1.data             7334                       # number of overall misses
 system.l2c.overall_misses::total               428522                       # number of overall misses
-system.l2c.ReadReq_miss_latency           15853640000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency            3024000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency           416000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6434878000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            22288518000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           22288518000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                1962222                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 121144                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0.inst    747344500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data  15004707000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst     42364500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data     59224000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15853640000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data      2244000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data       780000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      3024000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data       104000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data       312000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total       416000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   6112681000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data    322197000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6434878000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    747344500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data  21117388000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst     42364500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data    381421000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     22288518000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    747344500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data  21117388000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst     42364500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data    381421000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    22288518000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst         915760                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data        1046462                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst          87002                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data          34142                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2083366                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               816294                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       816294                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           816294                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2625                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                 548                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         2625                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data          548                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            3173                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0                33                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1                93                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data           33                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data           93                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total           126                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               287834                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                18765                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       287834                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data        18765                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           306599                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2250056                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  139909                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          915760                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data         1334296                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst           87002                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data           52907                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2389965                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2250056                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 139909                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         915760                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data        1334296                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst          87002                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data          52907                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2389965                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.154329                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.016121                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.934476                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.903285                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.454545                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.795699                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.408381                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.330189                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.186828                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.058245                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.186828                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.058245                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52352.135047                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   8117583.205325                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2            inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  1232.776192                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1  6109.090909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0 27733.333333                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1  5621.621622                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 54743.487656                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 1038553.582957                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    53020.812469                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    2735123.082587                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2             inf                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   53020.812469                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   2735123.082587                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2            inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.015693                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.275649                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.009368                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.033331                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.934476                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.903285                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.454545                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.795699                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.408381                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.330189                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.015693                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.304282                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.009368                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.138621                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.015693                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.304282                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.009368                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.138621                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52003.653190                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52017.316332                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51980.981595                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52042.179262                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data   914.798206                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  1575.757576                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  6933.333333                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  4216.216216                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52002.458612                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52000.806972                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52003.653190                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52013.014714                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 51980.981595                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52007.226616                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52003.653190                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52013.014714                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 51980.981595                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52007.226616                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -149,61 +182,113 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          119935                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                       11                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                        11                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                       11                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                 304769                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                2948                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses                89                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               123742                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  428511                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 428511                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency      12195855000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     117981000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency      3560000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4949974000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency       17145829000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency      17145829000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency    802314500                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1391411500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   2193726000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.155318                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         2.515758                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2              inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.123048                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      5.379562                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     2.696970                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     0.956989                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.429908                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       6.594298                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.190445                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          3.062784                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2               inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.190445                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         3.062784                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2              inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.717580                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40020.691995                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency        40000                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40002.375911                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40012.576107                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40012.576107                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              119935                       # number of writebacks
+system.l2c.writebacks::total                   119935                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu1.inst            11                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                11                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst             11                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 11                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst            11                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                11                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst        14371                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data       288456                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst          804                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         1138                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          304769                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         2453                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data          495                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2948                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data           15                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data           74                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total           89                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data       117546                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data         6196                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        123742                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst        14371                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       406002                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst          804                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data         7334                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           428511                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst        14371                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       406002                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst          804                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data         7334                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          428511                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    574888000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data  11543235000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst     32164000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data     45568000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  12195855000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data     98181000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data     19800000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    117981000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data       600000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data      2960000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total      3560000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   4702129000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data    247845000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4949974000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    574888000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data  16245364000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst     32164000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data    293413000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  17145829000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    574888000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data  16245364000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst     32164000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data    293413000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  17145829000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data    792100000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data     10214500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    802314500                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data   1122200000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    269211500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1391411500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data   1914300000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data    279426000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   2193726000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.275649                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.033331                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.934476                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.903285                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.454545                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.795699                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.408381                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.330189                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.304282                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.138621                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.015693                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.304282                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.009241                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.138621                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40017.316332                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40042.179262                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40024.867509                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.458612                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000.806972                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40013.014714                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40007.226616                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40003.340060                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40013.014714                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40004.975124                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40007.226616                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41694                       # number of replacements
 system.iocache.tagsinuse                     0.563721                       # Cycle average of tags in use
@@ -211,58 +296,41 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     41710                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1751545158000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.563721                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.035233                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  174                       # number of ReadReq misses
+system.iocache.occ_blocks::tsunami.ide       0.563721                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.035233                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.035233                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41726                       # number of demand (read+write) misses
+system.iocache.demand_misses::tsunami.ide        41726                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41726                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41726                       # number of overall misses
+system.iocache.overall_misses::tsunami.ide        41726                       # number of overall misses
 system.iocache.overall_misses::total            41726                       # number of overall misses
-system.iocache.ReadReq_miss_latency          20052998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       5721783806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         5741836804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        5741836804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                174                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_latency::tsunami.ide     20052998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     20052998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   5721783806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5721783806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5741836804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5741836804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5741836804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5741836804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          174                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            174                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41726                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41726                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41726                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41726                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41726                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41726                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115247.114943                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137701.766606                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137608.129320                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137608.129320                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115247.114943                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137701.766606                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 137608.129320                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 137608.129320                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64596068                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10459                       # number of cycles access was blocked
@@ -271,38 +339,32 @@ system.iocache.avg_blocked_cycles::no_mshrs  6176.122765                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41520                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                174                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               41726                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              41726                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     11004998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3560928000                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    3571932998                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   3571932998                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63247.114943                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85698.113208                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85604.491157                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           41520                       # number of writebacks
+system.iocache.writebacks::total                41520                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          174                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          174                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41726                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41726                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41726                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41726                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     11004998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     11004998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3560928000                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3560928000                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3571932998                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3571932998                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3571932998                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3571932998                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63247.114943                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85698.113208                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85604.491157                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85604.491157                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -351,7 +413,8 @@ system.cpu0.itb.data_accesses                       0                       # DT
 system.cpu0.numCycles                      3916023774                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.num_insts                        54072652                       # Number of instructions executed
+system.cpu0.committedInsts                   54072652                       # Number of instructions committed
+system.cpu0.committedOps                     54072652                       # Number of ops (including micro ops) committed
 system.cpu0.num_int_alu_accesses             50043234                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                293967                       # Number of float alu accesses
 system.cpu0.num_func_calls                    1426863                       # number of times a function call or return occured
@@ -494,51 +557,39 @@ system.cpu0.icache.total_refs                53165471                       # To
 system.cpu0.icache.sampled_refs                915659                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                 58.062522                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           36696092000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           508.800486                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.993751                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0           53165471                       # number of ReadReq hits
+system.cpu0.icache.occ_blocks::cpu0.inst   508.800486                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.993751                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.993751                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     53165471                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       53165471                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0            53165471                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu0.inst     53165471                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::total        53165471                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0           53165471                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu0.inst     53165471                       # number of overall hits
 system.cpu0.icache.overall_hits::total       53165471                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0           915781                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu0.inst       915781                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total       915781                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0            915781                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu0.inst       915781                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total        915781                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0           915781                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu0.inst       915781                       # number of overall misses
 system.cpu0.icache.overall_misses::total       915781                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency   13429132500                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency    13429132500                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency   13429132500                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0       54081252                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst  13429132500                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total  13429132500                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst  13429132500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total  13429132500                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst  13429132500                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total  13429132500                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     54081252                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total     54081252                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0        54081252                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu0.inst     54081252                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::total     54081252                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0       54081252                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     54081252                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     54081252                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.016933                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.016933                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.016933                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14664.130944                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14664.130944                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14664.130944                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.016933                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.016933                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.016933                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14664.130944                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14664.130944                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14664.130944                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -547,119 +598,96 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                      55                       # number of writebacks
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses         915781                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses          915781                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses         915781                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency  10681093500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency  10681093500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency  10681093500                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.016933                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0     0.016933                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0     0.016933                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11663.370937                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11663.370937                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.writebacks::writebacks           55                       # number of writebacks
+system.cpu0.icache.writebacks::total               55                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       915781                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       915781                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       915781                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       915781                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       915781                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       915781                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst  10681093500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total  10681093500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst  10681093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total  10681093500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst  10681093500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total  10681093500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.016933                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11663.370937                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements               1338438                       # number of replacements
-system.cpu0.dcache.tagsinuse               502.524901                       # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse               503.524900                       # Cycle average of tags in use
 system.cpu0.dcache.total_refs                13348404                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs               1338837                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                  9.970149                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           503.524900                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -1.000000                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.983447                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1           -0.001953                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            7421006                       # number of ReadReq hits
+system.cpu0.dcache.warmup_cycle              83958000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.occ_blocks::cpu0.data   503.524900                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.983447                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.983447                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7421006                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        7421006                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           5560133                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5560133                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total       5560133                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       176505                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       176505                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       176505                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::       191674                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       191674                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       191674                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0            12981139                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data     12981139                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::total        12981139                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0           12981139                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu0.data     12981139                       # number of overall hits
 system.cpu0.dcache.overall_hits::total       12981139                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0          1036101                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu0.data      1036101                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total      1036101                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0          291536                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       291536                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total       291536                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0        16544                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data        16544                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total        16544                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0          410                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data          410                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total          410                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0           1327637                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data      1327637                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total       1327637                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0          1327637                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu0.data      1327637                       # number of overall misses
 system.cpu0.dcache.overall_misses::total      1327637                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency   26570279500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency   9109954000                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency    234949000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency      2973000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency    35680233500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency   35680233500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        8457107                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data  26570279500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total  26570279500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   9109954000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   9109954000                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    234949000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    234949000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data      2973000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total      2973000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data  35680233500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total  35680233500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data  35680233500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total  35680233500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      8457107                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      8457107                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::      5851669                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5851669                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5851669                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       193049                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       193049                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       193049                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       192084                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       192084                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       192084                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        14308776                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     14308776                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total     14308776                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       14308776                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     14308776                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     14308776                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.122512                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.049821                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.085698                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.002134                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.092785                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.092785                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 25644.487844                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 31248.127161                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 14201.462766                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  7251.219512                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 26874.991809                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 26874.991809                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.122512                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.049821                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.085698                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.002134                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.092785                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.092785                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25644.487844                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 31248.127161                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14201.462766                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  7251.219512                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 26874.991809                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 26874.991809                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -668,54 +696,53 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  786441                       # number of writebacks
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses        1036101                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses        291536                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses        16544                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses          410                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses         1327637                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses        1327637                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency  23461938500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency   8235346000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency    185317000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency      1743000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency  31697284500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency  31697284500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency    884470000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency   1242107000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency   2126577000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.122512                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.049821                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.085698                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.002134                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.092785                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.092785                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 22644.451168                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 28248.127161                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11201.462766                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  4251.219512                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 23874.963186                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks       786441                       # number of writebacks
+system.cpu0.dcache.writebacks::total           786441                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data      1036101                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total      1036101                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       291536                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       291536                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data        16544                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total        16544                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data          410                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total          410                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data      1327637                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total      1327637                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data      1327637                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total      1327637                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data  23461938500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total  23461938500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   8235346000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   8235346000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data    185317000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total    185317000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data      1743000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total      1743000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data  31697284500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total  31697284500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data  31697284500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total  31697284500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data    884470000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total    884470000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data   1242107000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total   1242107000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data   2126577000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total   2126577000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.122512                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.049821                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.085698                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.002134                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.092785                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.092785                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 22644.451168                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 28248.127161                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11201.462766                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  4251.219512                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23874.963186                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.fetch_hits                          0                       # ITB hits
 system.cpu1.dtb.fetch_misses                        0                       # ITB misses
@@ -752,7 +779,8 @@ system.cpu1.itb.data_accesses                       0                       # DT
 system.cpu1.numCycles                      3917294190                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.num_insts                         5282991                       # Number of instructions executed
+system.cpu1.committedInsts                    5282991                       # Number of instructions committed
+system.cpu1.committedOps                      5282991                       # Number of ops (including micro ops) committed
 system.cpu1.num_int_alu_accesses              4948310                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                 34031                       # Number of float alu accesses
 system.cpu1.num_func_calls                     158031                       # number of times a function call or return occured
@@ -843,51 +871,39 @@ system.cpu1.icache.total_refs                 5199349                       # To
 system.cpu1.icache.sampled_refs                 86969                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                 59.783935                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle          1942711132000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           419.807616                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.819937                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0            5199349                       # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst   419.807616                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.819937                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.819937                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst      5199349                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        5199349                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0             5199349                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::cpu1.inst      5199349                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::total         5199349                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0            5199349                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::cpu1.inst      5199349                       # number of overall hits
 system.cpu1.icache.overall_hits::total        5199349                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0            87005                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::cpu1.inst        87005                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total        87005                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0             87005                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst        87005                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total         87005                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0            87005                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst        87005                       # number of overall misses
 system.cpu1.icache.overall_misses::total        87005                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency    1260607500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency     1260607500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency    1260607500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0        5286354                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   1260607500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   1260607500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   1260607500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   1260607500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   1260607500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   1260607500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst      5286354                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total      5286354                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0         5286354                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::cpu1.inst      5286354                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::total      5286354                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0        5286354                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst      5286354                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total      5286354                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.016458                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.016458                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.016458                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14488.908683                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14488.908683                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14488.908683                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.016458                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.016458                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.016458                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14488.908683                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14488.908683                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14488.908683                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -896,32 +912,26 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                      14                       # number of writebacks
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses          87005                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses           87005                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses          87005                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency    999558500                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency    999558500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency    999558500                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.016458                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0     0.016458                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0     0.016458                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11488.517901                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11488.517901                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks           14                       # number of writebacks
+system.cpu1.icache.writebacks::total               14                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst        87005                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total        87005                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst        87005                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total        87005                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst        87005                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total        87005                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst    999558500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total    999558500                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst    999558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total    999558500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst    999558500                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total    999558500                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.016458                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11488.517901                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                 52960                       # number of replacements
 system.cpu1.dcache.tagsinuse               389.521271                       # Cycle average of tags in use
@@ -929,84 +939,69 @@ system.cpu1.dcache.total_refs                 1644934                       # To
 system.cpu1.dcache.sampled_refs                 53472                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                 30.762530                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle          1942411783000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           389.521271                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.760784                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            1003161                       # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data   389.521271                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.760784                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.760784                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      1003161                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        1003161                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0            616899                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data       616899                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total        616899                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0        11784                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data        11784                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total        11784                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::        11526                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data        11526                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total        11526                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0             1620060                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data      1620060                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total         1620060                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0            1620060                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data      1620060                       # number of overall hits
 system.cpu1.dcache.overall_hits::total        1620060                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0            37113                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data        37113                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total        37113                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0           20421                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data        20421                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total        20421                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0          982                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data          982                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total          982                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0          505                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data          505                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total          505                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0             57534                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data        57534                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total         57534                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0            57534                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data        57534                       # number of overall misses
 system.cpu1.dcache.overall_misses::total        57534                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency     533263000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency    556796000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency     13079000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency      6416000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency     1090059000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency    1090059000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        1040274                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data    533263000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total    533263000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data    556796000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total    556796000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data     13079000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total     13079000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data      6416000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total      6416000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   1090059000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   1090059000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   1090059000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   1090059000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      1040274                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      1040274                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::       637320                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data       637320                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total       637320                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0        12766                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data        12766                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total        12766                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0        12031                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data        12031                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total        12031                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0         1677594                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data      1677594                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total      1677594                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0        1677594                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data      1677594                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total      1677594                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.035676                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.032042                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.076923                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.041975                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.034296                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.034296                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14368.630938                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 27265.853778                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 13318.737271                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0 12704.950495                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 18946.344770                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 18946.344770                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.035676                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.032042                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.076923                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.041975                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.034296                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.034296                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14368.630938                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 27265.853778                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13318.737271                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 12704.950495                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 18946.344770                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18946.344770                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1015,54 +1010,53 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                   29784                       # number of writebacks
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses          37113                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses         20421                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses          982                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses          505                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses           57534                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses          57534                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency    421922000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency    495533000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     10133000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency      4901000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency    917455000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency    917455000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency     11413500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    298050500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency    309464000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.035676                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.032042                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.076923                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.041975                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.034296                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.034296                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11368.577048                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 24265.853778                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency 10318.737271                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  9704.950495                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 15946.310008                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks        29784                       # number of writebacks
+system.cpu1.dcache.writebacks::total            29784                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data        37113                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total        37113                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data        20421                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total        20421                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data          982                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total          982                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data          505                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total          505                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data        57534                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total        57534                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data        57534                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total        57534                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data    421922000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total    421922000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data    495533000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total    495533000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     10133000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     10133000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data      4901000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total      4901000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data    917455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total    917455000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data    917455000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total    917455000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data     11413500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total     11413500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    298050500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    298050500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data    309464000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total    309464000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.035676                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.032042                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.076923                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.041975                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.034296                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.034296                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11368.577048                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24265.853778                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 10318.737271                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  9704.950495                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 15946.310008                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 54195aa23ef4971bbb2c5842929781653013522e..c8fe39e3815e5d5bd4af0b858450e573360d91ae 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -68,6 +69,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
+workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
@@ -82,20 +84,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -118,20 +113,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -215,20 +203,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -247,20 +228,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -286,7 +260,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -356,7 +329,6 @@ pio=system.iobus.port[25]
 type=TsunamiCChip
 pio_addr=8803072344064
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[1]
@@ -438,7 +410,6 @@ fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -455,7 +426,6 @@ fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -472,7 +442,6 @@ fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -489,7 +458,6 @@ fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -506,7 +474,6 @@ fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -523,7 +490,6 @@ fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -540,7 +506,6 @@ fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -557,7 +522,6 @@ fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -574,7 +538,6 @@ fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -591,7 +554,6 @@ fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -608,7 +570,6 @@ fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -625,7 +586,6 @@ fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -642,7 +602,6 @@ fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -659,7 +618,6 @@ fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -676,7 +634,6 @@ fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -693,7 +650,6 @@ fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -710,7 +666,6 @@ fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -727,7 +682,6 @@ fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -744,7 +698,6 @@ fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
-platform=system.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -760,7 +713,6 @@ type=BadDevice
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
-platform=system.tsunami
 system=system
 pio=system.iobus.port[22]
 
@@ -825,7 +777,6 @@ type=TsunamiIO
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=1000
-platform=system.tsunami
 system=system
 time=Thu Jan  1 00:00:00 2009
 tsunami=system.tsunami
@@ -836,7 +787,6 @@ pio=system.iobus.port[23]
 type=TsunamiPChip
 pio_addr=8802535473152
 pio_latency=1000
-platform=system.tsunami
 system=system
 tsunami=system.tsunami
 pio=system.iobus.port[2]
index 826f2c28ba9b0e176b1e99fc829054815686ce12..e3d6e41acbd243d58e357b3219a3c76e89e5e902 100755 (executable)
@@ -1,12 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:22:43
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:47
 gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA_FS/tests/opt/quick/10.linux-boot/alpha/linux/tsunami-simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-      0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 1915548867000 because m5_exit instruction encountered
index ac9598c088eecb3d039440417264f28c44042ed4..713b264a4d44ddb4adf9b5b3230d6589d466f69e 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  1.915549                       # Nu
 sim_ticks                                1915548867000                       # Number of ticks simulated
 final_tick                               1915548867000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1659827                       # Simulator instruction rate (inst/s)
-host_tick_rate                            56637748152                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 290988                       # Number of bytes of host memory used
-host_seconds                                    33.82                       # Real time elapsed on the host
+host_inst_rate                                1998214                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1998212                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            68184353129                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 288188                       # Number of bytes of host memory used
+host_seconds                                    28.09                       # Real time elapsed on the host
 sim_insts                                    56137087                       # Number of instructions simulated
+sim_ops                                      56137087                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    29663360                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 943040                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10122368                       # Number of bytes written to this memory
@@ -25,79 +27,85 @@ system.l2c.total_refs                         2311163                       # To
 system.l2c.sampled_refs                        421794                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          5.479364                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                    6937912000                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 11241.373247                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 23110.665097                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.171530                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.352641                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1710461                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        23110.665097                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           3746.363547                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           7495.009700                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.352641                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.057165                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.114365                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.524171                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.inst              913599                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              796862                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1710461                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   826671                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          826671                       # number of Writeback hits
 system.l2c.Writeback_hits::total               826671                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                       6                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data                6                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   6                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   185878                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            185878                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               185878                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1896339                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                           0                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               913599                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               982740                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1896339                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1896339                       # number of overall hits
-system.l2c.overall_hits::1                          0                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              913599                       # number of overall hits
+system.l2c.overall_hits::cpu.data              982740                       # number of overall hits
 system.l2c.overall_hits::total                1896339                       # number of overall hits
-system.l2c.ReadReq_misses::0                   304138                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             14735                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data            289403                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total               304138                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                     7                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data              7                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                 7                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 118294                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          118294                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             118294                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    422432                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                         0                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              14735                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             407697                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                422432                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   422432                       # number of overall misses
-system.l2c.overall_misses::1                        0                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             14735                       # number of overall misses
+system.l2c.overall_misses::cpu.data            407697                       # number of overall misses
 system.l2c.overall_misses::total               422432                       # number of overall misses
-system.l2c.ReadReq_miss_latency           15820206500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency             248000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6151753000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency            21971959500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency           21971959500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2014599                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.inst    766261500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data  15053945000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total    15820206500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data       248000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       248000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6151753000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6151753000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.inst    766261500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data  21205698000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total     21971959500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.inst    766261500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data  21205698000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total    21971959500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.inst          928334                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1086265                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2014599                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               826671                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       826671                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           826671                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  13                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data           13                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              13                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               304172                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        304172                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           304172                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2318771                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                       0                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           928334                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1390437                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2318771                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2318771                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                      0                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          928334                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1390437                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2318771                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.150967                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.538462                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.388905                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.182179                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               no_value                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           no_value                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.182179                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              no_value                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          no_value                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52016.540189                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1            inf                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 35428.571429                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52003.930884                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52013.009194                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1             inf                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52013.009194                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1            inf                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.inst       0.015873                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.266420                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.538462                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.388905                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.inst        0.015873                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.293215                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.inst       0.015873                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.293215                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52002.816423                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52017.238937                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 35428.571429                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52003.930884                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52002.816423                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52013.377582                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52002.816423                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52013.377582                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -106,48 +114,59 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          116650                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                 304138                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                   7                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               118294                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  422432                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 422432                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency      12170545000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency        320000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4732225000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency       16902770000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency      16902770000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency    772673000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1083819500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   1856492500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.150967                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1              inf                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.538462                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.388905                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.182179                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1               inf                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total           inf                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.182179                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1              inf                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40016.522105                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 45714.285714                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40003.930884                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40012.996175                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40012.996175                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              116650                       # number of writebacks
+system.l2c.writebacks::total                   116650                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.inst        14735                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data       289403                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total          304138                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data            7                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total            7                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       118294                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        118294                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         14735                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        407697                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           422432                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        14735                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       407697                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          422432                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    589436000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data  11581109000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total  12170545000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data       320000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total       320000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4732225000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4732225000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    589436000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data  16313334000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total  16902770000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    589436000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data  16313334000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total  16902770000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data    772673000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total    772673000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1083819500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1083819500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data   1856492500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   1856492500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.266420                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.538462                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.388905                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.293215                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.015873                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.293215                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40017.238937                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 45714.285714                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40003.930884                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40013.377582                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40002.443163                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40013.377582                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     41685                       # number of replacements
 system.iocache.tagsinuse                     1.340325                       # Cycle average of tags in use
@@ -155,58 +174,41 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     41701                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              1750545944000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 1.340325                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.083770                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  173                       # number of ReadReq misses
+system.iocache.occ_blocks::tsunami.ide       1.340325                       # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide      0.083770                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.083770                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::tsunami.ide          173                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              173                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               41552                       # number of WriteReq misses
+system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           41552                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 41725                       # number of demand (read+write) misses
+system.iocache.demand_misses::tsunami.ide        41725                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             41725                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                41725                       # number of overall misses
+system.iocache.overall_misses::tsunami.ide        41725                       # number of overall misses
 system.iocache.overall_misses::total            41725                       # number of overall misses
-system.iocache.ReadReq_miss_latency          19940998                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       5722300806                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         5742241804                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        5742241804                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                173                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_latency::tsunami.ide     19940998                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total     19940998                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::tsunami.ide   5722300806                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   5722300806                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::tsunami.ide   5742241804                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   5742241804                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::tsunami.ide   5742241804                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   5742241804                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::tsunami.ide          173                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            173                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             41552                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::tsunami.ide        41552                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         41552                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               41725                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::tsunami.ide        41725                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           41725                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              41725                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::tsunami.ide        41725                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          41725                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 115265.884393                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 137714.208847                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 137621.133709                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 137621.133709                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::tsunami.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::tsunami.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::tsunami.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::tsunami.ide            1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::tsunami.ide 115265.884393                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 137714.208847                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::tsunami.ide 137621.133709                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::tsunami.ide 137621.133709                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      64604060                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                10476                       # number of cycles access was blocked
@@ -215,38 +217,32 @@ system.iocache.avg_blocked_cycles::no_mshrs  6166.863307                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       41512                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                173                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             41552                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               41725                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              41725                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     10944998                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3561447990                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    3572392988                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   3572392988                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 63265.884393                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 85710.627407                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 85617.567118                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           41512                       # number of writebacks
+system.iocache.writebacks::total                41512                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::tsunami.ide          173                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          173                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::tsunami.ide        41552                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        41552                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::tsunami.ide        41725                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        41725                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::tsunami.ide        41725                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        41725                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::tsunami.ide     10944998                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     10944998                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::tsunami.ide   3561447990                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3561447990                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::tsunami.ide   3572392988                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   3572392988                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::tsunami.ide   3572392988                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   3572392988                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::tsunami.ide            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 63265.884393                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 85710.627407                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 85617.567118                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 85617.567118                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.disk0.dma_read_full_pages                    0                       # Number of full page size DMA reads (not PRD).
 system.disk0.dma_read_bytes                      1024                       # Number of bytes transfered via DMA reads (not PRD).
@@ -295,7 +291,8 @@ system.cpu.itb.data_accesses                        0                       # DT
 system.cpu.numCycles                       3831097734                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         56137087                       # Number of instructions executed
+system.cpu.committedInsts                    56137087                       # Number of instructions committed
+system.cpu.committedOps                      56137087                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              52011214                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                 324192                       # Number of float alu accesses
 system.cpu.num_func_calls                     1482242                       # number of times a function call or return occured
@@ -434,51 +431,39 @@ system.cpu.icache.total_refs                 55220553                       # To
 system.cpu.icache.sampled_refs                 928194                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  59.492469                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            36307428000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            508.721464                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.993597                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0            55220553                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     508.721464                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.993597                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.993597                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     55220553                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        55220553                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0             55220553                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst      55220553                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total         55220553                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0            55220553                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst     55220553                       # number of overall hits
 system.cpu.icache.overall_hits::total        55220553                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            928354                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       928354                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        928354                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             928354                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       928354                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         928354                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            928354                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       928354                       # number of overall misses
 system.cpu.icache.overall_misses::total        928354                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    13616370500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     13616370500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    13616370500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0        56148907                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  13616370500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  13616370500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  13616370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  13616370500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  13616370500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  13616370500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     56148907                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     56148907                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0         56148907                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst     56148907                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total     56148907                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0        56148907                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     56148907                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     56148907                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.016534                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.016534                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.016534                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14667.218001                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14667.218001                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14667.218001                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.016534                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.016534                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.016534                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14667.218001                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14667.218001                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14667.218001                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -487,32 +472,26 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                       85                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          928354                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           928354                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          928354                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency  10830625500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency  10830625500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency  10830625500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.016534                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.016534                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.016534                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11666.482290                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11666.482290                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks           85                       # number of writebacks
+system.cpu.icache.writebacks::total                85                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       928354                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       928354                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       928354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       928354                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       928354                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       928354                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst  10830625500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total  10830625500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst  10830625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total  10830625500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst  10830625500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total  10830625500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.016534                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11666.482290                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1390115                       # number of replacements
 system.cpu.dcache.tagsinuse                511.984023                       # Cycle average of tags in use
@@ -520,77 +499,63 @@ system.cpu.dcache.total_refs                 14038335                       # To
 system.cpu.dcache.sampled_refs                1390627                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  10.094968                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               84029000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.984023                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999969                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0             7807536                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.984023                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999969                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999969                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data      7807536                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7807536                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            5848554                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      5848554                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        5848554                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::       183025                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       183025                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       183025                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         199203                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       199203                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       199203                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             13656090                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      13656090                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         13656090                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            13656090                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     13656090                       # number of overall hits
 system.cpu.dcache.overall_hits::total        13656090                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1069110                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1069110                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1069110                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           304335                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       304335                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       304335                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        17201                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        17201                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        17201                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0            1373445                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      1373445                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        1373445                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           1373445                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      1373445                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1373445                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    27121920500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    9228484000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency    245980000                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     36350404500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    36350404500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0         8876646                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  27121920500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  27121920500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9228484000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9228484000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    245980000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    245980000                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  36350404500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  36350404500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  36350404500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  36350404500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data      8876646                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total      8876646                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        6152889                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      6152889                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      6152889                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       200226                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       200226                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       200226                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       199203                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       199203                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       199203                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         15029535                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     15029535                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     15029535                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        15029535                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     15029535                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     15029535                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.120441                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.049462                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.085908                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.091383                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.091383                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 25368.690313                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30323.439631                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 14300.331376                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 26466.589124                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 26466.589124                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.120441                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.049462                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.085908                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.091383                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.091383                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 25368.690313                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30323.439631                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14300.331376                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26466.589124                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26466.589124                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -599,48 +564,47 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   826586                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1069110                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         304335                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses        17201                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1373445                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1373445                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  23914545000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8315479000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    194377000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  32230024000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  32230024000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency    862763000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1199607500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency   2062370500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.120441                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.049462                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.085908                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.091383                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.091383                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 22368.647754                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27323.439631                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 11300.331376                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 23466.555996                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       826586                       # number of writebacks
+system.cpu.dcache.writebacks::total            826586                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1069110                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1069110                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       304335                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        17201                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        17201                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1373445                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1373445                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1373445                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1373445                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  23914545000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  23914545000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8315479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8315479000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    194377000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    194377000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  32230024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  32230024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  32230024000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  32230024000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data    862763000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total    862763000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1199607500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1199607500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data   2062370500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total   2062370500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.120441                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.049462                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.085908                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.091383                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22368.647754                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27323.439631                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11300.331376                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23466.555996                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 04178bb329c2fcc5f32615605b4c18bf6fd11b8d..614929bfc24c29fbd7962b9ed47b13b7bdb90b44 100755 (executable)
@@ -1,18 +1,11 @@
-warn: Sockets disabled, not accepting vnc client connections
-warn: Sockets disabled, not accepting terminal connections
-warn: Sockets disabled, not accepting gdb connections
-warn: The clidr register always reports 0 caches.
-warn: clidr LoUIS field of 0b001 to match current ARM implementations.
-warn: The csselr register isn't implemented.
-warn: The ccsidr register isn't implemented and always reads as 0.
-warn:  instruction 'mcr bpiallis' unimplemented
-warn:  instruction 'mcr icialluis' unimplemented
-warn:  instruction 'mcr dccimvac' unimplemented
-warn:  instruction 'mcr dccmvau' unimplemented
-warn:  instruction 'mcr icimvau' unimplemented
-warn:  instruction 'mcr bpiallis' unimplemented
-warn: LCD dual screen mode not supported
-warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors
-warn:  instruction 'mcr icialluis' unimplemented
-warn:  instruction 'mcr icialluis' unimplemented
-hack: be nice to actually delete the event here
+Traceback (most recent call last):
+  File "<string>", line 1, in <module>
+  File "/tmp/gem5.ali/src/python/m5/main.py", line 357, in main
+    exec filecode in scope
+  File "tests/run.py", line 70, in <module>
+    execfile(joinpath(tests_root, 'configs', test_filename + '.py'))
+  File "tests/configs/realview-simple-atomic-dual.py", line 86, in <module>
+    system.l2c.num_cpus = 2
+  File "/tmp/gem5.ali/src/python/m5/SimObject.py", line 725, in __setattr__
+    % (self.__class__.__name__, attr)
+AttributeError: Class L2 has no parameter num_cpus
index 417579719ca88f6a1ac89e6dae427516abe4cb8c..d3606030fb3554d59092ba681ebd47c9f4e91bc4 100755 (executable)
@@ -1,12 +1,7 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:37:03
 gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic-dual
-Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
-info: Using bootloader at address 0x80000000
-info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2411694099500 because m5_exit instruction encountered
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
index 2ca0aa5cb9ebcc477360972c62c33f8cd014b104..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 100644 (file)
@@ -1,719 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-sim_seconds                                  2.411694                       # Number of seconds simulated
-sim_ticks                                2411694099500                       # Number of ticks simulated
-final_tick                               2411694099500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2039542                       # Simulator instruction rate (inst/s)
-host_tick_rate                            61821688958                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 378872                       # Number of bytes of host memory used
-host_seconds                                    39.01                       # Real time elapsed on the host
-sim_insts                                    79563488                       # Number of instructions simulated
-system.nvmem.bytes_read                            68                       # Number of bytes read from this memory
-system.nvmem.bytes_inst_read                       68                       # Number of instructions bytes read from this memory
-system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
-system.nvmem.num_reads                             17                       # Number of read requests responded to by this memory
-system.nvmem.num_writes                             0                       # Number of write requests responded to by this memory
-system.nvmem.num_other                              0                       # Number of other requests responded to by this memory
-system.nvmem.bw_read                               28                       # Total read bandwidth from this memory (bytes/s)
-system.nvmem.bw_inst_read                          28                       # Instruction read bandwidth from this memory (bytes/s)
-system.nvmem.bw_total                              28                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bytes_read                   123270308                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read                1011392                       # Number of instructions bytes read from this memory
-system.physmem.bytes_written                 10185232                       # Number of bytes written to this memory
-system.physmem.num_reads                     14146769                       # Number of read requests responded to by this memory
-system.physmem.num_writes                      869038                       # Number of write requests responded to by this memory
-system.physmem.num_other                            0                       # Number of other requests responded to by this memory
-system.physmem.bw_read                       51113575                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read                    419370                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write                       4223269                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total                      55336844                       # Total bandwidth to/from this memory (bytes/s)
-system.l2c.replacements                        127720                       # number of replacements
-system.l2c.tagsinuse                     25547.920863                       # Cycle average of tags in use
-system.l2c.total_refs                         1498989                       # Total number of references to valid blocks.
-system.l2c.sampled_refs                        156132                       # Sample count of references to valid blocks.
-system.l2c.avg_refs                          9.600780                       # Average number of references to valid blocks.
-system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  4404.089299                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                  6217.918720                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 14925.912843                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.067201                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.094878                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.227751                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                     706190                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     499815                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                      12920                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                1218925                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   580461                       # number of Writeback hits
-system.l2c.Writeback_hits::total               580461                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     776                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     523                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                1299                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                   147                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                   202                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::total               349                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                    64831                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    37797                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::total               102628                       # number of ReadExReq hits
-system.l2c.demand_hits::0                      771021                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      537612                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                       12920                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                 1321553                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                     771021                       # number of overall hits
-system.l2c.overall_hits::1                     537612                       # number of overall hits
-system.l2c.overall_hits::2                      12920                       # number of overall hits
-system.l2c.overall_hits::total                1321553                       # number of overall hits
-system.l2c.ReadReq_misses::0                    19675                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                    15224                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                       52                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                34951                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  6349                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  3492                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total              9841                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                 791                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                 531                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::total            1322                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                  99048                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  48785                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total             147833                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    118723                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     64009                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                        52                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                182784                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   118723                       # number of overall misses
-system.l2c.overall_misses::1                    64009                       # number of overall misses
-system.l2c.overall_misses::2                       52                       # number of overall misses
-system.l2c.overall_misses::total               182784                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                 725865                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 515039                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                  12972                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total            1253876                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               580461                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total           580461                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                7125                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                4015                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total           11140                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0               938                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               733                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::total          1671                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               163879                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                86582                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total           250461                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                  889744                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  601621                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                   12972                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total             1504337                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                 889744                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 601621                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                  12972                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total            1504337                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.027106                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.029559                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.004009                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.060673                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.891088                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.869738                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.843284                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.724420                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.604397                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.563454                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.133435                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.106394                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.004009                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.243838                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.133435                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.106394                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.004009                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.243838                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          111818                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
-system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
-system.cf0.dma_read_txs                             0                       # Number of DMA read transactions (not PRD).
-system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
-system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
-system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
-system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu0.dtb.read_hits                     9339288                       # DTB read hits
-system.cpu0.dtb.read_misses                      5153                       # DTB read misses
-system.cpu0.dtb.write_hits                    6907876                       # DTB write hits
-system.cpu0.dtb.write_misses                     1048                       # DTB write misses
-system.cpu0.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.dtb.flush_entries                    2247                       # Number of entries that have been flushed from TLB
-system.cpu0.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.dtb.prefetch_faults                   150                       # Number of TLB faults due to prefetch
-system.cpu0.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.dtb.perms_faults                      248                       # Number of TLB faults due to permissions restrictions
-system.cpu0.dtb.read_accesses                 9344441                       # DTB read accesses
-system.cpu0.dtb.write_accesses                6908924                       # DTB write accesses
-system.cpu0.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu0.dtb.hits                         16247164                       # DTB hits
-system.cpu0.dtb.misses                           6201                       # DTB misses
-system.cpu0.dtb.accesses                     16253365                       # DTB accesses
-system.cpu0.itb.inst_hits                    34822552                       # ITB inst hits
-system.cpu0.itb.inst_misses                      2978                       # ITB inst misses
-system.cpu0.itb.read_hits                           0                       # DTB read hits
-system.cpu0.itb.read_misses                         0                       # DTB read misses
-system.cpu0.itb.write_hits                          0                       # DTB write hits
-system.cpu0.itb.write_misses                        0                       # DTB write misses
-system.cpu0.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu0.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu0.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu0.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu0.itb.flush_entries                    1462                       # Number of entries that have been flushed from TLB
-system.cpu0.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu0.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu0.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu0.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu0.itb.read_accesses                       0                       # DTB read accesses
-system.cpu0.itb.write_accesses                      0                       # DTB write accesses
-system.cpu0.itb.inst_accesses                34825530                       # ITB inst accesses
-system.cpu0.itb.hits                         34822552                       # DTB hits
-system.cpu0.itb.misses                           2978                       # DTB misses
-system.cpu0.itb.accesses                     34825530                       # DTB accesses
-system.cpu0.numCycles                      4823340800                       # number of cpu cycles simulated
-system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.num_insts                        44975797                       # Number of instructions executed
-system.cpu0.num_int_alu_accesses             39858123                       # Number of integer alu accesses
-system.cpu0.num_fp_alu_accesses                  4945                       # Number of float alu accesses
-system.cpu0.num_func_calls                    1311755                       # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts      4494669                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                    39858123                       # number of integer instructions
-system.cpu0.num_fp_insts                         4945                       # number of float instructions
-system.cpu0.num_int_register_reads          202125744                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes          42204131                       # number of times the integer registers were written
-system.cpu0.num_fp_register_reads                3641                       # number of times the floating registers were read
-system.cpu0.num_fp_register_writes               1308                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     17030946                       # number of memory refs
-system.cpu0.num_load_insts                    9786549                       # Number of load instructions
-system.cpu0.num_store_insts                   7244397                       # Number of store instructions
-system.cpu0.num_idle_cycles              4777543068.852608                       # Number of idle cycles
-system.cpu0.num_busy_cycles              45797731.147393                       # Number of busy cycles
-system.cpu0.not_idle_fraction                0.009495                       # Percentage of non-idle cycles
-system.cpu0.idle_fraction                    0.990505                       # Percentage of idle cycles
-system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu0.kern.inst.quiesce                   59311                       # number of quiesce instructions executed
-system.cpu0.icache.replacements                504460                       # number of replacements
-system.cpu0.icache.tagsinuse               511.627588                       # Cycle average of tags in use
-system.cpu0.icache.total_refs                34319155                       # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs                504972                       # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs                 67.962491                       # Average number of references to valid blocks.
-system.cpu0.icache.warmup_cycle           64519524000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           511.627588                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.999273                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0           34319155                       # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total       34319155                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0            34319155                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total        34319155                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0           34319155                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.icache.overall_hits::total       34319155                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0           504973                       # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total       504973                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0            504973                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total        504973                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0           504973                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
-system.cpu0.icache.overall_misses::total       504973                       # number of overall misses
-system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0       34824128                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total     34824128                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0        34824128                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total     34824128                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0       34824128                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total     34824128                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.014501                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.014501                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.014501                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                   24728                       # number of writebacks
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.replacements                380107                       # number of replacements
-system.cpu0.dcache.tagsinuse               479.716402                       # Cycle average of tags in use
-system.cpu0.dcache.total_refs                14708286                       # Total number of references to valid blocks.
-system.cpu0.dcache.sampled_refs                380619                       # Sample count of references to valid blocks.
-system.cpu0.dcache.avg_refs                 38.643068                       # Average number of references to valid blocks.
-system.cpu0.dcache.warmup_cycle              22115000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           479.716402                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.936946                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            7803296                       # number of ReadReq hits
-system.cpu0.dcache.ReadReq_hits::total        7803296                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           6534059                       # number of WriteReq hits
-system.cpu0.dcache.WriteReq_hits::total       6534059                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       172314                       # number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_hits::total       172314                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::0        174866                       # number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_hits::total       174866                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0            14337355                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::total        14337355                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0           14337355                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu0.dcache.overall_hits::total       14337355                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0           237350                       # number of ReadReq misses
-system.cpu0.dcache.ReadReq_misses::total       237350                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0          183580                       # number of WriteReq misses
-system.cpu0.dcache.WriteReq_misses::total       183580                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0         9878                       # number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_misses::total         9878                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0         7293                       # number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_misses::total         7293                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0            420930                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::total        420930                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0           420930                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu0.dcache.overall_misses::total       420930                       # number of overall misses
-system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        8040646                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_accesses::total      8040646                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::0       6717639                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::total      6717639                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       182192                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::total       182192                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       182159                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::total       182159                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        14758285                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::total     14758285                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       14758285                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::total     14758285                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.029519                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.027328                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.054218                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.040036                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.028522                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.028522                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu0.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  339627                       # number of writebacks
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
-system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
-system.cpu1.dtb.read_hits                     6258230                       # DTB read hits
-system.cpu1.dtb.read_misses                      2159                       # DTB read misses
-system.cpu1.dtb.write_hits                    4713962                       # DTB write hits
-system.cpu1.dtb.write_misses                     1181                       # DTB write misses
-system.cpu1.dtb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.dtb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.dtb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.dtb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.dtb.flush_entries                    1498                       # Number of entries that have been flushed from TLB
-system.cpu1.dtb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.dtb.prefetch_faults                    92                       # Number of TLB faults due to prefetch
-system.cpu1.dtb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.dtb.perms_faults                      204                       # Number of TLB faults due to permissions restrictions
-system.cpu1.dtb.read_accesses                 6260389                       # DTB read accesses
-system.cpu1.dtb.write_accesses                4715143                       # DTB write accesses
-system.cpu1.dtb.inst_accesses                       0                       # ITB inst accesses
-system.cpu1.dtb.hits                         10972192                       # DTB hits
-system.cpu1.dtb.misses                           3340                       # DTB misses
-system.cpu1.dtb.accesses                     10975532                       # DTB accesses
-system.cpu1.itb.inst_hits                    27739434                       # ITB inst hits
-system.cpu1.itb.inst_misses                      1388                       # ITB inst misses
-system.cpu1.itb.read_hits                           0                       # DTB read hits
-system.cpu1.itb.read_misses                         0                       # DTB read misses
-system.cpu1.itb.write_hits                          0                       # DTB write hits
-system.cpu1.itb.write_misses                        0                       # DTB write misses
-system.cpu1.itb.flush_tlb                           4                       # Number of times complete TLB was flushed
-system.cpu1.itb.flush_tlb_mva                       0                       # Number of times TLB was flushed by MVA
-system.cpu1.itb.flush_tlb_mva_asid               1439                       # Number of times TLB was flushed by MVA & ASID
-system.cpu1.itb.flush_tlb_asid                     63                       # Number of times TLB was flushed by ASID
-system.cpu1.itb.flush_entries                    1342                       # Number of entries that have been flushed from TLB
-system.cpu1.itb.align_faults                        0                       # Number of TLB faults due to alignment restrictions
-system.cpu1.itb.prefetch_faults                     0                       # Number of TLB faults due to prefetch
-system.cpu1.itb.domain_faults                       0                       # Number of TLB faults due to domain restrictions
-system.cpu1.itb.perms_faults                        0                       # Number of TLB faults due to permissions restrictions
-system.cpu1.itb.read_accesses                       0                       # DTB read accesses
-system.cpu1.itb.write_accesses                      0                       # DTB write accesses
-system.cpu1.itb.inst_accesses                27740822                       # ITB inst accesses
-system.cpu1.itb.hits                         27739434                       # DTB hits
-system.cpu1.itb.misses                           1388                       # DTB misses
-system.cpu1.itb.accesses                     27740822                       # DTB accesses
-system.cpu1.numCycles                      4822838236                       # number of cpu cycles simulated
-system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
-system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.num_insts                        34587691                       # Number of instructions executed
-system.cpu1.num_int_alu_accesses             30998246                       # Number of integer alu accesses
-system.cpu1.num_fp_alu_accesses                  5772                       # Number of float alu accesses
-system.cpu1.num_func_calls                     758024                       # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts      3375080                       # number of instructions that are conditional controls
-system.cpu1.num_int_insts                    30998246                       # number of integer instructions
-system.cpu1.num_fp_insts                         5772                       # number of float instructions
-system.cpu1.num_int_register_reads          156835040                       # number of times the integer registers were read
-system.cpu1.num_int_register_writes          33469179                       # number of times the integer registers were written
-system.cpu1.num_fp_register_reads                3980                       # number of times the floating registers were read
-system.cpu1.num_fp_register_writes               1792                       # number of times the floating registers were written
-system.cpu1.num_mem_refs                     11415835                       # number of memory refs
-system.cpu1.num_load_insts                    6478994                       # Number of load instructions
-system.cpu1.num_store_insts                   4936841                       # Number of store instructions
-system.cpu1.num_idle_cycles              4787960178.177661                       # Number of idle cycles
-system.cpu1.num_busy_cycles              34878057.822339                       # Number of busy cycles
-system.cpu1.not_idle_fraction                0.007232                       # Percentage of non-idle cycles
-system.cpu1.idle_fraction                    0.992768                       # Percentage of idle cycles
-system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
-system.cpu1.kern.inst.quiesce                   33011                       # number of quiesce instructions executed
-system.cpu1.icache.replacements                374406                       # number of replacements
-system.cpu1.icache.tagsinuse               498.143079                       # Cycle average of tags in use
-system.cpu1.icache.total_refs                27365572                       # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs                374918                       # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs                 72.990819                       # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle           69956143000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           498.143079                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.972936                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0           27365572                       # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total       27365572                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0            27365572                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total        27365572                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0           27365572                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.icache.overall_hits::total       27365572                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0           374920                       # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total       374920                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0            374920                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total        374920                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0           374920                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
-system.cpu1.icache.overall_misses::total       374920                       # number of overall misses
-system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0       27740492                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total     27740492                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0        27740492                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::total     27740492                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0       27740492                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::total     27740492                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.013515                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.013515                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.013515                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.icache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                   13905                       # number of writebacks
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.replacements                247434                       # number of replacements
-system.cpu1.dcache.tagsinuse               444.903488                       # Cycle average of tags in use
-system.cpu1.dcache.total_refs                 9876826                       # Total number of references to valid blocks.
-system.cpu1.dcache.sampled_refs                247805                       # Sample count of references to valid blocks.
-system.cpu1.dcache.avg_refs                 39.857251                       # Average number of references to valid blocks.
-system.cpu1.dcache.warmup_cycle           69253206000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           444.903488                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.868952                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            5955973                       # number of ReadReq hits
-system.cpu1.dcache.ReadReq_hits::total        5955973                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0           3777038                       # number of WriteReq hits
-system.cpu1.dcache.WriteReq_hits::total       3777038                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0        59593                       # number of LoadLockedReq hits
-system.cpu1.dcache.LoadLockedReq_hits::total        59593                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::0         60090                       # number of StoreCondReq hits
-system.cpu1.dcache.StoreCondReq_hits::total        60090                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0             9733011                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::total         9733011                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0            9733011                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
-system.cpu1.dcache.overall_hits::total        9733011                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0           165799                       # number of ReadReq misses
-system.cpu1.dcache.ReadReq_misses::total       165799                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0          111467                       # number of WriteReq misses
-system.cpu1.dcache.WriteReq_misses::total       111467                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0        10725                       # number of LoadLockedReq misses
-system.cpu1.dcache.LoadLockedReq_misses::total        10725                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0        10198                       # number of StoreCondReq misses
-system.cpu1.dcache.StoreCondReq_misses::total        10198                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0            277266                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::total        277266                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0           277266                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
-system.cpu1.dcache.overall_misses::total       277266                       # number of overall misses
-system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        6121772                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.ReadReq_accesses::total      6121772                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::0       3888505                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::total      3888505                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0        70318                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::total        70318                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0        70288                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::total        70288                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0        10010277                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::total     10010277                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0       10010277                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::total     10010277                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.027083                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.028666                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.152521                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.145089                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.027698                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.027698                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
-system.cpu1.dcache.blocked::no_targets              0                       # number of cycles access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
-system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                  202201                       # number of writebacks
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.iocache.replacements                         0                       # number of replacements
-system.iocache.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
-system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
-system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
-system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
-system.iocache.blocked::no_targets                  0                       # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs     no_value                       # average number of cycles each access was blocked
-system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
-system.iocache.fast_writes                          0                       # number of fast writes performed
-system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                           0                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
-system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
-
----------- End Simulation Statistics   ----------
index 5b5bd916405b2aa9b2b3394ce603f9a6c81b25d5..5cb72c285f53a2a99ed711d9e8978b257d6aa1d3 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
@@ -93,6 +93,7 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
+workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
@@ -107,20 +108,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -152,20 +146,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -217,20 +204,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -249,20 +229,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -288,7 +261,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.realview
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -330,7 +302,6 @@ system=system
 type=A9SCU
 pio_addr=520093696
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.membus.port[5]
 
@@ -340,7 +311,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268451840
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[24]
 
@@ -410,7 +380,6 @@ max_backoff_delay=10000000
 min_backoff_delay=4000
 pio_addr=268566528
 pio_latency=10000
-platform=system.realview
 system=system
 vnc=system.vncserver
 dma=system.iobus.port[6]
@@ -422,7 +391,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268632064
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[12]
 
@@ -432,7 +400,6 @@ fake_mem=true
 pio_addr=1073741824
 pio_latency=1000
 pio_size=536870912
-platform=system.realview
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -461,7 +428,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268513280
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[19]
 
@@ -471,7 +437,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268517376
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[20]
 
@@ -481,7 +446,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268521472
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[21]
 
@@ -494,7 +458,6 @@ int_num=52
 is_mouse=false
 pio_addr=268460032
 pio_latency=1000
-platform=system.realview
 system=system
 vnc=system.vncserver
 pio=system.iobus.port[7]
@@ -508,7 +471,6 @@ int_num=53
 is_mouse=true
 pio_addr=268464128
 pio_latency=1000
-platform=system.realview
 system=system
 vnc=system.vncserver
 pio=system.iobus.port[8]
@@ -519,7 +481,6 @@ fake_mem=false
 pio_addr=520101888
 pio_latency=1000
 pio_size=4095
-platform=system.realview
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -538,7 +499,6 @@ int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.membus.port[6]
 
@@ -548,7 +508,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268455936
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[25]
 
@@ -557,7 +516,6 @@ type=RealViewCtrl
 idreg=0
 pio_addr=268435456
 pio_latency=1000
-platform=system.realview
 proc_id0=201326592
 proc_id1=201327138
 system=system
@@ -569,7 +527,6 @@ amba_id=266289
 ignore_access=false
 pio_addr=268529664
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[26]
 
@@ -579,7 +536,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268492800
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[23]
 
@@ -589,7 +545,6 @@ amba_id=0
 ignore_access=false
 pio_addr=269357056
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[16]
 
@@ -599,7 +554,6 @@ amba_id=0
 ignore_access=true
 pio_addr=268439552
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[17]
 
@@ -609,7 +563,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268488704
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[22]
 
@@ -623,7 +576,6 @@ int_num0=36
 int_num1=36
 pio_addr=268505088
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[3]
 
@@ -637,7 +589,6 @@ int_num0=37
 int_num1=37
 pio_addr=268509184
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[4]
 
@@ -660,7 +611,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268476416
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[13]
 
@@ -670,7 +620,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268480512
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[14]
 
@@ -680,7 +629,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268484608
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[15]
 
@@ -690,7 +638,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268500992
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[18]
 
index e355498ce23174d172130bf61cdfa9278690d6e1..31542346f29ee4b1d1593e74a2b81ed7fa63fd79 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:24:55
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:36:22
 gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
index e3050fa31c13c03266a5be72bf8e57486890845b..d895bb1201866b5d957fc6f69e13f86e3d2558ed 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.332317                       # Nu
 sim_ticks                                2332316587000                       # Number of ticks simulated
 final_tick                               2332316587000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2072038                       # Simulator instruction rate (inst/s)
-host_tick_rate                            63144661085                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379208                       # Number of bytes of host memory used
-host_seconds                                    36.94                       # Real time elapsed on the host
-sim_insts                                    76532931                       # Number of instructions simulated
+host_inst_rate                                2011652                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2597875                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            79169370264                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 376316                       # Number of bytes of host memory used
+host_seconds                                    29.46                       # Real time elapsed on the host
+sim_insts                                    59262876                       # Number of instructions simulated
+sim_ops                                      76532931                       # Number of ops (including micro ops) simulated
 system.nvmem.bytes_read                            20                       # Number of bytes read from this memory
 system.nvmem.bytes_inst_read                       20                       # Number of instructions bytes read from this memory
 system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
@@ -34,72 +36,92 @@ system.l2c.total_refs                         1520830                       # To
 system.l2c.sampled_refs                        146847                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         10.356562                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 10591.091336                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 13649.297042                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.161607                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.208272                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1188216                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                      10669                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        13639.466210                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        7.864412                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        1.966419                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           5246.411267                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           5344.680069                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.208122                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000120                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000030                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.080054                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.081553                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.369879                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          7522                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          3147                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              831710                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              356506                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1198885                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   604613                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          604613                       # number of Writeback hits
 system.l2c.Writeback_hits::total               604613                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      26                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   105791                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            105791                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               105791                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1294007                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                       10669                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker           7522                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           3147                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               831710                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               462297                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1304676                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1294007                       # number of overall hits
-system.l2c.overall_hits::1                      10669                       # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker          7522                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          3147                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              831710                       # number of overall hits
+system.l2c.overall_hits::cpu.data              462297                       # number of overall hits
 system.l2c.overall_hits::total                1304676                       # number of overall hits
-system.l2c.ReadReq_misses::0                    31716                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       27                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker           19                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker            8                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             14294                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             17422                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                31743                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  2911                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2911                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2911                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 141169                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          141169                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             141169                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    172885                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        27                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker           19                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker            8                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              14294                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             158591                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                172912                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   172885                       # number of overall misses
-system.l2c.overall_misses::1                       27                       # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker           19                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker            8                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             14294                       # number of overall misses
+system.l2c.overall_misses::cpu.data            158591                       # number of overall misses
 system.l2c.overall_misses::total               172912                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                1219932                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                  10696                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.dtb.walker         7541                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         3155                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          846004                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          373928                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            1230628                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               604613                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       604613                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           604613                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2937                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2937                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            2937                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               246960                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        246960                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           246960                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 1466892                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                   10696                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker         7541                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         3155                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           846004                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           620888                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             1477588                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                1466892                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                  10696                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         7541                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         3155                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          846004                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          620888                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            1477588                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.025998                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.002524                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.028522                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.991147                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.571627                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.117858                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.002524                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.120382                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.117858                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.002524                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.120382                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.002520                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.002536                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.016896                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.046592                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.991147                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.571627                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.002520                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.002536                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.016896                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.255426                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.002520                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.002536                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.016896                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.255426                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -108,26 +130,8 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          102531                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              102531                       # number of writebacks
+system.l2c.writebacks::total                   102531                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -180,7 +184,8 @@ system.cpu.itb.accesses                      60278360                       # DT
 system.cpu.numCycles                       4664556206                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         76532931                       # Number of instructions executed
+system.cpu.committedInsts                    59262876                       # Number of instructions committed
+system.cpu.committedOps                      76532931                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              68161177                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
 system.cpu.num_func_calls                     1971944                       # number of times a function call or return occured
@@ -206,47 +211,30 @@ system.cpu.icache.total_refs                 59429083                       # To
 system.cpu.icache.sampled_refs                 847566                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  70.117351                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle             5705452000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            511.678552                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0            59429083                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     511.678552                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.999372                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.999372                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     59429083                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        59429083                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0             59429083                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst      59429083                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total         59429083                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0            59429083                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst     59429083                       # number of overall hits
 system.cpu.icache.overall_hits::total        59429083                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            847566                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       847566                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        847566                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             847566                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       847566                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         847566                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            847566                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       847566                       # number of overall misses
 system.cpu.icache.overall_misses::total        847566                       # number of overall misses
-system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0        60276649                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst     60276649                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     60276649                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0         60276649                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst     60276649                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total     60276649                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0        60276649                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60276649                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60276649                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.014061                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.014061                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.014061                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014061                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014061                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014061                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -255,26 +243,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                    44721                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks        44721                       # number of writebacks
+system.cpu.icache.writebacks::total             44721                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 622134                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997030                       # Cycle average of tags in use
@@ -282,65 +252,48 @@ system.cpu.dcache.total_refs                 23580069                       # To
 system.cpu.dcache.sampled_refs                 622646                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  37.870747                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               21763000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.997030                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            13150366                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.997030                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     13150366                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13150366                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            9943631                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9943631                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        9943631                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::       235999                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       235999                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       235999                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         247136                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247136                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       247136                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             23093997                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      23093997                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         23093997                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            23093997                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     23093997                       # number of overall hits
 system.cpu.dcache.overall_hits::total        23093997                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0            364548                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data       364548                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        364548                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           249897                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       249897                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       249897                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        11138                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11138                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        11138                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0             614445                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data       614445                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total         614445                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0            614445                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data       614445                       # number of overall misses
 system.cpu.dcache.overall_misses::total        614445                       # number of overall misses
-system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13514914                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     13514914                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     13514914                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0       10193528                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10193528                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     10193528                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       247137                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247137                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       247137                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       247136                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247136                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       247136                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         23708442                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     23708442                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     23708442                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        23708442                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23708442                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     23708442                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.026974                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.024515                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.045068                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.025917                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.025917                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026974                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024515                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.045068                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.025917                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.025917                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -349,26 +302,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   559892                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       559892                       # number of writebacks
+system.cpu.dcache.writebacks::total            559892                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -376,38 +311,6 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -416,26 +319,6 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                           0                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 82d6c82a5848cffd97db942f7f3b3dc7303fe7d8..73f5e0c763c4afb8bb6c2658d79dbacd35afb409 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
@@ -19,7 +19,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
-memories=system.physmem system.nvmem
+memories=system.nvmem system.physmem
 midr_regval=890224640
 num_work_ids=16
 physmem=system.physmem
@@ -90,6 +90,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu0.tracer
+workload=
 dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
@@ -104,20 +105,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -149,20 +143,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -214,6 +201,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu1.tracer
+workload=
 dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
@@ -228,20 +216,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -273,20 +254,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -338,20 +312,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -370,20 +337,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=2
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -409,7 +369,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.realview
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -451,7 +410,6 @@ system=system
 type=A9SCU
 pio_addr=520093696
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.membus.port[5]
 
@@ -461,7 +419,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268451840
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[24]
 
@@ -531,7 +488,6 @@ max_backoff_delay=10000000
 min_backoff_delay=4000
 pio_addr=268566528
 pio_latency=10000
-platform=system.realview
 system=system
 vnc=system.vncserver
 dma=system.iobus.port[6]
@@ -543,7 +499,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268632064
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[12]
 
@@ -553,7 +508,6 @@ fake_mem=true
 pio_addr=1073741824
 pio_latency=1000
 pio_size=536870912
-platform=system.realview
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -582,7 +536,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268513280
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[19]
 
@@ -592,7 +545,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268517376
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[20]
 
@@ -602,7 +554,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268521472
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[21]
 
@@ -615,7 +566,6 @@ int_num=52
 is_mouse=false
 pio_addr=268460032
 pio_latency=1000
-platform=system.realview
 system=system
 vnc=system.vncserver
 pio=system.iobus.port[7]
@@ -629,7 +579,6 @@ int_num=53
 is_mouse=true
 pio_addr=268464128
 pio_latency=1000
-platform=system.realview
 system=system
 vnc=system.vncserver
 pio=system.iobus.port[8]
@@ -640,7 +589,6 @@ fake_mem=false
 pio_addr=520101888
 pio_latency=1000
 pio_size=4095
-platform=system.realview
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -659,7 +607,6 @@ int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.membus.port[6]
 
@@ -669,7 +616,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268455936
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[25]
 
@@ -678,7 +624,6 @@ type=RealViewCtrl
 idreg=0
 pio_addr=268435456
 pio_latency=1000
-platform=system.realview
 proc_id0=201326592
 proc_id1=201327138
 system=system
@@ -690,7 +635,6 @@ amba_id=266289
 ignore_access=false
 pio_addr=268529664
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[26]
 
@@ -700,7 +644,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268492800
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[23]
 
@@ -710,7 +653,6 @@ amba_id=0
 ignore_access=false
 pio_addr=269357056
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[16]
 
@@ -720,7 +662,6 @@ amba_id=0
 ignore_access=true
 pio_addr=268439552
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[17]
 
@@ -730,7 +671,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268488704
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[22]
 
@@ -744,7 +684,6 @@ int_num0=36
 int_num1=36
 pio_addr=268505088
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[3]
 
@@ -758,7 +697,6 @@ int_num0=37
 int_num1=37
 pio_addr=268509184
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[4]
 
@@ -781,7 +719,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268476416
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[13]
 
@@ -791,7 +728,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268480512
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[14]
 
@@ -801,7 +737,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268484608
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[15]
 
@@ -811,7 +746,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268500992
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[18]
 
index 2f40c0e53a2d5269ca6761994869032d480fb442..83064ae1d8e08d3870789d54f9306b76bde99aaf 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:38:22
 gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing-dual
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
index 6f6f084e37b915fc2f0f46ff1ef8d1ae495c7dea..46b5d4b73b37407cd9db1c6c7752bc36cc900c86 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.669611                       # Nu
 sim_ticks                                2669611225000                       # Number of ticks simulated
 final_tick                               2669611225000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 842154                       # Simulator instruction rate (inst/s)
-host_tick_rate                            28671225175                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380676                       # Number of bytes of host memory used
-host_seconds                                    93.11                       # Real time elapsed on the host
-sim_insts                                    78413959                       # Number of instructions simulated
+host_inst_rate                                 868396                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1110924                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            37821516206                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 377896                       # Number of bytes of host memory used
+host_seconds                                    70.58                       # Real time elapsed on the host
+sim_insts                                    61295262                       # Number of instructions simulated
+sim_ops                                      78413959                       # Number of ops (including micro ops) simulated
 system.nvmem.bytes_read                            68                       # Number of bytes read from this memory
 system.nvmem.bytes_inst_read                       68                       # Number of instructions bytes read from this memory
 system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
@@ -34,127 +36,233 @@ system.l2c.total_refs                         1540412                       # To
 system.l2c.sampled_refs                        157158                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          9.801677                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  6351.465954                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                  4614.904109                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                 15206.143377                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.096916                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.070418                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.232027                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                     562859                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                     656143                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                      11798                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        15197.869059                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.dtb.walker       8.069070                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.itb.walker       0.114155                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst          2680.486069                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data          3670.979885                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.dtb.walker       0.091092                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.itb.walker       0.000002                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst          2441.904066                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data          2173.000042                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.231901                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.dtb.walker      0.000123                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.itb.walker      0.000002                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.040901                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.056015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.dtb.walker      0.000001                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.itb.walker      0.000000                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.037260                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.033157                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.399361                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.dtb.walker         4237                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.itb.walker         1502                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.inst             371106                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data             191753                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.dtb.walker         4185                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.itb.walker         1874                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst             499097                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data             157046                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1230800                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   589400                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          589400                       # number of Writeback hits
 system.l2c.Writeback_hits::total               589400                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                    1143                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     692                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data            1143                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1.data             692                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                1835                       # number of UpgradeReq hits
-system.l2c.SCUpgradeReq_hits::0                   168                       # number of SCUpgradeReq hits
-system.l2c.SCUpgradeReq_hits::1                   186                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu0.data           168                       # number of SCUpgradeReq hits
+system.l2c.SCUpgradeReq_hits::cpu1.data           186                       # number of SCUpgradeReq hits
 system.l2c.SCUpgradeReq_hits::total               354                       # number of SCUpgradeReq hits
-system.l2c.ReadExReq_hits::0                    42506                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                    58554                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0.data            42506                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1.data            58554                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               101060                       # number of ReadExReq hits
-system.l2c.demand_hits::0                      605365                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                      714697                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                       11798                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.dtb.walker          4237                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.itb.walker          1502                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst              371106                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data              234259                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.dtb.walker          4185                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.itb.walker          1874                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst              499097                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data              215600                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1331860                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                     605365                       # number of overall hits
-system.l2c.overall_hits::1                     714697                       # number of overall hits
-system.l2c.overall_hits::2                      11798                       # number of overall hits
+system.l2c.overall_hits::cpu0.dtb.walker         4237                       # number of overall hits
+system.l2c.overall_hits::cpu0.itb.walker         1502                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst             371106                       # number of overall hits
+system.l2c.overall_hits::cpu0.data             234259                       # number of overall hits
+system.l2c.overall_hits::cpu1.dtb.walker         4185                       # number of overall hits
+system.l2c.overall_hits::cpu1.itb.walker         1874                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst             499097                       # number of overall hits
+system.l2c.overall_hits::cpu1.data             215600                       # number of overall hits
 system.l2c.overall_hits::total                1331860                       # number of overall hits
-system.l2c.ReadReq_misses::0                    18655                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                    16034                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                       50                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.dtb.walker           24                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.itb.walker           14                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst             7728                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data            10927                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.dtb.walker            8                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.itb.walker            4                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst             7533                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data             8501                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                34739                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  3515                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  5223                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data          3515                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data          5223                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              8738                       # number of UpgradeReq misses
-system.l2c.SCUpgradeReq_misses::0                 546                       # number of SCUpgradeReq misses
-system.l2c.SCUpgradeReq_misses::1                 614                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu0.data          546                       # number of SCUpgradeReq misses
+system.l2c.SCUpgradeReq_misses::cpu1.data          614                       # number of SCUpgradeReq misses
 system.l2c.SCUpgradeReq_misses::total            1160                       # number of SCUpgradeReq misses
-system.l2c.ReadExReq_misses::0                  97324                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                  51524                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data          97324                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data          51524                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             148848                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    115979                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     67558                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                        50                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.dtb.walker           24                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.itb.walker           14                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst              7728                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data            108251                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.dtb.walker            8                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.itb.walker            4                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst              7533                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data             60025                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                183587                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   115979                       # number of overall misses
-system.l2c.overall_misses::1                    67558                       # number of overall misses
-system.l2c.overall_misses::2                       50                       # number of overall misses
+system.l2c.overall_misses::cpu0.dtb.walker           24                       # number of overall misses
+system.l2c.overall_misses::cpu0.itb.walker           14                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst             7728                       # number of overall misses
+system.l2c.overall_misses::cpu0.data           108251                       # number of overall misses
+system.l2c.overall_misses::cpu1.dtb.walker            8                       # number of overall misses
+system.l2c.overall_misses::cpu1.itb.walker            4                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst             7533                       # number of overall misses
+system.l2c.overall_misses::cpu1.data            60025                       # number of overall misses
 system.l2c.overall_misses::total               183587                       # number of overall misses
-system.l2c.ReadReq_miss_latency            1812504500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           56471000                       # number of UpgradeReq miss cycles
-system.l2c.SCUpgradeReq_miss_latency          6300000                       # number of SCUpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7751543000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             9564047500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            9564047500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                 581514                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                 672177                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                  11848                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0.dtb.walker      1250500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.itb.walker       728500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.inst    402353500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data    568569000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.dtb.walker       416000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.itb.walker       208000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst    393731000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data    445248000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1812504500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0.data     25676000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data     30795000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     56471000                       # number of UpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu0.data      1664000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::cpu1.data      4636000                       # number of SCUpgradeReq miss cycles
+system.l2c.SCUpgradeReq_miss_latency::total      6300000                       # number of SCUpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data   5064009000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data   2687534000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7751543000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.dtb.walker      1250500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.itb.walker       728500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.inst    402353500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data   5632578000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.dtb.walker       416000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.itb.walker       208000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst    393731000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data   3132782000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      9564047500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.dtb.walker      1250500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.itb.walker       728500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.inst    402353500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data   5632578000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.dtb.walker       416000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.itb.walker       208000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst    393731000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data   3132782000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     9564047500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.dtb.walker         4261                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.itb.walker         1516                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst         378834                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data         202680                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.dtb.walker         4193                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.itb.walker         1878                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst         506630                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data         165547                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            1265539                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               589400                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       589400                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           589400                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                4658                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                5915                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data         4658                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data         5915                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total           10573                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::0               714                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.SCUpgradeReq_accesses::1               800                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu0.data          714                       # number of SCUpgradeReq accesses(hits+misses)
+system.l2c.SCUpgradeReq_accesses::cpu1.data          800                       # number of SCUpgradeReq accesses(hits+misses)
 system.l2c.SCUpgradeReq_accesses::total          1514                       # number of SCUpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               139830                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1               110078                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data       139830                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data       110078                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           249908                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                  721344                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                  782255                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                   11848                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.dtb.walker         4261                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.itb.walker         1516                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst          378834                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data          342510                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.dtb.walker         4193                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.itb.walker         1878                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst          506630                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data          275625                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             1515447                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                 721344                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                 782255                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                  11848                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.dtb.walker         4261                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.itb.walker         1516                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst         378834                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data         342510                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.dtb.walker         4193                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.itb.walker         1878                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst         506630                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data         275625                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            1515447                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.032080                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.023854                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.004220                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.060154                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.754616                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.883009                       # miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::0         0.764706                       # miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_miss_rate::1         0.767500                       # miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.696017                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.468068                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.160782                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.086363                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.004220                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.251365                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.160782                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.086363                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.004220                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.251365                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   97159.179845                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   113041.318448                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2       36250090                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 36460290.498293                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 16065.718350                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 10811.985449                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::0 11538.461538                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::1 10260.586319                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::2          inf                       # average SCUpgradeReq miss latency
-system.l2c.SCUpgradeReq_avg_miss_latency::total          inf                       # average SCUpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 79646.777773                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 150445.287633                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    82463.614103                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    141567.949022                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2       191280950                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 191504981.563124                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   82463.614103                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   141567.949022                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2      191280950                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 191504981.563124                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.dtb.walker     0.005632                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.itb.walker     0.009235                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.020399                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.053913                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.itb.walker     0.002130                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.014869                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.051351                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.754616                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data     0.883009                       # miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu0.data     0.764706                       # miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_miss_rate::cpu1.data     0.767500                       # miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data     0.696017                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data     0.468068                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.dtb.walker     0.005632                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.itb.walker     0.009235                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.020399                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.316052                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.itb.walker     0.002130                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.014869                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.217778                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.dtb.walker     0.005632                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.itb.walker     0.009235                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.020399                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.316052                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.dtb.walker     0.001908                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.itb.walker     0.002130                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.014869                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.217778                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52104.166667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 52035.714286                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52064.376294                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data 52033.403496                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52267.489712                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data 52375.955770                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0.data  7304.694168                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  5896.036760                       # average UpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data  3047.619048                       # average SCUpgradeReq miss latency
+system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data  7550.488599                       # average SCUpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52032.479142                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52160.818259                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52104.166667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.itb.walker 52035.714286                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52064.376294                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52032.572447                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.dtb.walker        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 52267.489712                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52191.286964                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52104.166667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.itb.walker 52035.714286                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52064.376294                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52032.572447                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.dtb.walker        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.itb.walker        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 52267.489712                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52191.286964                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -163,61 +271,172 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          111955                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                        9                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                         9                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        9                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  34730                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                8738                       # number of UpgradeReq MSHR misses
-system.l2c.SCUpgradeReq_mshr_misses              1160                       # number of SCUpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               148848                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  183578                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 183578                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       1395310000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     350593500                       # number of UpgradeReq MSHR miss cycles
-system.l2c.SCUpgradeReq_mshr_miss_latency     46546000                       # number of SCUpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5965367000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        7360677000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       7360677000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131926671000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency  31372379500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 163299050500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.059723                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         0.051668                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         2.931296                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     3.042688                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      1.875912                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      1.477261                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::0     1.624650                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::1     1.450000                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::2          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.SCUpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for SCUpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       1.064493                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       1.352205                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.254494                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          0.234678                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2         15.494429                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total     15.983602                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.254494                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         0.234678                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2        15.494429                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total    15.983602                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40175.928592                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40122.854200                       # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency 40125.862069                       # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40076.903956                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40095.637822                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40095.637822                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              111955                       # number of writebacks
+system.l2c.writebacks::total                   111955                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu0.data             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 9                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu0.data              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  9                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu0.data             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 9                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker           24                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.itb.walker           14                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.inst         7727                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data        10919                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker            8                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.itb.walker            4                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst         7533                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data         8501                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           34730                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data         3515                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data         5223                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         8738                       # number of UpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu0.data          546                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::cpu1.data          614                       # number of SCUpgradeReq MSHR misses
+system.l2c.SCUpgradeReq_mshr_misses::total         1160                       # number of SCUpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data        97324                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data        51524                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        148848                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.dtb.walker           24                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.itb.walker           14                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst         7727                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data       108243                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.dtb.walker            8                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.itb.walker            4                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst         7533                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data        60025                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           183578                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.dtb.walker           24                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.itb.walker           14                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst         7727                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data       108243                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.dtb.walker            8                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.itb.walker            4                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst         7533                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data        60025                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          183578                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker       962000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker       560000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst    309600000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data    437141000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker       320000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker       160000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst    303331000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data    343236000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1395310000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data    140869500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data    209724000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    350593500                       # number of UpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data     21887000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data     24659000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.SCUpgradeReq_mshr_miss_latency::total     46546000                       # number of SCUpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data   3896121000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data   2069246000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5965367000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker       962000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.itb.walker       560000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst    309600000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data   4333262000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker       320000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.itb.walker       160000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst    303331000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data   2412482000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   7360677000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker       962000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.itb.walker       560000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst    309600000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data   4333262000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker       320000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.itb.walker       160000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst    303331000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data   2412482000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   7360677000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data   8189961000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 123467229000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131926671000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data  30961750000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data    410629500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31372379500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.inst    265520000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0.data  39151711000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.inst      3961000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1.data 123877858500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 163299050500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker     0.005632                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker     0.009235                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.020397                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.053873                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker     0.002130                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.014869                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.051351                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.754616                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data     0.883009                       # mshr miss rate for UpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data     0.764706                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data     0.767500                       # mshr miss rate for SCUpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data     0.696017                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data     0.468068                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker     0.005632                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.itb.walker     0.009235                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.020397                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.316029                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.itb.walker     0.002130                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.014869                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.217778                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker     0.005632                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.itb.walker     0.009235                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.020397                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.316029                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker     0.001908                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.itb.walker     0.002130                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.014869                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.217778                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40067.296493                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40034.893305                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40266.958715                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40375.955770                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40076.671408                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40153.934520                       # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40086.080586                       # average SCUpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40161.237785                       # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40032.479142                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40160.818259                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40067.296493                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40032.722670                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40266.958715                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40191.286964                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40083.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40067.296493                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40032.722670                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40266.958715                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40191.286964                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -270,7 +489,8 @@ system.cpu0.itb.accesses                     35749115                       # DT
 system.cpu0.numCycles                      5337805216                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.num_insts                        43969024                       # Number of instructions executed
+system.cpu0.committedInsts                   35373502                       # Number of instructions committed
+system.cpu0.committedOps                     43969024                       # Number of ops (including micro ops) committed
 system.cpu0.num_int_alu_accesses             39881498                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                  4107                       # Number of float alu accesses
 system.cpu0.num_func_calls                     977479                       # number of times a function call or return occured
@@ -296,51 +516,39 @@ system.cpu0.icache.total_refs                35367311                       # To
 system.cpu0.icache.sampled_refs                380581                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                 92.929786                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle           74921716000                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           510.849663                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.997753                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::0           35367311                       # number of ReadReq hits
+system.cpu0.icache.occ_blocks::cpu0.inst   510.849663                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.997753                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.997753                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst     35367311                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       35367311                       # number of ReadReq hits
-system.cpu0.icache.demand_hits::0            35367311                       # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::cpu0.inst     35367311                       # number of demand (read+write) hits
 system.cpu0.icache.demand_hits::total        35367311                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::0           35367311                       # number of overall hits
-system.cpu0.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.icache.overall_hits::cpu0.inst     35367311                       # number of overall hits
 system.cpu0.icache.overall_hits::total       35367311                       # number of overall hits
-system.cpu0.icache.ReadReq_misses::0           380583                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::cpu0.inst       380583                       # number of ReadReq misses
 system.cpu0.icache.ReadReq_misses::total       380583                       # number of ReadReq misses
-system.cpu0.icache.demand_misses::0            380583                       # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::cpu0.inst       380583                       # number of demand (read+write) misses
 system.cpu0.icache.demand_misses::total        380583                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::0           380583                       # number of overall misses
-system.cpu0.icache.overall_misses::1                0                       # number of overall misses
+system.cpu0.icache.overall_misses::cpu0.inst       380583                       # number of overall misses
 system.cpu0.icache.overall_misses::total       380583                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency    5651439000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency     5651439000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency    5651439000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::0       35747894                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst   5651439000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total   5651439000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst   5651439000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total   5651439000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst   5651439000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total   5651439000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst     35747894                       # number of ReadReq accesses(hits+misses)
 system.cpu0.icache.ReadReq_accesses::total     35747894                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::0        35747894                       # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::cpu0.inst     35747894                       # number of demand (read+write) accesses
 system.cpu0.icache.demand_accesses::total     35747894                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::0       35747894                       # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst     35747894                       # number of overall (read+write) accesses
 system.cpu0.icache.overall_accesses::total     35747894                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::0      0.010646                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::0       0.010646                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::0      0.010646                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::0 14849.425749                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::0 14849.425749                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::0 14849.425749                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.010646                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.010646                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.010646                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14849.425749                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14849.425749                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14849.425749                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -349,34 +557,32 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                   12960                       # number of writebacks
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses         380583                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses          380583                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses         380583                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency   4509188500                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency   4509188500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency   4509188500                       # number of overall MSHR miss cycles
-system.cpu0.icache.ReadReq_mshr_uncacheable_latency    351814000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency    351814000                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate::0     0.010646                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate::0     0.010646                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate::0     0.010646                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 11848.108034                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 11848.108034                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 11848.108034                       # average overall mshr miss latency
-system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.writebacks::writebacks        12960                       # number of writebacks
+system.cpu0.icache.writebacks::total            12960                       # number of writebacks
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst       380583                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total       380583                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst       380583                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total       380583                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst       380583                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total       380583                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst   4509188500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total   4509188500                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst   4509188500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total   4509188500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst   4509188500                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total   4509188500                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total    351814000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst    351814000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.overall_mshr_uncacheable_latency::total    351814000                       # number of overall MSHR uncacheable cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.010646                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.010646                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.010646                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11848.108034                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11848.108034                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11848.108034                       # average overall mshr miss latency
+system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst          inf                       # average overall mshr uncacheable latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                334596                       # number of replacements
 system.cpu0.dcache.tagsinuse               450.118381                       # Cycle average of tags in use
@@ -384,84 +590,69 @@ system.cpu0.dcache.total_refs                12875674                       # To
 system.cpu0.dcache.sampled_refs                335004                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                 38.434389                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle             663204000                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           450.118381                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.879137                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits::0            7428609                       # number of ReadReq hits
+system.cpu0.dcache.occ_blocks::cpu0.data   450.118381                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.879137                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.879137                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data      7428609                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        7428609                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits::0           5172633                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data      5172633                       # number of WriteReq hits
 system.cpu0.dcache.WriteReq_hits::total       5172633                       # number of WriteReq hits
-system.cpu0.dcache.LoadLockedReq_hits::0       126778                       # number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_hits::cpu0.data       126778                       # number of LoadLockedReq hits
 system.cpu0.dcache.LoadLockedReq_hits::total       126778                       # number of LoadLockedReq hits
-system.cpu0.dcache.StoreCondReq_hits::       127996                       # number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_hits::cpu0.data       127996                       # number of StoreCondReq hits
 system.cpu0.dcache.StoreCondReq_hits::total       127996                       # number of StoreCondReq hits
-system.cpu0.dcache.demand_hits::0            12601242                       # number of demand (read+write) hits
-system.cpu0.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::cpu0.data     12601242                       # number of demand (read+write) hits
 system.cpu0.dcache.demand_hits::total        12601242                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits::0           12601242                       # number of overall hits
-system.cpu0.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu0.dcache.overall_hits::cpu0.data     12601242                       # number of overall hits
 system.cpu0.dcache.overall_hits::total       12601242                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses::0           217330                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::cpu0.data       217330                       # number of ReadReq misses
 system.cpu0.dcache.ReadReq_misses::total       217330                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses::0          155538                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data       155538                       # number of WriteReq misses
 system.cpu0.dcache.WriteReq_misses::total       155538                       # number of WriteReq misses
-system.cpu0.dcache.LoadLockedReq_misses::0         9456                       # number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_misses::cpu0.data         9456                       # number of LoadLockedReq misses
 system.cpu0.dcache.LoadLockedReq_misses::total         9456                       # number of LoadLockedReq misses
-system.cpu0.dcache.StoreCondReq_misses::0         8189                       # number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_misses::cpu0.data         8189                       # number of StoreCondReq misses
 system.cpu0.dcache.StoreCondReq_misses::total         8189                       # number of StoreCondReq misses
-system.cpu0.dcache.demand_misses::0            372868                       # number of demand (read+write) misses
-system.cpu0.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::cpu0.data       372868                       # number of demand (read+write) misses
 system.cpu0.dcache.demand_misses::total        372868                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses::0           372868                       # number of overall misses
-system.cpu0.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu0.dcache.overall_misses::cpu0.data       372868                       # number of overall misses
 system.cpu0.dcache.overall_misses::total       372868                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency    3330686000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency   6317758500                       # number of WriteReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_latency    100249000                       # number of LoadLockedReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_latency     70240000                       # number of StoreCondReq miss cycles
-system.cpu0.dcache.demand_miss_latency     9648444500                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency    9648444500                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses::0        7645939                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data   3330686000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total   3330686000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data   6317758500                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total   6317758500                       # number of WriteReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data    100249000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_latency::total    100249000                       # number of LoadLockedReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data     70240000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_latency::total     70240000                       # number of StoreCondReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data   9648444500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total   9648444500                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data   9648444500                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total   9648444500                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data      7645939                       # number of ReadReq accesses(hits+misses)
 system.cpu0.dcache.ReadReq_accesses::total      7645939                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses::      5328171                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data      5328171                       # number of WriteReq accesses(hits+misses)
 system.cpu0.dcache.WriteReq_accesses::total      5328171                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_accesses::0       136234                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data       136234                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu0.dcache.LoadLockedReq_accesses::total       136234                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_accesses::0       136185                       # number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_accesses::cpu0.data       136185                       # number of StoreCondReq accesses(hits+misses)
 system.cpu0.dcache.StoreCondReq_accesses::total       136185                       # number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses::0        12974110                       # number of demand (read+write) accesses
-system.cpu0.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::cpu0.data     12974110                       # number of demand (read+write) accesses
 system.cpu0.dcache.demand_accesses::total     12974110                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses::0       12974110                       # number of overall (read+write) accesses
-system.cpu0.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data     12974110                       # number of overall (read+write) accesses
 system.cpu0.dcache.overall_accesses::total     12974110                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate::0      0.028424                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate::0     0.029192                       # miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_miss_rate::0     0.069410                       # miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_miss_rate::0     0.060131                       # miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_miss_rate::0       0.028739                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu0.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate::0      0.028739                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu0.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency::0 15325.477385                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::0 40618.745901                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::0 10601.628596                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::0  8577.359873                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency::0 25876.300728                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::0 25876.300728                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.028424                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.029192                       # miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data     0.069410                       # miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data     0.060131                       # miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.028739                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.028739                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15325.477385                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40618.745901                       # average WriteReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10601.628596                       # average LoadLockedReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data  8577.359873                       # average StoreCondReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 25876.300728                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 25876.300728                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -470,56 +661,56 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                  294891                       # number of writebacks
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses         217330                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses        155538                       # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses         9456                       # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses         8184                       # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses          372868                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses         372868                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency   2678673500                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency   5851029000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency     71881000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency     45691000                       # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency         1000                       # number of StoreCondFailReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency   8529702500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency   8529702500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency   9171180500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency  40129379500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency  49300560000                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::0     0.028424                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::0     0.029192                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::0     0.069410                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::0     0.060095                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::0     0.028739                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::0     0.028739                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 12325.373855                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 37618.003318                       # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency  7601.628596                       # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency  5582.966764                       # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency          inf                       # average StoreCondFailReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 22875.930624                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 22875.930624                       # average overall mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks       294891                       # number of writebacks
+system.cpu0.dcache.writebacks::total           294891                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data       217330                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total       217330                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data       155538                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total       155538                       # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data         9456                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total         9456                       # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data         8184                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total         8184                       # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data       372868                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total       372868                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data       372868                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total       372868                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data   2678673500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total   2678673500                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data   5851029000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total   5851029000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data     71881000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total     71881000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data     45691000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total     45691000                       # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total         1000                       # number of StoreCondFailReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data   8529702500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total   8529702500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data   8529702500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total   8529702500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data   9171180500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total   9171180500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data  40129379500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total  40129379500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data  49300560000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total  49300560000                       # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.028424                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.029192                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data     0.069410                       # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data     0.060095                       # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.028739                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.028739                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12325.373855                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 37618.003318                       # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data  7601.628596                       # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data  5582.966764                       # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data          inf                       # average StoreCondFailReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 22875.930624                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 22875.930624                       # average overall mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
@@ -566,7 +757,8 @@ system.cpu1.itb.accesses                     26851434                       # DT
 system.cpu1.numCycles                      5339222450                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.num_insts                        34444935                       # Number of instructions executed
+system.cpu1.committedInsts                   25921760                       # Number of instructions committed
+system.cpu1.committedOps                     34444935                       # Number of ops (including micro ops) committed
 system.cpu1.num_int_alu_accesses             31033253                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                  5714                       # Number of float alu accesses
 system.cpu1.num_func_calls                    1093852                       # number of times a function call or return occured
@@ -592,51 +784,39 @@ system.cpu1.icache.total_refs                26339543                       # To
 system.cpu1.icache.sampled_refs                508733                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                 51.774788                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle          191336880000                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0           497.375159                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.971436                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::0           26339543                       # number of ReadReq hits
+system.cpu1.icache.occ_blocks::cpu1.inst   497.375159                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.971436                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.971436                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst     26339543                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total       26339543                       # number of ReadReq hits
-system.cpu1.icache.demand_hits::0            26339543                       # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::cpu1.inst     26339543                       # number of demand (read+write) hits
 system.cpu1.icache.demand_hits::total        26339543                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits::0           26339543                       # number of overall hits
-system.cpu1.icache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.icache.overall_hits::cpu1.inst     26339543                       # number of overall hits
 system.cpu1.icache.overall_hits::total       26339543                       # number of overall hits
-system.cpu1.icache.ReadReq_misses::0           508733                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::cpu1.inst       508733                       # number of ReadReq misses
 system.cpu1.icache.ReadReq_misses::total       508733                       # number of ReadReq misses
-system.cpu1.icache.demand_misses::0            508733                       # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::cpu1.inst       508733                       # number of demand (read+write) misses
 system.cpu1.icache.demand_misses::total        508733                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::0           508733                       # number of overall misses
-system.cpu1.icache.overall_misses::1                0                       # number of overall misses
+system.cpu1.icache.overall_misses::cpu1.inst       508733                       # number of overall misses
 system.cpu1.icache.overall_misses::total       508733                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency    7436442000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency     7436442000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency    7436442000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::0       26848276                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst   7436442000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total   7436442000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst   7436442000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total   7436442000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst   7436442000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total   7436442000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst     26848276                       # number of ReadReq accesses(hits+misses)
 system.cpu1.icache.ReadReq_accesses::total     26848276                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses::0        26848276                       # number of demand (read+write) accesses
-system.cpu1.icache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::cpu1.inst     26848276                       # number of demand (read+write) accesses
 system.cpu1.icache.demand_accesses::total     26848276                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses::0       26848276                       # number of overall (read+write) accesses
-system.cpu1.icache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst     26848276                       # number of overall (read+write) accesses
 system.cpu1.icache.overall_accesses::total     26848276                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::0      0.018948                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::0       0.018948                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate::0      0.018948                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::0 14617.573462                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::0 14617.573462                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::0 14617.573462                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.018948                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.018948                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.018948                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14617.573462                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14617.573462                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14617.573462                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -645,34 +825,32 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                   27998                       # number of writebacks
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses         508733                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses          508733                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses         508733                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency   5908060000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency   5908060000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency   5908060000                       # number of overall MSHR miss cycles
-system.cpu1.icache.ReadReq_mshr_uncacheable_latency      5250000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency      5250000                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate::0     0.018948                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate::0     0.018948                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::0     0.018948                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 11613.282409                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 11613.282409                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 11613.282409                       # average overall mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.writebacks::writebacks        27998                       # number of writebacks
+system.cpu1.icache.writebacks::total            27998                       # number of writebacks
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst       508733                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total       508733                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst       508733                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total       508733                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst       508733                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total       508733                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst   5908060000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total   5908060000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst   5908060000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total   5908060000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst   5908060000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total   5908060000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total      5250000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst      5250000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.overall_mshr_uncacheable_latency::total      5250000                       # number of overall MSHR uncacheable cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.018948                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.018948                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.018948                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11613.282409                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11613.282409                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11613.282409                       # average overall mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst          inf                       # average overall mshr uncacheable latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                295754                       # number of replacements
 system.cpu1.dcache.tagsinuse               467.166427                       # Cycle average of tags in use
@@ -680,84 +858,69 @@ system.cpu1.dcache.total_refs                11737107                       # To
 system.cpu1.dcache.sampled_refs                296266                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                 39.616787                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle           75924171000                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0           467.166427                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.912434                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits::0            6345290                       # number of ReadReq hits
+system.cpu1.dcache.occ_blocks::cpu1.data   467.166427                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.912434                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.912434                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data      6345290                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        6345290                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits::0           5152610                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data      5152610                       # number of WriteReq hits
 system.cpu1.dcache.WriteReq_hits::total       5152610                       # number of WriteReq hits
-system.cpu1.dcache.LoadLockedReq_hits::0       104795                       # number of LoadLockedReq hits
+system.cpu1.dcache.LoadLockedReq_hits::cpu1.data       104795                       # number of LoadLockedReq hits
 system.cpu1.dcache.LoadLockedReq_hits::total       104795                       # number of LoadLockedReq hits
-system.cpu1.dcache.StoreCondReq_hits::       106403                       # number of StoreCondReq hits
+system.cpu1.dcache.StoreCondReq_hits::cpu1.data       106403                       # number of StoreCondReq hits
 system.cpu1.dcache.StoreCondReq_hits::total       106403                       # number of StoreCondReq hits
-system.cpu1.dcache.demand_hits::0            11497900                       # number of demand (read+write) hits
-system.cpu1.dcache.demand_hits::1                   0                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::cpu1.data     11497900                       # number of demand (read+write) hits
 system.cpu1.dcache.demand_hits::total        11497900                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits::0           11497900                       # number of overall hits
-system.cpu1.dcache.overall_hits::1                  0                       # number of overall hits
+system.cpu1.dcache.overall_hits::cpu1.data     11497900                       # number of overall hits
 system.cpu1.dcache.overall_hits::total       11497900                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses::0           188245                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::cpu1.data       188245                       # number of ReadReq misses
 system.cpu1.dcache.ReadReq_misses::total       188245                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses::0          137493                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data       137493                       # number of WriteReq misses
 system.cpu1.dcache.WriteReq_misses::total       137493                       # number of WriteReq misses
-system.cpu1.dcache.LoadLockedReq_misses::0        11557                       # number of LoadLockedReq misses
+system.cpu1.dcache.LoadLockedReq_misses::cpu1.data        11557                       # number of LoadLockedReq misses
 system.cpu1.dcache.LoadLockedReq_misses::total        11557                       # number of LoadLockedReq misses
-system.cpu1.dcache.StoreCondReq_misses::0         9906                       # number of StoreCondReq misses
+system.cpu1.dcache.StoreCondReq_misses::cpu1.data         9906                       # number of StoreCondReq misses
 system.cpu1.dcache.StoreCondReq_misses::total         9906                       # number of StoreCondReq misses
-system.cpu1.dcache.demand_misses::0            325738                       # number of demand (read+write) misses
-system.cpu1.dcache.demand_misses::1                 0                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::cpu1.data       325738                       # number of demand (read+write) misses
 system.cpu1.dcache.demand_misses::total        325738                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses::0           325738                       # number of overall misses
-system.cpu1.dcache.overall_misses::1                0                       # number of overall misses
+system.cpu1.dcache.overall_misses::cpu1.data       325738                       # number of overall misses
 system.cpu1.dcache.overall_misses::total       325738                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency    2729023500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency   4123985000                       # number of WriteReq miss cycles
-system.cpu1.dcache.LoadLockedReq_miss_latency    131721000                       # number of LoadLockedReq miss cycles
-system.cpu1.dcache.StoreCondReq_miss_latency     82493000                       # number of StoreCondReq miss cycles
-system.cpu1.dcache.demand_miss_latency     6853008500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency    6853008500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses::0        6533535                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data   2729023500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total   2729023500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data   4123985000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total   4123985000                       # number of WriteReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data    131721000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.LoadLockedReq_miss_latency::total    131721000                       # number of LoadLockedReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data     82493000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.StoreCondReq_miss_latency::total     82493000                       # number of StoreCondReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data   6853008500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total   6853008500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data   6853008500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total   6853008500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data      6533535                       # number of ReadReq accesses(hits+misses)
 system.cpu1.dcache.ReadReq_accesses::total      6533535                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses::      5290103                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data      5290103                       # number of WriteReq accesses(hits+misses)
 system.cpu1.dcache.WriteReq_accesses::total      5290103                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.LoadLockedReq_accesses::0       116352                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data       116352                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu1.dcache.LoadLockedReq_accesses::total       116352                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu1.dcache.StoreCondReq_accesses::0       116309                       # number of StoreCondReq accesses(hits+misses)
+system.cpu1.dcache.StoreCondReq_accesses::cpu1.data       116309                       # number of StoreCondReq accesses(hits+misses)
 system.cpu1.dcache.StoreCondReq_accesses::total       116309                       # number of StoreCondReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses::0        11823638                       # number of demand (read+write) accesses
-system.cpu1.dcache.demand_accesses::1               0                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::cpu1.data     11823638                       # number of demand (read+write) accesses
 system.cpu1.dcache.demand_accesses::total     11823638                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses::0       11823638                       # number of overall (read+write) accesses
-system.cpu1.dcache.overall_accesses::1              0                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data     11823638                       # number of overall (read+write) accesses
 system.cpu1.dcache.overall_accesses::total     11823638                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate::0      0.028812                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate::0     0.025991                       # miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_miss_rate::0     0.099328                       # miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_miss_rate::0     0.085170                       # miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_miss_rate::0       0.027550                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::1       no_value                       # miss rate for demand accesses
-system.cpu1.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate::0      0.027550                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::1      no_value                       # miss rate for overall accesses
-system.cpu1.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency::0 14497.189832                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu1.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::0 29994.145156                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::0 11397.508004                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::0  8327.579245                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::1          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total          inf                       # average StoreCondReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency::0 21038.406634                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::0 21038.406634                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.028812                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.025991                       # miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data     0.099328                       # miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data     0.085170                       # miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.027550                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.027550                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14497.189832                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 29994.145156                       # average WriteReq miss latency
+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11397.508004                       # average LoadLockedReq miss latency
+system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data  8327.579245                       # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21038.406634                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21038.406634                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -766,54 +929,53 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                  253551                       # number of writebacks
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses         188245                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses        137493                       # number of WriteReq MSHR misses
-system.cpu1.dcache.LoadLockedReq_mshr_misses        11557                       # number of LoadLockedReq MSHR misses
-system.cpu1.dcache.StoreCondReq_mshr_misses         9900                       # number of StoreCondReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses          325738                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses         325738                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency   2164153000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency   3711466500                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.LoadLockedReq_mshr_miss_latency     97050000                       # number of LoadLockedReq MSHR miss cycles
-system.cpu1.dcache.StoreCondReq_mshr_miss_latency     52793000                       # number of StoreCondReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency   5875619500                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency   5875619500                       # number of overall MSHR miss cycles
-system.cpu1.dcache.ReadReq_mshr_uncacheable_latency 137931975000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.dcache.WriteReq_mshr_uncacheable_latency    470526000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency 138402501000                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate::0     0.028812                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::0     0.025991                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::0     0.099328                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::0     0.085118                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::1          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total          inf                       # mshr miss rate for StoreCondReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate::0     0.027550                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate::0     0.027550                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 11496.470026                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 26993.857869                       # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency  8397.508004                       # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency  5332.626263                       # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 18037.869392                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 18037.869392                       # average overall mshr miss latency
-system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks       253551                       # number of writebacks
+system.cpu1.dcache.writebacks::total           253551                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data       188245                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total       188245                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data       137493                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total       137493                       # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data        11557                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total        11557                       # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data         9900                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total         9900                       # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data       325738                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total       325738                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data       325738                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total       325738                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data   2164153000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total   2164153000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data   3711466500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total   3711466500                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data     97050000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total     97050000                       # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data     52793000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total     52793000                       # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data   5875619500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total   5875619500                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data   5875619500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total   5875619500                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 137931975000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 137931975000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data    470526000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total    470526000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 138402501000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 138402501000                       # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.028812                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.025991                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data     0.099328                       # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data     0.085118                       # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.027550                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.027550                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11496.470026                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26993.857869                       # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data  8397.508004                       # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data  5332.626263                       # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18037.869392                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18037.869392                       # average overall mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data          inf                       # average overall mshr uncacheable latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -821,38 +983,6 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -861,28 +991,12 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                           0                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1342252853622                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1342252853622                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342252853622                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1342252853622                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342252853622                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1342252853622                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index b4466ea535de8799cd6509eb8836491e76d60a3c..49efd7ba09c46786e8bfbaf976f543fbbfba04de 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,7 +9,6 @@ time_sync_spin_threshold=100000000
 [system]
 type=LinuxArmSystem
 children=bridge cf0 cpu intrctrl iobus iocache l2c membus nvmem physmem realview terminal toL2Bus vncserver
-boot_cpu_frequency=500
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_loader_mem=system.nvmem
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
@@ -90,6 +90,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
+workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
@@ -104,20 +105,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -149,20 +143,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -214,20 +201,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -246,20 +226,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -285,7 +258,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.realview
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -327,7 +299,6 @@ system=system
 type=A9SCU
 pio_addr=520093696
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.membus.port[5]
 
@@ -337,7 +308,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268451840
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[24]
 
@@ -407,7 +377,6 @@ max_backoff_delay=10000000
 min_backoff_delay=4000
 pio_addr=268566528
 pio_latency=10000
-platform=system.realview
 system=system
 vnc=system.vncserver
 dma=system.iobus.port[6]
@@ -419,7 +388,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268632064
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[12]
 
@@ -429,7 +397,6 @@ fake_mem=true
 pio_addr=1073741824
 pio_latency=1000
 pio_size=536870912
-platform=system.realview
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -458,7 +425,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268513280
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[19]
 
@@ -468,7 +434,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268517376
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[20]
 
@@ -478,7 +443,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268521472
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[21]
 
@@ -491,7 +455,6 @@ int_num=52
 is_mouse=false
 pio_addr=268460032
 pio_latency=1000
-platform=system.realview
 system=system
 vnc=system.vncserver
 pio=system.iobus.port[7]
@@ -505,7 +468,6 @@ int_num=53
 is_mouse=true
 pio_addr=268464128
 pio_latency=1000
-platform=system.realview
 system=system
 vnc=system.vncserver
 pio=system.iobus.port[8]
@@ -516,7 +478,6 @@ fake_mem=false
 pio_addr=520101888
 pio_latency=1000
 pio_size=4095
-platform=system.realview
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -535,7 +496,6 @@ int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.membus.port[6]
 
@@ -545,7 +505,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268455936
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[25]
 
@@ -554,7 +513,6 @@ type=RealViewCtrl
 idreg=0
 pio_addr=268435456
 pio_latency=1000
-platform=system.realview
 proc_id0=201326592
 proc_id1=201327138
 system=system
@@ -566,7 +524,6 @@ amba_id=266289
 ignore_access=false
 pio_addr=268529664
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[26]
 
@@ -576,7 +533,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268492800
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[23]
 
@@ -586,7 +542,6 @@ amba_id=0
 ignore_access=false
 pio_addr=269357056
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[16]
 
@@ -596,7 +551,6 @@ amba_id=0
 ignore_access=true
 pio_addr=268439552
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[17]
 
@@ -606,7 +560,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268488704
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[22]
 
@@ -620,7 +573,6 @@ int_num0=36
 int_num1=36
 pio_addr=268505088
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[3]
 
@@ -634,7 +586,6 @@ int_num0=37
 int_num1=37
 pio_addr=268509184
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[4]
 
@@ -657,7 +608,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268476416
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[13]
 
@@ -667,7 +617,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268480512
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[14]
 
@@ -677,7 +626,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268484608
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[15]
 
@@ -687,7 +635,6 @@ amba_id=0
 ignore_access=false
 pio_addr=268500992
 pio_latency=1000
-platform=system.realview
 system=system
 pio=system.iobus.port[18]
 
index 661533caf035a28cb694e55156b18d3ddf615fab..af233a80cbb848b9bb6b7d5fc7732c7d84e3fe22 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:21:22
-gem5 started Jan 23 2012 04:25:02
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:37:03
 gem5 executing on zizzer
-command line: build/ARM_FS/gem5.opt -d build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM_FS/tests/opt/quick/10.linux-boot/arm/linux/realview-simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
index 5437209981eaf6f64ccf65a65df60b96cbda480f..833c19821d5edef6574c136c03f7c13060a11e1f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  2.591442                       # Nu
 sim_ticks                                2591441692000                       # Number of ticks simulated
 final_tick                               2591441692000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 852555                       # Simulator instruction rate (inst/s)
-host_tick_rate                            29271571690                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 379496                       # Number of bytes of host memory used
-host_seconds                                    88.53                       # Real time elapsed on the host
-sim_insts                                    75477515                       # Number of instructions simulated
+host_inst_rate                                 874833                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1117723                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            38375829651                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 376612                       # Number of bytes of host memory used
+host_seconds                                    67.53                       # Real time elapsed on the host
+sim_insts                                    59075683                       # Number of instructions simulated
+sim_ops                                      75477515                       # Number of ops (including micro ops) simulated
 system.nvmem.bytes_read                            20                       # Number of bytes read from this memory
 system.nvmem.bytes_inst_read                       20                       # Number of instructions bytes read from this memory
 system.nvmem.bytes_written                          0                       # Number of bytes written to this memory
@@ -34,84 +36,125 @@ system.l2c.total_refs                         1535240                       # To
 system.l2c.sampled_refs                        146709                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         10.464525                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                 10331.534348                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 14596.842556                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.157647                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.222730                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    1198360                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                      12495                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        14588.908220                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        6.963925                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.970411                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           5158.445831                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           5173.088517                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.222609                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000106                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.078712                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.078935                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.380377                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          8825                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          3670                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              837469                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data              360891                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                1210855                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                   610049                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks          610049                       # number of Writeback hits
 system.l2c.Writeback_hits::total               610049                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      26                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data               26                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  26                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   106473                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            106473                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               106473                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     1304833                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                       12495                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker           8825                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           3670                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               837469                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data               467364                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 1317328                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    1304833                       # number of overall hits
-system.l2c.overall_hits::1                      12495                       # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker          8825                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          3670                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              837469                       # number of overall hits
+system.l2c.overall_hits::cpu.data              467364                       # number of overall hits
 system.l2c.overall_hits::total                1317328                       # number of overall hits
-system.l2c.ReadReq_misses::0                    31685                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       37                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker           24                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           13                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             14429                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             17256                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                31722                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  2875                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data           2875                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              2875                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 140928                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          140928                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             140928                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    172613                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        37                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker           24                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              14429                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             158184                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                172650                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   172613                       # number of overall misses
-system.l2c.overall_misses::1                       37                       # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker           24                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           13                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             14429                       # number of overall misses
+system.l2c.overall_misses::cpu.data            158184                       # number of overall misses
 system.l2c.overall_misses::total               172650                       # number of overall misses
-system.l2c.ReadReq_miss_latency            1654516000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency            1040000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          7338006500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             8992522500                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            8992522500                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                1230045                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                  12532                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker      1250000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       676000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    753120500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data    899469500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     1654516000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data      1040000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total      1040000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   7338006500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   7338006500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker      1250000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       676000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    753120500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8237476000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8992522500                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker      1250000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       676000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    753120500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8237476000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8992522500                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         8849                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         3683                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          851898                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data          378147                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            1242577                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0               610049                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks       610049                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total           610049                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2901                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         2901                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            2901                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               247401                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        247401                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           247401                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 1477446                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                   12532                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker         8849                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         3683                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           851898                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data           625548                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             1489978                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                1477446                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                  12532                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         8849                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         3683                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          851898                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data          625548                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            1489978                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.025759                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.002952                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.028712                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.991038                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.569634                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.116832                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.002952                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.119784                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.116832                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.002952                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.119784                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52217.642418                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   44716648.648649                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 44768866.291066                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0   361.739130                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52069.187812                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52096.438275                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    243041148.648649                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 243093245.086924                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52096.438275                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   243041148.648649                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 243093245.086924                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.002712                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003530                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.016937                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.045633                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.991038                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.569634                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.002712                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.003530                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.016937                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.252873                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.002712                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.003530                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.016937                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.252873                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker 52083.333333                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52194.919953                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52125.028975                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data   361.739130                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52069.187812                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker 52083.333333                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52194.919953                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52075.279421                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker 52083.333333                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52194.919953                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52075.279421                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -120,48 +163,87 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          103410                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  31722                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                2875                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               140928                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  172650                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 172650                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       1273844000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     115156000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     5646870000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        6920714000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       6920714000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency 131817513000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency  31206766500                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency 163024279500                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.025789                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         2.531280                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     2.557069                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.991038                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.569634                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.116857                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1         13.776732                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total     13.893589                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.116857                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1        13.776732                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total    13.893589                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40156.484459                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40054.260870                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40069.184264                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40085.224443                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40085.224443                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              103410                       # number of writebacks
+system.l2c.writebacks::total                   103410                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           24                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker           13                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        14429                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        17256                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           31722                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         2875                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         2875                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       140928                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        140928                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           24                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker           13                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         14429                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        158184                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           172650                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           24                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker           13                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        14429                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       158184                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          172650                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       962000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       520000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    579966000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data    692396000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1273844000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data    115156000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    115156000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   5646870000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   5646870000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       962000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       520000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    579966000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6339266000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6920714000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       962000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       520000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    579966000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6339266000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6920714000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.inst    264840000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 131552673000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total 131817513000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data  31206766500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total  31206766500                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.inst    264840000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data 162759439500                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total 163024279500                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.002712                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.003530                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.016937                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.045633                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.991038                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.569634                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.002712                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.003530                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.016937                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.252873                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.002712                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.003530                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.016937                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.252873                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40194.469471                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40124.942049                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40054.260870                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40069.184264                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40194.469471                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40075.266778                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40083.333333                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40194.469471                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40075.266778                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cf0.dma_read_full_pages                      0                       # Number of full page size DMA reads (not PRD).
 system.cf0.dma_read_bytes                           0                       # Number of bytes transfered via DMA reads (not PRD).
@@ -214,7 +296,8 @@ system.cpu.itb.accesses                      60362193                       # DT
 system.cpu.numCycles                       5182883384                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                         75477515                       # Number of instructions executed
+system.cpu.committedInsts                    59075683                       # Number of instructions committed
+system.cpu.committedOps                      75477515                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses              68255270                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                  10269                       # Number of float alu accesses
 system.cpu.num_func_calls                     1975579                       # number of times a function call or return occured
@@ -240,51 +323,39 @@ system.cpu.icache.total_refs                 59504239                       # To
 system.cpu.icache.sampled_refs                 853483                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  69.719302                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle            18512998000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.943281                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.997936                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0            59504239                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     510.943281                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.997936                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.997936                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst     59504239                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        59504239                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0             59504239                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst      59504239                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total         59504239                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0            59504239                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst     59504239                       # number of overall hits
 system.cpu.icache.overall_hits::total        59504239                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            853483                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       853483                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        853483                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             853483                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       853483                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         853483                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            853483                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       853483                       # number of overall misses
 system.cpu.icache.overall_misses::total        853483                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    12547128000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     12547128000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    12547128000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0        60357722                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  12547128000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  12547128000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  12547128000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  12547128000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  12547128000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  12547128000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst     60357722                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total     60357722                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0         60357722                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst     60357722                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total     60357722                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0        60357722                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst     60357722                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total     60357722                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.014140                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.014140                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.014140                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14701.087192                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14701.087192                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14701.087192                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.014140                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.014140                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.014140                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14701.087192                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14701.087192                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14701.087192                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -293,34 +364,32 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                    45661                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          853483                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           853483                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          853483                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   9984295500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   9984295500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   9984295500                       # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_uncacheable_latency    350913000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency    350913000                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.014140                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.014140                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.014140                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11698.294518                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11698.294518                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11698.294518                       # average overall mshr miss latency
-system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks        45661                       # number of writebacks
+system.cpu.icache.writebacks::total             45661                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       853483                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       853483                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       853483                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       853483                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       853483                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       853483                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9984295500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9984295500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9984295500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9984295500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9984295500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9984295500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst    350913000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_uncacheable_latency::total    350913000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst    350913000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_latency::total    350913000                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.014140                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.014140                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.014140                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11698.294518                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11698.294518                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11698.294518                       # average overall mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                 626903                       # number of replacements
 system.cpu.dcache.tagsinuse                511.875592                       # Cycle average of tags in use
@@ -328,77 +397,63 @@ system.cpu.dcache.total_refs                 23615096                       # To
 system.cpu.dcache.sampled_refs                 627415                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  37.638718                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle              660309000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.875592                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999757                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            13170367                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.875592                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999757                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999757                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     13170367                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13170367                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            9958094                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      9958094                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        9958094                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::       236142                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       236142                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       236142                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::0         247592                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       247592                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       247592                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::0             23128461                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      23128461                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         23128461                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            23128461                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     23128461                       # number of overall hits
 system.cpu.dcache.overall_hits::total        23128461                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0            368563                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data       368563                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        368563                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           250302                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       250302                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       250302                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::0        11451                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data        11451                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total        11451                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses::0             618865                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data       618865                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total         618865                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0            618865                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data       618865                       # number of overall misses
 system.cpu.dcache.overall_misses::total        618865                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency     5846897000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    9551170500                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency    186076500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency     15398067500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    15398067500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13538930                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   5846897000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total   5846897000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9551170500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9551170500                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    186076500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total    186076500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  15398067500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  15398067500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  15398067500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  15398067500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13538930                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     13538930                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0       10208396                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     10208396                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     10208396                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::0       247593                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       247593                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       247593                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::0       247592                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       247592                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       247592                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         23747326                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     23747326                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     23747326                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        23747326                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     23747326                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     23747326                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.027222                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.024519                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::0     0.046249                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.026060                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.026060                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15864.036813                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 38158.586428                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::0 16249.803511                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::1          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::total          inf                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 24881.141283                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 24881.141283                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.027222                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.024519                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.046249                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.026060                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.026060                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15864.036813                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38158.586428                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 16249.803511                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 24881.141283                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 24881.141283                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -407,48 +462,47 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                   564388                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses          368563                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         250302                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses        11451                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.demand_mshr_misses           618865                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses          618865                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   4741074500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8800219500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency    151723500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  13541294000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  13541294000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency 146946835000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency  40367455500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency 187314290500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.027222                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.024519                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::0     0.046249                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::1          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total          inf                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.026060                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.026060                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12863.674596                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35158.406645                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency 13249.803511                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 21880.852852                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 21880.852852                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks       564388                       # number of writebacks
+system.cpu.dcache.writebacks::total            564388                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       368563                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total       368563                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       250302                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       250302                       # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data        11451                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total        11451                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       618865                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total       618865                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       618865                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total       618865                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   4741074500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total   4741074500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8800219500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8800219500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data    151723500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total    151723500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  13541294000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  13541294000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  13541294000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  13541294000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146946835000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146946835000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data  40367455500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total  40367455500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187314290500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 187314290500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.027222                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.024519                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.046249                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.026060                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.026060                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12863.674596                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35158.406645                       # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13249.803511                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21880.852852                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21880.852852                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.iocache.replacements                         0                       # number of replacements
 system.iocache.tagsinuse                            0                       # Cycle average of tags in use
@@ -456,38 +510,6 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                         0                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                      no_value                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::total                 0                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                    0                       # number of overall misses
-system.iocache.overall_misses::total                0                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::total               0                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::total              0                       # number of overall (read+write) accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -496,28 +518,12 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                           0                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.ReadReq_mshr_uncacheable_latency 1341941439938                       # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency 1341941439938                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.iocache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341941439938                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1341941439938                       # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341941439938                       # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1341941439938                       # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average ReadReq mshr uncacheable latency
+system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd          inf                       # average overall mshr uncacheable latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 91a089b4bb4fbafcdeb320f2e647208f9c3be11f..1885ca8f8569f78cd5f124179583e520d7522e15 100644 (file)
@@ -1,15 +1,15 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
 acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
 e820_table=system.e820_table
 init_param=0
@@ -50,6 +50,17 @@ oem_id=
 oem_revision=0
 oem_table_id=
 
+[system.apicbridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
 [system.bridge]
 type=Bridge
 delay=50000
@@ -89,6 +100,7 @@ simulate_inst_stalls=false
 system=system
 tracer=system.cpu.tracer
 width=1
+workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
@@ -103,20 +115,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -146,20 +151,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -178,20 +176,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -204,7 +195,6 @@ type=X86LocalApic
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
-platform=system.pc
 system=system
 int_port=system.membus.port[7]
 pio=system.membus.port[6]
@@ -231,20 +221,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -618,17 +601,6 @@ subtractive_decode=true
 type=IntrControl
 sys=system
 
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
 [system.iobus]
 type=Bus
 block_size=64
@@ -638,7 +610,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -651,20 +623,13 @@ is_top_level=true
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -683,20 +648,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -714,7 +672,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -722,7 +680,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -745,7 +702,6 @@ fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -786,7 +742,6 @@ fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -803,7 +758,6 @@ fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -820,7 +774,6 @@ fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -837,7 +790,6 @@ fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=1000
 pio_size=2
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -854,7 +806,6 @@ fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=1000
 pio_size=1
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -894,7 +845,6 @@ children=int_pin
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=1000
-platform=system.pc
 system=system
 time=Sun Jan  1 00:00:00 2012
 pio=system.iobus.port[2]
@@ -906,7 +856,6 @@ type=X86IntSourcePin
 type=I8237
 pio_addr=9223372036854775808
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[3]
 
@@ -1091,7 +1040,6 @@ external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
 pio_latency=1000
-platform=system.pc
 system=system
 int_port=system.iobus.port[13]
 pio=system.iobus.port[12]
@@ -1105,7 +1053,6 @@ keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
 mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[7]
 
@@ -1122,7 +1069,6 @@ mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
 pio_latency=1000
-platform=system.pc
 slave=system.pc.south_bridge.pic2
 system=system
 pio=system.iobus.port[8]
@@ -1137,7 +1083,6 @@ mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
 pio_latency=1000
-platform=system.pc
 slave=Null
 system=system
 pio=system.iobus.port[9]
@@ -1151,7 +1096,6 @@ children=int_pin
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[10]
 
@@ -1163,7 +1107,6 @@ type=PcSpeaker
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[11]
 
index 23cf47db2e3c63c69ba64804b7be7ab439a37681..e4d0a503279a4623975ba50c47403f7a2da65abc 100755 (executable)
@@ -1,13 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:46
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:48
 gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5112043255000 because m5_exit instruction encountered
index 324bf8929acb9d07e79b5ee83ec08f9e81f812ae..21f7dfc5d1b7f5d95600fa29bc42c08ff92628a8 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  5.112043                       # Nu
 sim_ticks                                5112043255000                       # Number of ticks simulated
 final_tick                               5112043255000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                2850135                       # Simulator instruction rate (inst/s)
-host_tick_rate                            35611898535                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 353172                       # Number of bytes of host memory used
-host_seconds                                   143.55                       # Real time elapsed on the host
-sim_insts                                   409133277                       # Number of instructions simulated
+host_inst_rate                                1772716                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3629762                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            45353186641                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 350348                       # Number of bytes of host memory used
+host_seconds                                   112.72                       # Real time elapsed on the host
+sim_insts                                   199813913                       # Number of instructions simulated
+sim_ops                                     409133277                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    15568704                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 972736                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 12232896                       # Number of bytes written to this memory
@@ -25,72 +27,92 @@ system.l2c.total_refs                         3332458                       # To
 system.l2c.sampled_refs                        196390                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         16.968573                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  9701.563280                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 27141.380805                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.148034                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.414145                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2042917                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                       9538                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        27139.322665                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        2.054559                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.003581                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           1828.819855                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           7872.743425                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.414113                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000031                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.027906                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.120129                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.562179                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          6729                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          2809                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              776101                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1266816                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                2052455                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1529403                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks         1529403                       # number of Writeback hits
 system.l2c.Writeback_hits::total              1529403                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                      31                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data               31                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                  31                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   168948                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            168948                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               168948                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2211865                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                        9538                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker           6729                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           2809                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               776101                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1435764                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 2221403                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2211865                       # number of overall hits
-system.l2c.overall_hits::1                       9538                       # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker          6729                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          2809                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              776101                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1435764                       # number of overall hits
 system.l2c.overall_hits::total                2221403                       # number of overall hits
-system.l2c.ReadReq_misses::0                    55972                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       27                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker           16                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           11                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             15200                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             40772                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                55999                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  1792                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data           1792                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              1792                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 144639                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          144639                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             144639                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    200611                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        27                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker           16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           11                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              15200                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             185411                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                200638                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   200611                       # number of overall misses
-system.l2c.overall_misses::1                       27                       # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker           16                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           11                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             15200                       # number of overall misses
+system.l2c.overall_misses::cpu.data            185411                       # number of overall misses
 system.l2c.overall_misses::total               200638                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2098889                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                   9565                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.dtb.walker         6745                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         2820                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          791301                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1307588                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2108454                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1529403                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1529403                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total          1529403                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                1823                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         1823                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            1823                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               313587                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        313587                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           313587                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2412476                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                    9565                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker         6745                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         2820                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           791301                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1621175                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2422041                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2412476                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                   9565                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         6745                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         2820                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          791301                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1621175                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2422041                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.026667                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.002823                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.029490                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.982995                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.461240                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.083156                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.002823                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.085978                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.083156                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.002823                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.085978                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.002372                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003901                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.019209                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.031181                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.982995                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.461240                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.002372                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.003901                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.019209                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.114368                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.002372                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.003901                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.019209                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.114368                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -99,26 +121,8 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          144472                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              144472                       # number of writebacks
+system.l2c.writebacks::total                   144472                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47570                       # number of replacements
 system.iocache.tagsinuse                     0.042409                       # Cycle average of tags in use
@@ -126,50 +130,29 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     47586                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              4994776740009                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.042409                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.002651                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  905                       # number of ReadReq misses
+system.iocache.occ_blocks::pc.south_bridge.ide     0.042409                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.002651                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.002651                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          905                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              905                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
+system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47625                       # number of demand (read+write) misses
+system.iocache.demand_misses::pc.south_bridge.ide        47625                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             47625                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47625                       # number of overall misses
+system.iocache.overall_misses::pc.south_bridge.ide        47625                       # number of overall misses
 system.iocache.overall_misses::total            47625                       # number of overall misses
-system.iocache.demand_miss_latency                  0                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency                 0                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                905                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          905                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            905                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47625                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47625                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           47625                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47625                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47625                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47625                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
@@ -178,26 +161,8 @@ system.iocache.avg_blocked_cycles::no_mshrs     no_value                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46667                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.demand_mshr_misses                   0                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses                  0                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.demand_mshr_miss_latency             0                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.demand_mshr_miss_rate::0      no_value                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             0                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.iocache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           46667                       # number of writebacks
+system.iocache.writebacks::total                46667                       # number of writebacks
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -214,7 +179,8 @@ system.pc.south_bridge.ide.disks1.dma_write_txs            1
 system.cpu.numCycles                      10224086531                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        409133277                       # Number of instructions executed
+system.cpu.committedInsts                   199813913                       # Number of instructions committed
+system.cpu.committedOps                     409133277                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             374297244                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -240,47 +206,30 @@ system.cpu.icache.total_refs                243365777                       # To
 system.cpu.icache.sampled_refs                 791307                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 307.549127                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle           148763105500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.627676                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.997320                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0           243365777                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     510.627676                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.997320                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.997320                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    243365777                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       243365777                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0            243365777                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst     243365777                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total        243365777                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0           243365777                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst    243365777                       # number of overall hits
 system.cpu.icache.overall_hits::total       243365777                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            791314                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       791314                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        791314                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             791314                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       791314                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         791314                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            791314                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       791314                       # number of overall misses
 system.cpu.icache.overall_misses::total        791314                       # number of overall misses
-system.cpu.icache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0       244157091                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::cpu.inst    244157091                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    244157091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0        244157091                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst    244157091                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total    244157091                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0       244157091                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    244157091                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    244157091                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.003241                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.003241                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.003241                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.003241                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.003241                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.003241                       # miss rate for overall accesses
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -289,26 +238,8 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      809                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks          809                       # number of writebacks
+system.cpu.icache.writebacks::total               809                       # number of writebacks
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         3435                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        3.021701                       # Cycle average of tags in use
@@ -316,51 +247,34 @@ system.cpu.itb_walker_cache.total_refs           7940                       # To
 system.cpu.itb_walker_cache.sampled_refs         3444                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.avg_refs         2.305459                       # Average number of references to valid blocks.
 system.cpu.itb_walker_cache.warmup_cycle 5105275407500                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     3.021701                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.188856                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1         7947                       # number of ReadReq hits
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.021701                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.188856                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.188856                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7947                       # number of ReadReq hits
 system.cpu.itb_walker_cache.ReadReq_hits::total         7947                       # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1            2                       # number of WriteReq hits
+system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1         7949                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7949                       # number of demand (read+write) hits
 system.cpu.itb_walker_cache.demand_hits::total         7949                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1         7949                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7949                       # number of overall hits
 system.cpu.itb_walker_cache.overall_hits::total         7949                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         4278                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4278                       # number of ReadReq misses
 system.cpu.itb_walker_cache.ReadReq_misses::total         4278                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         4278                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4278                       # number of demand (read+write) misses
 system.cpu.itb_walker_cache.demand_misses::total         4278                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         4278                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4278                       # number of overall misses
 system.cpu.itb_walker_cache.overall_misses::total         4278                       # number of overall misses
-system.cpu.itb_walker_cache.demand_miss_latency            0                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency            0                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        12225                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12225                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.ReadReq_accesses::total        12225                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1            2                       # number of WriteReq accesses(hits+misses)
+system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        12227                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12227                       # number of demand (read+write) accesses
 system.cpu.itb_walker_cache.demand_accesses::total        12227                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        12227                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12227                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12227                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.349939                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.349881                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.349881                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.349939                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.349881                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.349881                       # miss rate for overall accesses
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -369,26 +283,8 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks            518                       # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.demand_mshr_misses            0                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses            0                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0     no_value                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.itb_walker_cache.writebacks::writebacks          518                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          518                       # number of writebacks
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.replacements         7755                       # number of replacements
 system.cpu.dtb_walker_cache.tagsinuse        5.010998                       # Cycle average of tags in use
@@ -396,47 +292,30 @@ system.cpu.dtb_walker_cache.total_refs          12854                       # To
 system.cpu.dtb_walker_cache.sampled_refs         7767                       # Sample count of references to valid blocks.
 system.cpu.dtb_walker_cache.avg_refs         1.654950                       # Average number of references to valid blocks.
 system.cpu.dtb_walker_cache.warmup_cycle 5101232849000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1     5.010998                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.313187                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1        12875                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.010998                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.313187                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.313187                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        12875                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.ReadReq_hits::total        12875                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1        12875                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        12875                       # number of demand (read+write) hits
 system.cpu.dtb_walker_cache.demand_hits::total        12875                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1        12875                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        12875                       # number of overall hits
 system.cpu.dtb_walker_cache.overall_hits::total        12875                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1         8933                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8933                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.ReadReq_misses::total         8933                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1         8933                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8933                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.demand_misses::total         8933                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1         8933                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8933                       # number of overall misses
 system.cpu.dtb_walker_cache.overall_misses::total         8933                       # number of overall misses
-system.cpu.dtb_walker_cache.demand_miss_latency            0                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency            0                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1        21808                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21808                       # number of ReadReq accesses(hits+misses)
 system.cpu.dtb_walker_cache.ReadReq_accesses::total        21808                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1        21808                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21808                       # number of demand (read+write) accesses
 system.cpu.dtb_walker_cache.demand_accesses::total        21808                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1        21808                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21808                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21808                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.409620                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.409620                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.409620                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0     no_value                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.409620                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.409620                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.409620                       # miss rate for overall accesses
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -445,26 +324,8 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks           2517                       # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.demand_mshr_misses            0                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses            0                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0     no_value                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0     no_value                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dtb_walker_cache.writebacks::writebacks         2517                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2517                       # number of writebacks
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1621277                       # number of replacements
 system.cpu.dcache.tagsinuse                511.999417                       # Cycle average of tags in use
@@ -472,54 +333,37 @@ system.cpu.dcache.total_refs                 20142220                       # To
 system.cpu.dcache.sampled_refs                1621789                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  12.419754                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                7549500                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.999417                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999999                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            12057024                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.999417                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999999                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     12057024                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        12057024                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            8082938                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8082938                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        8082938                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             20139962                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      20139962                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         20139962                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            20139962                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     20139962                       # number of overall hits
 system.cpu.dcache.overall_hits::total        20139962                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1308207                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1308207                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1308207                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           315850                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       315850                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       315850                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            1624057                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      1624057                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        1624057                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           1624057                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      1624057                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1624057                       # number of overall misses
-system.cpu.dcache.demand_miss_latency               0                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency              0                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13365231                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     13365231                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     13365231                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8398788                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8398788                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      8398788                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         21764019                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     21764019                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     21764019                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        21764019                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21764019                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21764019                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.097881                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.037607                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.074621                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.074621                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.demand_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1     no_value                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total     no_value                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.097881                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037607                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.074621                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.074621                       # miss rate for overall accesses
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -528,26 +372,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1525559                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.demand_mshr_misses                0                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses               0                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.demand_mshr_miss_rate::0            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     no_value                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     no_value                       # mshr miss rate for overall accesses
-system.cpu.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1525559                       # number of writebacks
+system.cpu.dcache.writebacks::total           1525559                       # number of writebacks
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index e3a339662040cc3ad02adb0b8585ed63cec1d2ff..baa9c805bdb1042031e4c748396a8a9ffc997725 100644 (file)
@@ -1,15 +1,15 @@
 [root]
 type=Root
 children=system
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobridge iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
 acpi_description_table_pointer=system.acpi_description_table_pointer
-boot_cpu_frequency=500
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
 e820_table=system.e820_table
 init_param=0
@@ -50,6 +50,17 @@ oem_id=
 oem_revision=0
 oem_table_id=
 
+[system.apicbridge]
+type=Bridge
+delay=50000
+nack_delay=4000
+ranges=11529215046068469760:11529215046068473855
+req_size=16
+resp_size=16
+write_ack=false
+master=system.membus.port[2]
+slave=system.iobus.port[1]
+
 [system.bridge]
 type=Bridge
 delay=50000
@@ -86,6 +97,7 @@ profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
+workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
@@ -100,20 +112,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -143,20 +148,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -175,20 +173,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -201,7 +192,6 @@ type=X86LocalApic
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=1000
-platform=system.pc
 system=system
 int_port=system.membus.port[7]
 pio=system.membus.port[6]
@@ -228,20 +218,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -615,17 +598,6 @@ subtractive_decode=true
 type=IntrControl
 sys=system
 
-[system.iobridge]
-type=Bridge
-delay=50000
-nack_delay=4000
-ranges=11529215046068469760:11529215046068473855
-req_size=16
-resp_size=16
-write_ack=false
-master=system.membus.port[2]
-slave=system.iobus.port[1]
-
 [system.iobus]
 type=Bus
 block_size=64
@@ -635,7 +607,7 @@ header_cycles=1
 use_default_range=true
 width=64
 default=system.pc.pciconfig.pio
-port=system.bridge.master system.iobridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
+port=system.bridge.master system.apicbridge.slave system.pc.south_bridge.cmos.pio system.pc.south_bridge.dma1.pio system.pc.south_bridge.ide.pio system.pc.south_bridge.ide.config system.pc.south_bridge.ide.dma system.pc.south_bridge.keyboard.pio system.pc.south_bridge.pic1.pio system.pc.south_bridge.pic2.pio system.pc.south_bridge.pit.pio system.pc.south_bridge.speaker.pio system.pc.south_bridge.io_apic.pio system.pc.south_bridge.io_apic.int_port system.pc.i_dont_exist.pio system.pc.behind_pci.pio system.pc.com_1.pio system.pc.fake_com_2.pio system.pc.fake_com_3.pio system.pc.fake_com_4.pio system.pc.fake_floppy.pio system.iocache.cpu_side
 
 [system.iocache]
 type=BaseCache
@@ -648,20 +620,13 @@ is_top_level=false
 latency=50000
 max_miss_count=0
 mshrs=20
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=500000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=1024
 subblock_size=0
+system=system
 tgts_per_mshr=12
 trace_addr=0
 two_queue=false
@@ -680,20 +645,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
@@ -711,7 +669,7 @@ header_cycles=1
 use_default_range=false
 width=64
 default=system.membus.badaddr_responder.pio
-port=system.physmem.port[0] system.bridge.slave system.iobridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
+port=system.physmem.port[0] system.bridge.slave system.apicbridge.master system.system_port system.iocache.mem_side system.l2c.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.membus.badaddr_responder]
 type=IsaFake
@@ -719,7 +677,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -742,7 +699,6 @@ fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -783,7 +739,6 @@ fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -800,7 +755,6 @@ fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -817,7 +771,6 @@ fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=1000
 pio_size=8
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -834,7 +787,6 @@ fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=1000
 pio_size=2
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -851,7 +803,6 @@ fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=1000
 pio_size=1
-platform=system.pc
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -891,7 +842,6 @@ children=int_pin
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=1000
-platform=system.pc
 system=system
 time=Sun Jan  1 00:00:00 2012
 pio=system.iobus.port[2]
@@ -903,7 +853,6 @@ type=X86IntSourcePin
 type=I8237
 pio_addr=9223372036854775808
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[3]
 
@@ -1088,7 +1037,6 @@ external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
 pio_latency=1000
-platform=system.pc
 system=system
 int_port=system.iobus.port[13]
 pio=system.iobus.port[12]
@@ -1102,7 +1050,6 @@ keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
 mouse_int_pin=system.pc.south_bridge.keyboard.mouse_int_pin
 pio_addr=0
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[7]
 
@@ -1119,7 +1066,6 @@ mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
 pio_latency=1000
-platform=system.pc
 slave=system.pc.south_bridge.pic2
 system=system
 pio=system.iobus.port[8]
@@ -1134,7 +1080,6 @@ mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
 pio_latency=1000
-platform=system.pc
 slave=Null
 system=system
 pio=system.iobus.port[9]
@@ -1148,7 +1093,6 @@ children=int_pin
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[10]
 
@@ -1160,7 +1104,6 @@ type=PcSpeaker
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=1000
-platform=system.pc
 system=system
 pio=system.iobus.port[11]
 
index 5dde537a2d9310de1d35e89e5b2c3f4f9c1bb9be..9ff593dd3928964fa2719fb587f6ac52e77092af 100755 (executable)
@@ -1,13 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:12:17
-gem5 started Jan 23 2012 04:24:49
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:06:52
 gem5 executing on zizzer
-command line: build/X86_FS/gem5.opt -d build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86_FS/tests/opt/quick/10.linux-boot/x86/linux/pc-simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/fast/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 warning: add_child('terminal'): child 'terminal' already has parent
 Global frequency set at 1000000000000 ticks per second
-      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 5195470393000 because m5_exit instruction encountered
index c4a248e5e69201fbc65eda8b8f0e3eae2d040329..6ded30fe7bf16ed2e21cd82f21cef42265eccde7 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  5.195470                       # Nu
 sim_ticks                                5195470393000                       # Number of ticks simulated
 final_tick                               5195470393000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1681123                       # Simulator instruction rate (inst/s)
-host_tick_rate                            32940960656                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 349824                       # Number of bytes of host memory used
-host_seconds                                   157.72                       # Real time elapsed on the host
-sim_insts                                   265147881                       # Number of instructions simulated
+host_inst_rate                                1225094                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2351489                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            46076516791                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 346880                       # Number of bytes of host memory used
+host_seconds                                   112.76                       # Real time elapsed on the host
+sim_insts                                   138138472                       # Number of instructions simulated
+sim_ops                                     265147881                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                    13764096                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                 974400                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                 10427072                       # Number of bytes written to this memory
@@ -25,84 +27,125 @@ system.l2c.total_refs                         3363370                       # To
 system.l2c.sampled_refs                        168244                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                         19.991025                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                  7910.895776                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                 23478.999694                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.120711                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.358261                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                    2047882                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                       9561                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks        23478.740830                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.dtb.walker        0.248367                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.itb.walker        0.010497                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.inst           1900.597036                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu.data           6010.298740                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.358257                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.dtb.walker       0.000004                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.itb.walker       0.000000                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.inst             0.029001                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu.data             0.091710                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.478972                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu.dtb.walker          6528                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.itb.walker          3033                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.inst              773419                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu.data             1274463                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                2057443                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                  1534567                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks         1534567                       # number of Writeback hits
 system.l2c.Writeback_hits::total              1534567                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     320                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu.data              320                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                 320                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                   192958                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu.data            192958                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total               192958                       # number of ReadExReq hits
-system.l2c.demand_hits::0                     2240840                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                        9561                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.dtb.walker           6528                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.itb.walker           3033                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.inst               773419                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu.data              1467421                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                 2250401                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                    2240840                       # number of overall hits
-system.l2c.overall_hits::1                       9561                       # number of overall hits
+system.l2c.overall_hits::cpu.dtb.walker          6528                       # number of overall hits
+system.l2c.overall_hits::cpu.itb.walker          3033                       # number of overall hits
+system.l2c.overall_hits::cpu.inst              773419                       # number of overall hits
+system.l2c.overall_hits::cpu.data             1467421                       # number of overall hits
 system.l2c.overall_hits::total                2250401                       # number of overall hits
-system.l2c.ReadReq_misses::0                    50807                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       23                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.dtb.walker           13                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.itb.walker           10                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.inst             15226                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu.data             35581                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                50830                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  1369                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu.data           1369                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total              1369                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                 120168                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu.data          120168                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total             120168                       # number of ReadExReq misses
-system.l2c.demand_misses::0                    170975                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        23                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.dtb.walker           13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.itb.walker           10                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.inst              15226                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu.data             155749                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                170998                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                   170975                       # number of overall misses
-system.l2c.overall_misses::1                       23                       # number of overall misses
+system.l2c.overall_misses::cpu.dtb.walker           13                       # number of overall misses
+system.l2c.overall_misses::cpu.itb.walker           10                       # number of overall misses
+system.l2c.overall_misses::cpu.inst             15226                       # number of overall misses
+system.l2c.overall_misses::cpu.data            155749                       # number of overall misses
 system.l2c.overall_misses::total               170998                       # number of overall misses
-system.l2c.ReadReq_miss_latency            2656122500                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency           33778000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          6249324500                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             8905447000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            8905447000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                2098689                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                   9584                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu.dtb.walker       676000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.itb.walker       520000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.inst    791868000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu.data   1863058500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2656122500                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu.data     33778000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total     33778000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu.data   6249324500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   6249324500                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu.dtb.walker       676000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.itb.walker       520000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.inst    791868000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu.data   8112383000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      8905447000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu.dtb.walker       676000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.itb.walker       520000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.inst    791868000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu.data   8112383000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     8905447000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu.dtb.walker         6541                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.itb.walker         3043                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.inst          788645                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu.data         1310044                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total            2108273                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0              1534567                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks      1534567                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total          1534567                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                1689                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu.data         1689                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total            1689                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0               313126                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu.data        313126                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total           313126                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                 2411815                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                    9584                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.dtb.walker         6541                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.itb.walker         3043                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.inst           788645                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu.data          1623170                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total             2421399                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                2411815                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                   9584                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.dtb.walker         6541                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.itb.walker         3043                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.inst          788645                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu.data         1623170                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total            2421399                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.024209                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.002400                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.026609                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.810539                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.383769                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.070891                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.002400                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.073290                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.070891                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.002400                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.073290                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   52278.672230                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   115483586.956522                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 115535865.628752                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 24673.484295                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1          inf                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total          inf                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 52004.897310                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1          inf                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total          inf                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    52086.252376                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    387193347.826087                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 387245434.078463                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   52086.252376                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   387193347.826087                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 387245434.078463                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.itb.walker     0.003286                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.inst       0.019307                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu.data       0.027160                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu.data     0.810539                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu.data     0.383769                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.itb.walker     0.003286                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.inst        0.019307                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu.data        0.095954                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu.dtb.walker     0.001987                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.itb.walker     0.003286                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.inst       0.019307                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu.data       0.095954                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu.dtb.walker        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.itb.walker        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.inst 52007.618547                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu.data 52361.049436                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu.data 24673.484295                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu.data 52004.897310                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.inst 52007.618547                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu.data 52086.260586                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.dtb.walker        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.itb.walker        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.inst 52007.618547                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu.data 52086.260586                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -111,48 +154,83 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                          116255                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  50830                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                1369                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses               120168                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                  170998                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                 170998                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       2046144000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency      55109000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     4807305000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        6853449000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       6853449000                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency  56051785000                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1218050000                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency  57269835000                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.024220                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         5.303631                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     5.327851                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      0.810539                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1           inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total          inf                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       0.383769                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1            inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.070900                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1         17.842028                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total     17.912929                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.070900                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1        17.842028                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total    17.912929                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40254.652764                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 40254.930606                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40004.868185                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40079.117884                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40079.117884                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks              116255                       # number of writebacks
+system.l2c.writebacks::total                   116255                       # number of writebacks
+system.l2c.ReadReq_mshr_misses::cpu.dtb.walker           13                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.itb.walker           10                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.inst        15226                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu.data        35581                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           50830                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu.data         1369                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total         1369                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu.data       120168                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total        120168                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu.dtb.walker           13                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.itb.walker           10                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.inst         15226                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu.data        155749                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total           170998                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu.dtb.walker           13                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.itb.walker           10                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.inst        15226                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu.data       155749                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total          170998                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu.dtb.walker       520000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.itb.walker       400000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.inst    609142000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu.data   1436082000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   2046144000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu.data     55109000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total     55109000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu.data   4807305000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   4807305000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.dtb.walker       520000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.itb.walker       400000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.inst    609142000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu.data   6243387000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   6853449000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.dtb.walker       520000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.itb.walker       400000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.inst    609142000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu.data   6243387000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   6853449000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data  56051785000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total  56051785000                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data   1218050000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1218050000                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu.data  57269835000                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total  57269835000                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu.data     0.027160                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu.data     0.810539                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu.data     0.383769                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu.data     0.095954                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu.dtb.walker     0.001987                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.itb.walker     0.003286                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.inst     0.019307                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu.data     0.095954                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40360.922965                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40254.930606                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40004.868185                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu.data 40086.209221                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40006.699067                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu.data 40086.209221                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.iocache.replacements                     47510                       # number of replacements
 system.iocache.tagsinuse                     0.120586                       # Cycle average of tags in use
@@ -160,58 +238,41 @@ system.iocache.total_refs                           0                       # To
 system.iocache.sampled_refs                     47526                       # Sample count of references to valid blocks.
 system.iocache.avg_refs                             0                       # Average number of references to valid blocks.
 system.iocache.warmup_cycle              5048756072000                       # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::1                 0.120586                       # Average occupied blocks per context
-system.iocache.occ_percent::1                0.007537                       # Average percentage of cache occupancy
-system.iocache.demand_hits::0                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::1                       0                       # number of demand (read+write) hits
-system.iocache.demand_hits::total                   0                       # number of demand (read+write) hits
-system.iocache.overall_hits::0                      0                       # number of overall hits
-system.iocache.overall_hits::1                      0                       # number of overall hits
-system.iocache.overall_hits::total                  0                       # number of overall hits
-system.iocache.ReadReq_misses::1                  844                       # number of ReadReq misses
+system.iocache.occ_blocks::pc.south_bridge.ide     0.120586                       # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide     0.007537                       # Average percentage of cache occupancy
+system.iocache.occ_percent::total            0.007537                       # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide          844                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              844                       # number of ReadReq misses
-system.iocache.WriteReq_misses::1               46720                       # number of WriteReq misses
+system.iocache.WriteReq_misses::pc.south_bridge.ide        46720                       # number of WriteReq misses
 system.iocache.WriteReq_misses::total           46720                       # number of WriteReq misses
-system.iocache.demand_misses::0                     0                       # number of demand (read+write) misses
-system.iocache.demand_misses::1                 47564                       # number of demand (read+write) misses
+system.iocache.demand_misses::pc.south_bridge.ide        47564                       # number of demand (read+write) misses
 system.iocache.demand_misses::total             47564                       # number of demand (read+write) misses
-system.iocache.overall_misses::0                    0                       # number of overall misses
-system.iocache.overall_misses::1                47564                       # number of overall misses
+system.iocache.overall_misses::pc.south_bridge.ide        47564                       # number of overall misses
 system.iocache.overall_misses::total            47564                       # number of overall misses
-system.iocache.ReadReq_miss_latency         106575932                       # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency       6391379160                       # number of WriteReq miss cycles
-system.iocache.demand_miss_latency         6497955092                       # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency        6497955092                       # number of overall miss cycles
-system.iocache.ReadReq_accesses::1                844                       # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_miss_latency::pc.south_bridge.ide    106575932                       # number of ReadReq miss cycles
+system.iocache.ReadReq_miss_latency::total    106575932                       # number of ReadReq miss cycles
+system.iocache.WriteReq_miss_latency::pc.south_bridge.ide   6391379160                       # number of WriteReq miss cycles
+system.iocache.WriteReq_miss_latency::total   6391379160                       # number of WriteReq miss cycles
+system.iocache.demand_miss_latency::pc.south_bridge.ide   6497955092                       # number of demand (read+write) miss cycles
+system.iocache.demand_miss_latency::total   6497955092                       # number of demand (read+write) miss cycles
+system.iocache.overall_miss_latency::pc.south_bridge.ide   6497955092                       # number of overall miss cycles
+system.iocache.overall_miss_latency::total   6497955092                       # number of overall miss cycles
+system.iocache.ReadReq_accesses::pc.south_bridge.ide          844                       # number of ReadReq accesses(hits+misses)
 system.iocache.ReadReq_accesses::total            844                       # number of ReadReq accesses(hits+misses)
-system.iocache.WriteReq_accesses::1             46720                       # number of WriteReq accesses(hits+misses)
+system.iocache.WriteReq_accesses::pc.south_bridge.ide        46720                       # number of WriteReq accesses(hits+misses)
 system.iocache.WriteReq_accesses::total         46720                       # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::0                   0                       # number of demand (read+write) accesses
-system.iocache.demand_accesses::1               47564                       # number of demand (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide        47564                       # number of demand (read+write) accesses
 system.iocache.demand_accesses::total           47564                       # number of demand (read+write) accesses
-system.iocache.overall_accesses::0                  0                       # number of overall (read+write) accesses
-system.iocache.overall_accesses::1              47564                       # number of overall (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide        47564                       # number of overall (read+write) accesses
 system.iocache.overall_accesses::total          47564                       # number of overall (read+write) accesses
-system.iocache.ReadReq_miss_rate::1                 1                       # miss rate for ReadReq accesses
-system.iocache.WriteReq_miss_rate::1                1                       # miss rate for WriteReq accesses
-system.iocache.demand_miss_rate::0           no_value                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::1                  1                       # miss rate for demand accesses
-system.iocache.demand_miss_rate::total       no_value                       # miss rate for demand accesses
-system.iocache.overall_miss_rate::0          no_value                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::1                 1                       # miss rate for overall accesses
-system.iocache.overall_miss_rate::total      no_value                       # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::1 126274.800948                       # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::0          inf                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::1 136801.779966                       # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::1 136614.983853                       # average overall miss latency
-system.iocache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::1 136614.983853                       # average overall miss latency
-system.iocache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.iocache.ReadReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for ReadReq accesses
+system.iocache.WriteReq_miss_rate::pc.south_bridge.ide            1                       # miss rate for WriteReq accesses
+system.iocache.demand_miss_rate::pc.south_bridge.ide            1                       # miss rate for demand accesses
+system.iocache.overall_miss_rate::pc.south_bridge.ide            1                       # miss rate for overall accesses
+system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 126274.800948                       # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 136801.779966                       # average WriteReq miss latency
+system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 136614.983853                       # average overall miss latency
+system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 136614.983853                       # average overall miss latency
 system.iocache.blocked_cycles::no_mshrs      69564644                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                11299                       # number of cycles access was blocked
@@ -220,38 +281,32 @@ system.iocache.avg_blocked_cycles::no_mshrs  6156.708027                       #
 system.iocache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.iocache.fast_writes                          0                       # number of fast writes performed
 system.iocache.cache_copies                         0                       # number of cache copies performed
-system.iocache.writebacks                       46668                       # number of writebacks
-system.iocache.demand_mshr_hits                     0                       # number of demand (read+write) MSHR hits
-system.iocache.overall_mshr_hits                    0                       # number of overall MSHR hits
-system.iocache.ReadReq_mshr_misses                844                       # number of ReadReq MSHR misses
-system.iocache.WriteReq_mshr_misses             46720                       # number of WriteReq MSHR misses
-system.iocache.demand_mshr_misses               47564                       # number of demand (read+write) MSHR misses
-system.iocache.overall_mshr_misses              47564                       # number of overall MSHR misses
-system.iocache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.iocache.ReadReq_mshr_miss_latency     62666978                       # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency   3961676998                       # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency    4024343976                       # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency   4024343976                       # number of overall MSHR miss cycles
-system.iocache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::1            1                       # mshr miss rate for ReadReq accesses
-system.iocache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.iocache.WriteReq_mshr_miss_rate::0          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::1            1                       # mshr miss rate for WriteReq accesses
-system.iocache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.iocache.demand_mshr_miss_rate::0           inf                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::1             1                       # mshr miss rate for demand accesses
-system.iocache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.iocache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::1            1                       # mshr miss rate for overall accesses
-system.iocache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency 74249.973934                       # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency 84796.168622                       # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency 84609.031536                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency 84609.031536                       # average overall mshr miss latency
-system.iocache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.iocache.mshr_cap_events                      0                       # number of times MSHR cap was activated
-system.iocache.soft_prefetch_mshr_full              0                       # number of mshr full events for SW prefetching instrutions
+system.iocache.writebacks::writebacks           46668                       # number of writebacks
+system.iocache.writebacks::total                46668                       # number of writebacks
+system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide          844                       # number of ReadReq MSHR misses
+system.iocache.ReadReq_mshr_misses::total          844                       # number of ReadReq MSHR misses
+system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide        46720                       # number of WriteReq MSHR misses
+system.iocache.WriteReq_mshr_misses::total        46720                       # number of WriteReq MSHR misses
+system.iocache.demand_mshr_misses::pc.south_bridge.ide        47564                       # number of demand (read+write) MSHR misses
+system.iocache.demand_mshr_misses::total        47564                       # number of demand (read+write) MSHR misses
+system.iocache.overall_mshr_misses::pc.south_bridge.ide        47564                       # number of overall MSHR misses
+system.iocache.overall_mshr_misses::total        47564                       # number of overall MSHR misses
+system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide     62666978                       # number of ReadReq MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_latency::total     62666978                       # number of ReadReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide   3961676998                       # number of WriteReq MSHR miss cycles
+system.iocache.WriteReq_mshr_miss_latency::total   3961676998                       # number of WriteReq MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide   4024343976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.demand_mshr_miss_latency::total   4024343976                       # number of demand (read+write) MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide   4024343976                       # number of overall MSHR miss cycles
+system.iocache.overall_mshr_miss_latency::total   4024343976                       # number of overall MSHR miss cycles
+system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for ReadReq accesses
+system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for WriteReq accesses
+system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for demand accesses
+system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide            1                       # mshr miss rate for overall accesses
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 74249.973934                       # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 84796.168622                       # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536                       # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 84609.031536                       # average overall mshr miss latency
 system.iocache.no_allocate_misses                   0                       # Number of misses that were no-allocate
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        34816                       # Number of bytes transfered via DMA reads (not PRD).
@@ -268,7 +323,8 @@ system.pc.south_bridge.ide.disks1.dma_write_txs            1
 system.cpu.numCycles                      10390940786                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                        265147881                       # Number of instructions executed
+system.cpu.committedInsts                   138138472                       # Number of instructions committed
+system.cpu.committedOps                     265147881                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses             249556386                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -294,51 +350,39 @@ system.cpu.icache.total_refs                158433932                       # To
 system.cpu.icache.sampled_refs                 788651                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                 200.892324                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle           160047116000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            510.361283                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.996799                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::0           158433932                       # number of ReadReq hits
+system.cpu.icache.occ_blocks::cpu.inst     510.361283                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.996799                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.996799                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst    158433932                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total       158433932                       # number of ReadReq hits
-system.cpu.icache.demand_hits::0            158433932                       # number of demand (read+write) hits
-system.cpu.icache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::cpu.inst     158433932                       # number of demand (read+write) hits
 system.cpu.icache.demand_hits::total        158433932                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits::0           158433932                       # number of overall hits
-system.cpu.icache.overall_hits::1                   0                       # number of overall hits
+system.cpu.icache.overall_hits::cpu.inst    158433932                       # number of overall hits
 system.cpu.icache.overall_hits::total       158433932                       # number of overall hits
-system.cpu.icache.ReadReq_misses::0            788658                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::cpu.inst       788658                       # number of ReadReq misses
 system.cpu.icache.ReadReq_misses::total        788658                       # number of ReadReq misses
-system.cpu.icache.demand_misses::0             788658                       # number of demand (read+write) misses
-system.cpu.icache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::cpu.inst       788658                       # number of demand (read+write) misses
 system.cpu.icache.demand_misses::total         788658                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses::0            788658                       # number of overall misses
-system.cpu.icache.overall_misses::1                 0                       # number of overall misses
+system.cpu.icache.overall_misses::cpu.inst       788658                       # number of overall misses
 system.cpu.icache.overall_misses::total        788658                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency    11681762500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency     11681762500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency    11681762500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::0       159222590                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_miss_latency::cpu.inst  11681762500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total  11681762500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst  11681762500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total  11681762500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst  11681762500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total  11681762500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst    159222590                       # number of ReadReq accesses(hits+misses)
 system.cpu.icache.ReadReq_accesses::total    159222590                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses::0        159222590                       # number of demand (read+write) accesses
-system.cpu.icache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::cpu.inst    159222590                       # number of demand (read+write) accesses
 system.cpu.icache.demand_accesses::total    159222590                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses::0       159222590                       # number of overall (read+write) accesses
-system.cpu.icache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst    159222590                       # number of overall (read+write) accesses
 system.cpu.icache.overall_accesses::total    159222590                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate::0       0.004953                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate::0        0.004953                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.icache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate::0       0.004953                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.icache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 14812.203135                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 14812.203135                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 14812.203135                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.004953                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.004953                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.004953                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14812.203135                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 14812.203135                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 14812.203135                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -347,32 +391,26 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                      805                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses          788658                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses           788658                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses          788658                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency   9314744000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency   9314744000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency   9314744000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.004953                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.004953                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.004953                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 11810.878733                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 11810.878733                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 11810.878733                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.writebacks::writebacks          805                       # number of writebacks
+system.cpu.icache.writebacks::total               805                       # number of writebacks
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst       788658                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total       788658                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst       788658                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total       788658                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst       788658                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total       788658                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   9314744000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total   9314744000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst   9314744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total   9314744000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst   9314744000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total   9314744000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.004953                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11810.878733                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.itb_walker_cache.replacements         3754                       # number of replacements
 system.cpu.itb_walker_cache.tagsinuse        3.070606                       # Cycle average of tags in use
@@ -380,55 +418,43 @@ system.cpu.itb_walker_cache.total_refs           7549                       # To
 system.cpu.itb_walker_cache.sampled_refs         3765                       # Sample count of references to valid blocks.
 system.cpu.itb_walker_cache.avg_refs         2.005046                       # Average number of references to valid blocks.
 system.cpu.itb_walker_cache.warmup_cycle 5178573163000                       # Cycle when the warmup percentage was hit.
-system.cpu.itb_walker_cache.occ_blocks::1     3.070606                       # Average occupied blocks per context
-system.cpu.itb_walker_cache.occ_percent::1     0.191913                       # Average percentage of cache occupancy
-system.cpu.itb_walker_cache.ReadReq_hits::1         7619                       # number of ReadReq hits
+system.cpu.itb_walker_cache.occ_blocks::cpu.itb.walker     3.070606                       # Average occupied blocks per requestor
+system.cpu.itb_walker_cache.occ_percent::cpu.itb.walker     0.191913                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.occ_percent::total     0.191913                       # Average percentage of cache occupancy
+system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker         7619                       # number of ReadReq hits
 system.cpu.itb_walker_cache.ReadReq_hits::total         7619                       # number of ReadReq hits
-system.cpu.itb_walker_cache.WriteReq_hits::1            2                       # number of WriteReq hits
+system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker            2                       # number of WriteReq hits
 system.cpu.itb_walker_cache.WriteReq_hits::total            2                       # number of WriteReq hits
-system.cpu.itb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.demand_hits::1         7621                       # number of demand (read+write) hits
+system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker         7621                       # number of demand (read+write) hits
 system.cpu.itb_walker_cache.demand_hits::total         7621                       # number of demand (read+write) hits
-system.cpu.itb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.itb_walker_cache.overall_hits::1         7621                       # number of overall hits
+system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker         7621                       # number of overall hits
 system.cpu.itb_walker_cache.overall_hits::total         7621                       # number of overall hits
-system.cpu.itb_walker_cache.ReadReq_misses::1         4602                       # number of ReadReq misses
+system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker         4602                       # number of ReadReq misses
 system.cpu.itb_walker_cache.ReadReq_misses::total         4602                       # number of ReadReq misses
-system.cpu.itb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.demand_misses::1         4602                       # number of demand (read+write) misses
+system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker         4602                       # number of demand (read+write) misses
 system.cpu.itb_walker_cache.demand_misses::total         4602                       # number of demand (read+write) misses
-system.cpu.itb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.itb_walker_cache.overall_misses::1         4602                       # number of overall misses
+system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker         4602                       # number of overall misses
 system.cpu.itb_walker_cache.overall_misses::total         4602                       # number of overall misses
-system.cpu.itb_walker_cache.ReadReq_miss_latency     50817000                       # number of ReadReq miss cycles
-system.cpu.itb_walker_cache.demand_miss_latency     50817000                       # number of demand (read+write) miss cycles
-system.cpu.itb_walker_cache.overall_miss_latency     50817000                       # number of overall miss cycles
-system.cpu.itb_walker_cache.ReadReq_accesses::1        12221                       # number of ReadReq accesses(hits+misses)
+system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker     50817000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.ReadReq_miss_latency::total     50817000                       # number of ReadReq miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker     50817000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.demand_miss_latency::total     50817000                       # number of demand (read+write) miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker     50817000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.overall_miss_latency::total     50817000                       # number of overall miss cycles
+system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker        12221                       # number of ReadReq accesses(hits+misses)
 system.cpu.itb_walker_cache.ReadReq_accesses::total        12221                       # number of ReadReq accesses(hits+misses)
-system.cpu.itb_walker_cache.WriteReq_accesses::1            2                       # number of WriteReq accesses(hits+misses)
+system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker            2                       # number of WriteReq accesses(hits+misses)
 system.cpu.itb_walker_cache.WriteReq_accesses::total            2                       # number of WriteReq accesses(hits+misses)
-system.cpu.itb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.demand_accesses::1        12223                       # number of demand (read+write) accesses
+system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker        12223                       # number of demand (read+write) accesses
 system.cpu.itb_walker_cache.demand_accesses::total        12223                       # number of demand (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.overall_accesses::1        12223                       # number of overall (read+write) accesses
+system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker        12223                       # number of overall (read+write) accesses
 system.cpu.itb_walker_cache.overall_accesses::total        12223                       # number of overall (read+write) accesses
-system.cpu.itb_walker_cache.ReadReq_miss_rate::1     0.376565                       # miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::1     0.376503                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::1     0.376503                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::1 11042.372881                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::1 11042.372881                       # average overall miss latency
-system.cpu.itb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::1 11042.372881                       # average overall miss latency
-system.cpu.itb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker     0.376565                       # miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker     0.376503                       # miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker     0.376503                       # miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 11042.372881                       # average ReadReq miss latency
+system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 11042.372881                       # average overall miss latency
+system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 11042.372881                       # average overall miss latency
 system.cpu.itb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.itb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -437,32 +463,26 @@ system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.itb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.itb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.itb_walker_cache.writebacks            826                       # number of writebacks
-system.cpu.itb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.itb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.itb_walker_cache.ReadReq_mshr_misses         4602                       # number of ReadReq MSHR misses
-system.cpu.itb_walker_cache.demand_mshr_misses         4602                       # number of demand (read+write) MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_misses         4602                       # number of overall MSHR misses
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency     37011000                       # number of ReadReq MSHR miss cycles
-system.cpu.itb_walker_cache.demand_mshr_miss_latency     37011000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_miss_latency     37011000                       # number of overall MSHR miss cycles
-system.cpu.itb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::1     0.376565                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::1     0.376503                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::1     0.376503                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency  8042.372881                       # average ReadReq mshr miss latency
-system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency  8042.372881                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency  8042.372881                       # average overall mshr miss latency
-system.cpu.itb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.itb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.itb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.itb_walker_cache.writebacks::writebacks          826                       # number of writebacks
+system.cpu.itb_walker_cache.writebacks::total          826                       # number of writebacks
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker         4602                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_misses::total         4602                       # number of ReadReq MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker         4602                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.demand_mshr_misses::total         4602                       # number of demand (read+write) MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker         4602                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.overall_mshr_misses::total         4602                       # number of overall MSHR misses
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker     37011000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total     37011000                       # number of ReadReq MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker     37011000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.demand_mshr_miss_latency::total     37011000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker     37011000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.overall_mshr_miss_latency::total     37011000                       # number of overall MSHR miss cycles
+system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.376565                       # mshr miss rate for ReadReq accesses
+system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker     0.376503                       # mshr miss rate for demand accesses
+system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker     0.376503                       # mshr miss rate for overall accesses
+system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average ReadReq mshr miss latency
+system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average overall mshr miss latency
+system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker  8042.372881                       # average overall mshr miss latency
 system.cpu.itb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dtb_walker_cache.replacements         7704                       # number of replacements
 system.cpu.dtb_walker_cache.tagsinuse        5.052403                       # Cycle average of tags in use
@@ -470,51 +490,39 @@ system.cpu.dtb_walker_cache.total_refs          13051                       # To
 system.cpu.dtb_walker_cache.sampled_refs         7716                       # Sample count of references to valid blocks.
 system.cpu.dtb_walker_cache.avg_refs         1.691420                       # Average number of references to valid blocks.
 system.cpu.dtb_walker_cache.warmup_cycle 5160674969000                       # Cycle when the warmup percentage was hit.
-system.cpu.dtb_walker_cache.occ_blocks::1     5.052403                       # Average occupied blocks per context
-system.cpu.dtb_walker_cache.occ_percent::1     0.315775                       # Average percentage of cache occupancy
-system.cpu.dtb_walker_cache.ReadReq_hits::1        13051                       # number of ReadReq hits
+system.cpu.dtb_walker_cache.occ_blocks::cpu.dtb.walker     5.052403                       # Average occupied blocks per requestor
+system.cpu.dtb_walker_cache.occ_percent::cpu.dtb.walker     0.315775                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.occ_percent::total     0.315775                       # Average percentage of cache occupancy
+system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker        13051                       # number of ReadReq hits
 system.cpu.dtb_walker_cache.ReadReq_hits::total        13051                       # number of ReadReq hits
-system.cpu.dtb_walker_cache.demand_hits::0            0                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.demand_hits::1        13051                       # number of demand (read+write) hits
+system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker        13051                       # number of demand (read+write) hits
 system.cpu.dtb_walker_cache.demand_hits::total        13051                       # number of demand (read+write) hits
-system.cpu.dtb_walker_cache.overall_hits::0            0                       # number of overall hits
-system.cpu.dtb_walker_cache.overall_hits::1        13051                       # number of overall hits
+system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker        13051                       # number of overall hits
 system.cpu.dtb_walker_cache.overall_hits::total        13051                       # number of overall hits
-system.cpu.dtb_walker_cache.ReadReq_misses::1         8896                       # number of ReadReq misses
+system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker         8896                       # number of ReadReq misses
 system.cpu.dtb_walker_cache.ReadReq_misses::total         8896                       # number of ReadReq misses
-system.cpu.dtb_walker_cache.demand_misses::0            0                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.demand_misses::1         8896                       # number of demand (read+write) misses
+system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker         8896                       # number of demand (read+write) misses
 system.cpu.dtb_walker_cache.demand_misses::total         8896                       # number of demand (read+write) misses
-system.cpu.dtb_walker_cache.overall_misses::0            0                       # number of overall misses
-system.cpu.dtb_walker_cache.overall_misses::1         8896                       # number of overall misses
+system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker         8896                       # number of overall misses
 system.cpu.dtb_walker_cache.overall_misses::total         8896                       # number of overall misses
-system.cpu.dtb_walker_cache.ReadReq_miss_latency    103895500                       # number of ReadReq miss cycles
-system.cpu.dtb_walker_cache.demand_miss_latency    103895500                       # number of demand (read+write) miss cycles
-system.cpu.dtb_walker_cache.overall_miss_latency    103895500                       # number of overall miss cycles
-system.cpu.dtb_walker_cache.ReadReq_accesses::1        21947                       # number of ReadReq accesses(hits+misses)
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker    103895500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.ReadReq_miss_latency::total    103895500                       # number of ReadReq miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker    103895500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.demand_miss_latency::total    103895500                       # number of demand (read+write) miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker    103895500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.overall_miss_latency::total    103895500                       # number of overall miss cycles
+system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker        21947                       # number of ReadReq accesses(hits+misses)
 system.cpu.dtb_walker_cache.ReadReq_accesses::total        21947                       # number of ReadReq accesses(hits+misses)
-system.cpu.dtb_walker_cache.demand_accesses::0            0                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.demand_accesses::1        21947                       # number of demand (read+write) accesses
+system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker        21947                       # number of demand (read+write) accesses
 system.cpu.dtb_walker_cache.demand_accesses::total        21947                       # number of demand (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::0            0                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.overall_accesses::1        21947                       # number of overall (read+write) accesses
+system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker        21947                       # number of overall (read+write) accesses
 system.cpu.dtb_walker_cache.overall_accesses::total        21947                       # number of overall (read+write) accesses
-system.cpu.dtb_walker_cache.ReadReq_miss_rate::1     0.405340                       # miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::0     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::1     0.405340                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::0     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::1     0.405340                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::0          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::1 11678.900629                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::1 11678.900629                       # average overall miss latency
-system.cpu.dtb_walker_cache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::0          inf                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::1 11678.900629                       # average overall miss latency
-system.cpu.dtb_walker_cache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker     0.405340                       # miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average ReadReq miss latency
+system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average overall miss latency
+system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 11678.900629                       # average overall miss latency
 system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dtb_walker_cache.blocked::no_mshrs            0                       # number of cycles access was blocked
@@ -523,32 +531,26 @@ system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dtb_walker_cache.fast_writes             0                       # number of fast writes performed
 system.cpu.dtb_walker_cache.cache_copies            0                       # number of cache copies performed
-system.cpu.dtb_walker_cache.writebacks           2985                       # number of writebacks
-system.cpu.dtb_walker_cache.demand_mshr_hits            0                       # number of demand (read+write) MSHR hits
-system.cpu.dtb_walker_cache.overall_mshr_hits            0                       # number of overall MSHR hits
-system.cpu.dtb_walker_cache.ReadReq_mshr_misses         8896                       # number of ReadReq MSHR misses
-system.cpu.dtb_walker_cache.demand_mshr_misses         8896                       # number of demand (read+write) MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_misses         8896                       # number of overall MSHR misses
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency     77207000                       # number of ReadReq MSHR miss cycles
-system.cpu.dtb_walker_cache.demand_mshr_miss_latency     77207000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_miss_latency     77207000                       # number of overall MSHR miss cycles
-system.cpu.dtb_walker_cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::0          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::1     0.405340                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::0          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::1     0.405340                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::0          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::1     0.405340                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency  8678.844424                       # average ReadReq mshr miss latency
-system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency  8678.844424                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency  8678.844424                       # average overall mshr miss latency
-system.cpu.dtb_walker_cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dtb_walker_cache.mshr_cap_events            0                       # number of times MSHR cap was activated
-system.cpu.dtb_walker_cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dtb_walker_cache.writebacks::writebacks         2985                       # number of writebacks
+system.cpu.dtb_walker_cache.writebacks::total         2985                       # number of writebacks
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker         8896                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total         8896                       # number of ReadReq MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker         8896                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.demand_mshr_misses::total         8896                       # number of demand (read+write) MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker         8896                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.overall_mshr_misses::total         8896                       # number of overall MSHR misses
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker     77207000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total     77207000                       # number of ReadReq MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker     77207000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total     77207000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker     77207000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total     77207000                       # number of overall MSHR miss cycles
+system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for ReadReq accesses
+system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for demand accesses
+system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker     0.405340                       # mshr miss rate for overall accesses
+system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average ReadReq mshr miss latency
+system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average overall mshr miss latency
+system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker  8678.844424                       # average overall mshr miss latency
 system.cpu.dtb_walker_cache.no_allocate_misses            0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                1623424                       # number of replacements
 system.cpu.dcache.tagsinuse                511.997312                       # Cycle average of tags in use
@@ -556,62 +558,49 @@ system.cpu.dcache.total_refs                 20011404                       # To
 system.cpu.dcache.sampled_refs                1623936                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  12.322779                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle               44345000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            511.997312                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.999995                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits::0            11977182                       # number of ReadReq hits
+system.cpu.dcache.occ_blocks::cpu.data     511.997312                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.999995                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data     11977182                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        11977182                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::0            8032009                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data      8032009                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total        8032009                       # number of WriteReq hits
-system.cpu.dcache.demand_hits::0             20009191                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::1                    0                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      20009191                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         20009191                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::0            20009191                       # number of overall hits
-system.cpu.dcache.overall_hits::1                   0                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     20009191                       # number of overall hits
 system.cpu.dcache.overall_hits::total        20009191                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::0           1310824                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data      1310824                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total       1310824                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::0           315344                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       315344                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       315344                       # number of WriteReq misses
-system.cpu.dcache.demand_misses::0            1626168                       # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::1                  0                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      1626168                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        1626168                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::0           1626168                       # number of overall misses
-system.cpu.dcache.overall_misses::1                 0                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      1626168                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1626168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency    19851809000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency    9514837000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency     29366646000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency    29366646000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::0        13288006                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_miss_latency::cpu.data  19851809000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total  19851809000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data   9514837000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total   9514837000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  29366646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total  29366646000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  29366646000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total  29366646000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data     13288006                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     13288006                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::0        8347353                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data      8347353                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total      8347353                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::0         21635359                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::1                0                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     21635359                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     21635359                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::0        21635359                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::1               0                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     21635359                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     21635359                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::0       0.098647                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::0      0.037778                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate::0        0.075163                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::1        no_value                       # miss rate for demand accesses
-system.cpu.dcache.demand_miss_rate::total     no_value                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::0       0.075163                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::1       no_value                       # miss rate for overall accesses
-system.cpu.dcache.overall_miss_rate::total     no_value                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 15144.526649                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::1          inf                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total          inf                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 30172.881044                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::1          inf                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total          inf                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 18058.802043                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 18058.802043                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1          inf                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total          inf                       # average overall miss latency
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.098647                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.037778                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.075163                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.075163                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15144.526649                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30172.881044                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 18058.802043                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 18058.802043                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -620,42 +609,41 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                  1529951                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses         1310824                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses         315344                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses          1626168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses         1626168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency  15919294500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency   8568794500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency  24488089000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency  24488089000                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency  75925324500                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency   1379728500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency  77305053000                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.098647                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::1          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total          inf                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.037778                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::1          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total          inf                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.075163                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total          inf                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.075163                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total          inf                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 12144.494227                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 27172.847747                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 15058.769451                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 15058.769451                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.writebacks::writebacks      1529951                       # number of writebacks
+system.cpu.dcache.writebacks::total           1529951                       # number of writebacks
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data      1310824                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total      1310824                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       315344                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total       315344                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data      1626168                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total      1626168                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data      1626168                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total      1626168                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data  15919294500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total  15919294500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data   8568794500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total   8568794500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  24488089000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total  24488089000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  24488089000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total  24488089000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data  75925324500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total  75925324500                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   1379728500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   1379728500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  77305053000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total  77305053000                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.098647                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.037778                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.075163                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.075163                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12144.494227                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27172.847747                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 15058.769451                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 15058.769451                       # average overall mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 4bff39dc1d66f5eb5b200b57fb7c9706541e54c2..7a0c1d8ae5eb122dee5f0f52a6b16b7e18a792c4 100644 (file)
@@ -64,6 +64,7 @@ simulate_inst_stalls=false
 system=drivesys
 tracer=drivesys.cpu.tracer
 width=1
+workload=
 dcache_port=drivesys.membus.port[4]
 icache_port=drivesys.membus.port[3]
 
@@ -165,7 +166,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -225,7 +225,6 @@ pio=drivesys.iobus.port[25]
 type=TsunamiCChip
 pio_addr=8803072344064
 pio_latency=1000
-platform=drivesys.tsunami
 system=drivesys
 tsunami=drivesys.tsunami
 pio=drivesys.iobus.port[1]
@@ -308,7 +307,6 @@ fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -325,7 +323,6 @@ fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -342,7 +339,6 @@ fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -359,7 +355,6 @@ fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -376,7 +371,6 @@ fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -393,7 +387,6 @@ fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -410,7 +403,6 @@ fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -427,7 +419,6 @@ fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -444,7 +435,6 @@ fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -461,7 +451,6 @@ fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -478,7 +467,6 @@ fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -495,7 +483,6 @@ fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -512,7 +499,6 @@ fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -529,7 +515,6 @@ fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -546,7 +531,6 @@ fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -563,7 +547,6 @@ fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -580,7 +563,6 @@ fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -597,7 +579,6 @@ fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -614,7 +595,6 @@ fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
-platform=drivesys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -630,7 +610,6 @@ type=BadDevice
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
-platform=drivesys.tsunami
 system=drivesys
 pio=drivesys.iobus.port[22]
 
@@ -695,7 +674,6 @@ type=TsunamiIO
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=1000
-platform=drivesys.tsunami
 system=drivesys
 time=Thu Jan  1 00:00:00 2009
 tsunami=drivesys.tsunami
@@ -706,7 +684,6 @@ pio=drivesys.iobus.port[23]
 type=TsunamiPChip
 pio_addr=8802535473152
 pio_latency=1000
-platform=drivesys.tsunami
 system=drivesys
 tsunami=drivesys.tsunami
 pio=drivesys.iobus.port[2]
@@ -746,6 +723,7 @@ int1=drivesys.tsunami.ethernet.interface
 [root]
 type=Root
 children=drivesys etherdump etherlink testsys
+full_system=true
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -816,6 +794,7 @@ simulate_inst_stalls=false
 system=testsys
 tracer=testsys.cpu.tracer
 width=1
+workload=
 dcache_port=testsys.membus.port[4]
 icache_port=testsys.membus.port[3]
 
@@ -917,7 +896,6 @@ fake_mem=false
 pio_addr=0
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=true
 ret_data16=65535
 ret_data32=4294967295
@@ -977,7 +955,6 @@ pio=testsys.iobus.port[25]
 type=TsunamiCChip
 pio_addr=8803072344064
 pio_latency=1000
-platform=testsys.tsunami
 system=testsys
 tsunami=testsys.tsunami
 pio=testsys.iobus.port[1]
@@ -1060,7 +1037,6 @@ fake_mem=false
 pio_addr=8796093677568
 pio_latency=1000
 pio_size=393216
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1077,7 +1053,6 @@ fake_mem=false
 pio_addr=8804615848432
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1094,7 +1069,6 @@ fake_mem=false
 pio_addr=8804615848304
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1111,7 +1085,6 @@ fake_mem=false
 pio_addr=8804615848569
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1128,7 +1101,6 @@ fake_mem=false
 pio_addr=8804615848451
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1145,7 +1117,6 @@ fake_mem=false
 pio_addr=8804615848515
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1162,7 +1133,6 @@ fake_mem=false
 pio_addr=8804615848579
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1179,7 +1149,6 @@ fake_mem=false
 pio_addr=8804615848643
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1196,7 +1165,6 @@ fake_mem=false
 pio_addr=8804615848707
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1213,7 +1181,6 @@ fake_mem=false
 pio_addr=8804615848771
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1230,7 +1197,6 @@ fake_mem=false
 pio_addr=8804615848835
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1247,7 +1213,6 @@ fake_mem=false
 pio_addr=8804615848899
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1264,7 +1229,6 @@ fake_mem=false
 pio_addr=8804615850617
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1281,7 +1245,6 @@ fake_mem=false
 pio_addr=8804615848891
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1298,7 +1261,6 @@ fake_mem=false
 pio_addr=8804615848816
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1315,7 +1277,6 @@ fake_mem=false
 pio_addr=8804615848696
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1332,7 +1293,6 @@ fake_mem=false
 pio_addr=8804615848936
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1349,7 +1309,6 @@ fake_mem=false
 pio_addr=8804615848680
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1366,7 +1325,6 @@ fake_mem=false
 pio_addr=8804615848944
 pio_latency=1000
 pio_size=8
-platform=testsys.tsunami
 ret_bad_addr=false
 ret_data16=65535
 ret_data32=4294967295
@@ -1382,7 +1340,6 @@ type=BadDevice
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=1000
-platform=testsys.tsunami
 system=testsys
 pio=testsys.iobus.port[22]
 
@@ -1447,7 +1404,6 @@ type=TsunamiIO
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=1000
-platform=testsys.tsunami
 system=testsys
 time=Thu Jan  1 00:00:00 2009
 tsunami=testsys.tsunami
@@ -1458,7 +1414,6 @@ pio=testsys.iobus.port[23]
 type=TsunamiPChip
 pio_addr=8802535473152
 pio_latency=1000
-platform=testsys.tsunami
 system=testsys
 tsunami=testsys.tsunami
 pio=testsys.iobus.port[2]
index d1174531ef3c6645711d23a820a6701bf4919772..ca565fefcf4c1e101665b5844d0a833c306c628d 100755 (executable)
@@ -1,13 +1,11 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:53:29
-gem5 started Jan 23 2012 04:23:10
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:10:02
 gem5 executing on zizzer
-command line: build/ALPHA_FS/gem5.opt -d build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA_FS/tests/opt/quick/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-      0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-      0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: kernel located at: /dist/m5/system/binaries/vmlinux
 info: Entering event queue @ 0.  Starting simulation...
index c3a385a95a7bf42b725c08737ecd5eba0b4000cb..4f6f5ddfe7c9543125491115d038705197791cec 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.200001                       # Nu
 sim_ticks                                200000789468                       # Number of ticks simulated
 final_tick                               4300236018046                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                              201516796                       # Simulator instruction rate (inst/s)
-host_tick_rate                           147427543497                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 479620                       # Number of bytes of host memory used
-host_seconds                                     1.36                       # Real time elapsed on the host
+host_inst_rate                              238054601                       # Simulator instruction rate (inst/s)
+host_op_rate                                238047910                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                           174152914765                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 476544                       # Number of bytes of host memory used
+host_seconds                                     1.15                       # Real time elapsed on the host
 sim_insts                                   273374833                       # Number of instructions simulated
+sim_ops                                     273374833                       # Number of ops (including micro ops) simulated
 testsys.physmem.bytes_read                   19104208                       # Number of bytes read from this memory
 testsys.physmem.bytes_inst_read              14257548                       # Number of instructions bytes read from this memory
 testsys.physmem.bytes_written                 3887982                       # Number of bytes written to this memory
@@ -66,7 +68,8 @@ testsys.cpu.itb.data_accesses                       0                       # DT
 testsys.cpu.numCycles                    199569460393                       # number of cpu cycles simulated
 testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
 testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.num_insts                         3560411                       # Number of instructions executed
+testsys.cpu.committedInsts                    3560411                       # Number of instructions committed
+testsys.cpu.committedOps                      3560411                       # Number of ops (including micro ops) committed
 testsys.cpu.num_int_alu_accesses              3348322                       # Number of integer alu accesses
 testsys.cpu.num_fp_alu_accesses                 17380                       # Number of float alu accesses
 testsys.cpu.num_func_calls                     107994                       # number of times a function call or return occured
@@ -258,7 +261,8 @@ drivesys.cpu.itb.data_accesses                      0                       # DT
 drivesys.cpu.numCycles                   199571362884                       # number of cpu cycles simulated
 drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
 drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.num_insts                        1958129                       # Number of instructions executed
+drivesys.cpu.committedInsts                   1958129                       # Number of instructions committed
+drivesys.cpu.committedOps                     1958129                       # Number of ops (including micro ops) committed
 drivesys.cpu.num_int_alu_accesses             1889973                       # Number of integer alu accesses
 drivesys.cpu.num_fp_alu_accesses                 1278                       # Number of float alu accesses
 drivesys.cpu.num_func_calls                    121650                       # number of times a function call or return occured
@@ -391,11 +395,13 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                      785978                       # Number of ticks simulated
 final_tick                               4300236804024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                           864513825905                       # Simulator instruction rate (inst/s)
-host_tick_rate                             2363296319                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 479620                       # Number of bytes of host memory used
+host_inst_rate                           826237832724                       # Simulator instruction rate (inst/s)
+host_op_rate                             785322914063                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2155916043                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 476544                       # Number of bytes of host memory used
 host_seconds                                     0.00                       # Real time elapsed on the host
 sim_insts                                   273374833                       # Number of instructions simulated
+sim_ops                                     273374833                       # Number of ops (including micro ops) simulated
 testsys.physmem.bytes_read                          0                       # Number of bytes read from this memory
 testsys.physmem.bytes_inst_read                     0                       # Number of instructions bytes read from this memory
 testsys.physmem.bytes_written                       0                       # Number of bytes written to this memory
@@ -449,7 +455,8 @@ testsys.cpu.itb.data_accesses                       0                       # DT
 testsys.cpu.numCycles                               0                       # number of cpu cycles simulated
 testsys.cpu.numWorkItemsStarted                     0                       # number of work items this cpu started
 testsys.cpu.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-testsys.cpu.num_insts                               0                       # Number of instructions executed
+testsys.cpu.committedInsts                          0                       # Number of instructions committed
+testsys.cpu.committedOps                            0                       # Number of ops (including micro ops) committed
 testsys.cpu.num_int_alu_accesses                    0                       # Number of integer alu accesses
 testsys.cpu.num_fp_alu_accesses                     0                       # Number of float alu accesses
 testsys.cpu.num_func_calls                          0                       # number of times a function call or return occured
@@ -568,7 +575,8 @@ drivesys.cpu.itb.data_accesses                      0                       # DT
 drivesys.cpu.numCycles                              0                       # number of cpu cycles simulated
 drivesys.cpu.numWorkItemsStarted                    0                       # number of work items this cpu started
 drivesys.cpu.numWorkItemsCompleted                  0                       # number of work items this cpu completed
-drivesys.cpu.num_insts                              0                       # Number of instructions executed
+drivesys.cpu.committedInsts                         0                       # Number of instructions committed
+drivesys.cpu.committedOps                           0                       # Number of ops (including micro ops) committed
 drivesys.cpu.num_int_alu_accesses                   0                       # Number of integer alu accesses
 drivesys.cpu.num_fp_alu_accesses                    0                       # Number of float alu accesses
 drivesys.cpu.num_func_calls                         0                       # number of times a function call or return occured
index b17544f09dffda35571ddec3cd018dd9203c6a8a..afc8aa811e638d7899a2edcdfba54e695e09449c 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index ba10334c574799d0914175a3c64830cc952628cb..ff8d4bf123d4d4ddfff3df41bf961b8c845a2413 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/inorder-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 4ce82e64f238e343ffcb8146dd2e8a140e1e061c..fc30a21c8eeba53d07dd5b2954c03b87a13b20b8 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000021                       # Nu
 sim_ticks                                    21216000                       # Number of ticks simulated
 final_tick                                   21216000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  36015                       # Simulator instruction rate (inst/s)
-host_tick_rate                              119302866                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207132                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  38129                       # Simulator instruction rate (inst/s)
+host_op_rate                                    38124                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              126288909                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209388                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30016                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  19264                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -68,9 +70,10 @@ system.cpu.comNops                                 17                       # Nu
 system.cpu.comNonSpec                              17                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                               3265                       # Number of Integer instructions committed
 system.cpu.comFloats                                2                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        6404                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total                  6404                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                        6404                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          6404                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                  6404                       # Number of Instructions committed (Total)
 system.cpu.cpi                               6.626015                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         6.626015                       # CPI: Total CPI of All Threads
@@ -124,26 +127,39 @@ system.cpu.icache.total_refs                      581                       # To
 system.cpu.icache.sampled_refs                    301                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   1.930233                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            138.882502                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.067814                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                    581                       # number of ReadReq hits
-system.cpu.icache.demand_hits                     581                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                    581                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  348                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   348                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  348                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       19241000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        19241000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       19241000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses                929                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                 929                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses                929                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.374596                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.374596                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.374596                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55290.229885                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55290.229885                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55290.229885                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     138.882502                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.067814                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.067814                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          581                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             581                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           581                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              581                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          581                       # number of overall hits
+system.cpu.icache.overall_hits::total             581                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          348                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           348                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          348                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            348                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          348                       # number of overall misses
+system.cpu.icache.overall_misses::total           348                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19241000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19241000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19241000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19241000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19241000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19241000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          929                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          929                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          929                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          929                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          929                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          929                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.374596                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.374596                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.374596                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55290.229885                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55290.229885                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55290.229885                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -152,27 +168,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                46                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 46                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                46                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             302                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              302                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             302                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     16049000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     16049000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     16049000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.325081                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.325081                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.325081                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.384106                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53142.384106                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53142.384106                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           46                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           46                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           46                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           46                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           46                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           46                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          302                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          302                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          302                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          302                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          302                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          302                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16049000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16049000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16049000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16049000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16049000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16049000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.325081                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.325081                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.325081                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.384106                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.384106                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.384106                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                102.671807                       # Cycle average of tags in use
@@ -180,32 +199,49 @@ system.cpu.dcache.total_refs                     1703                       # To
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  10.136905                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            102.671807                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.025066                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1088                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   615                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1703                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1703                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   97                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 250                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   347                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  347                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5508500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      13555500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        19064000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       19064000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2050                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2050                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.081857                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.289017                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.169268                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.169268                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 56788.659794                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        54222                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54939.481268                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54939.481268                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data     102.671807                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025066                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025066                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1088                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1088                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          615                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            615                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1703                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1703                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1703                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1703                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           97                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            97                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          250                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          250                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          347                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            347                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          347                       # number of overall misses
+system.cpu.dcache.overall_misses::total           347                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5508500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5508500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     13555500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     13555500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     19064000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     19064000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     19064000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     19064000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2050                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2050                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.081857                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.289017                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.169268                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.169268                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56788.659794                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        54222                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54939.481268                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54939.481268                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      1656000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -214,32 +250,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets        46000                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                 2                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              177                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                179                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               179                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              95                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      5114000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      3910000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      9024000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      9024000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.080169                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53831.578947                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53561.643836                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53714.285714                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53714.285714                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          177                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          177                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          179                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          179                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          179                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          179                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5114000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5114000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3910000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3910000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      9024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      9024000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      9024000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      9024000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53831.578947                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53561.643836                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53714.285714                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53714.285714                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               195.209568                       # Cycle average of tags in use
@@ -247,31 +289,64 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.sampled_refs                   395                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002532                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           195.209568                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005957                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 396                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  469                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 469                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      20702000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      3822000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       24524000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      24524000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               397                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                470                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               470                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.997481                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.997872                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.997872                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52277.777778                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52356.164384                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52289.978678                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52289.978678                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    138.958412                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.251157                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004241                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001717                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005957                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          301                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          396                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          301                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           469                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          469                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15707000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4995000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     20702000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3822000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3822000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15707000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      8817000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     24524000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15707000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      8817000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     24524000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          302                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          397                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          302                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          470                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          302                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          470                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996689                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996689                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996689                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52182.724252                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52578.947368                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52356.164384                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52182.724252                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52482.142857                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52182.724252                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52482.142857                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -280,30 +355,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            396                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             469                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            469                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     15877000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2942500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     18819500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     18819500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997481                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.997872                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.997872                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40093.434343                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40308.219178                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40126.865672                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40126.865672                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          396                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          469                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          469                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12038500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3838500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15877000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2942500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2942500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12038500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6781000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     18819500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12038500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6781000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     18819500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996689                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40405.263158                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40308.219178                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40363.095238                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39995.016611                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40363.095238                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index db5baf5c54a7e10f167c532e44e1ccc2b7562773..79efc97496b7a5e94dc98d124a448a2496b7f9cb 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 6e993ab1c1b76b3a64e5fdbfbfdda22a34bbed63..684d7e9b2e594eaf993d21038602980db0a730bd 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 3b3d572bb03a8beab0bcfe7e410d22fe49d016d1..49671266a47affb6098a67f6a9015c26263c8225 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12004500                       # Number of ticks simulated
 final_tick                                   12004500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  38695                       # Simulator instruction rate (inst/s)
-host_tick_rate                               72731813                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208040                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  42281                       # Simulator instruction rate (inst/s)
+host_op_rate                                    42276                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               79460110                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210060                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        6386                       # Number of instructions simulated
+sim_ops                                          6386                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       31040                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  19904                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -270,6 +272,7 @@ system.cpu.iew.wb_rate                       0.374511                       # in
 system.cpu.iew.wb_fanout                     0.736883                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           6403                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             6403                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            5259                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              17                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               381                       # The number of times a branch was mispredicted
@@ -290,7 +293,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        11614                       # Number of insts commited each cycle
-system.cpu.commit.count                          6403                       # Number of instructions committed
+system.cpu.commit.committedInsts                 6403                       # Number of instructions committed
+system.cpu.commit.committedOps                   6403                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2050                       # Number of memory references committed
 system.cpu.commit.loads                          1185                       # Number of loads committed
@@ -306,6 +310,7 @@ system.cpu.rob.rob_writes                       24313                       # Th
 system.cpu.timesIdled                             230                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           11418                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        6386                       # Number of Instructions Simulated
+system.cpu.committedOps                          6386                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  6386                       # Number of Instructions Simulated
 system.cpu.cpi                               3.759787                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         3.759787                       # CPI: Total CPI of All Threads
@@ -323,26 +328,39 @@ system.cpu.icache.total_refs                     1606                       # To
 system.cpu.icache.sampled_refs                    312                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   5.147436                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            160.112304                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.078180                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1606                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1606                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1606                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  433                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   433                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  433                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15431000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15431000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15431000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               2039                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                2039                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               2039                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.212359                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.212359                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.212359                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35637.413395                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35637.413395                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35637.413395                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     160.112304                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.078180                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.078180                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1606                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1606                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1606                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1606                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1606                       # number of overall hits
+system.cpu.icache.overall_hits::total            1606                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          433                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           433                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          433                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            433                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          433                       # number of overall misses
+system.cpu.icache.overall_misses::total           433                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15431000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15431000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15431000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15431000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15431000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15431000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2039                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2039                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2039                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2039                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2039                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2039                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.212359                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.212359                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.212359                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35637.413395                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35637.413395                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35637.413395                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -351,27 +369,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               121                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                121                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               121                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             312                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              312                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             312                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     11021000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     11021000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     11021000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.153016                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.153016                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.153016                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35323.717949                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35323.717949                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35323.717949                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          121                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          121                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          121                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          121                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          121                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          121                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          312                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          312                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          312                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          312                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          312                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          312                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11021000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11021000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11021000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11021000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11021000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11021000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.153016                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.153016                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.153016                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35323.717949                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35323.717949                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35323.717949                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                109.290272                       # Cycle average of tags in use
@@ -379,32 +400,49 @@ system.cpu.dcache.total_refs                     2154                       # To
 system.cpu.dcache.sampled_refs                    174                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  12.379310                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            109.290272                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.026682                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1645                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   509                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2154                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2154                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  154                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 356                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   510                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  510                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5497500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      12467500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        17965000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       17965000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1799                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2664                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2664                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.085603                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.411561                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.191441                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.191441                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35698.051948                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 35021.067416                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35225.490196                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35225.490196                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data     109.290272                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.026682                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.026682                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1645                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1645                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          509                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            509                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2154                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2154                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2154                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2154                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          154                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           154                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          356                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          356                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          510                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            510                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          510                       # number of overall misses
+system.cpu.dcache.overall_misses::total           510                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5497500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5497500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     12467500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     12467500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     17965000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     17965000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     17965000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     17965000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1799                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1799                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2664                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2664                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2664                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2664                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085603                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.411561                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.191441                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.191441                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35698.051948                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35021.067416                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35225.490196                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35225.490196                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -413,32 +451,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                53                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              283                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                336                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               336                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             101                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              174                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             174                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      3654500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2611500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      6266000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      6266000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.056142                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.065315                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.065315                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 36183.168317                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35773.972603                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 36011.494253                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 36011.494253                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           53                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           53                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          283                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          283                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          336                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          336                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          336                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          101                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          174                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          174                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          174                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3654500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3654500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2611500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2611500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6266000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6266000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6266000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6266000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.056142                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.065315                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.065315                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36183.168317                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35773.972603                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36011.494253                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36011.494253                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               221.643066                       # Cycle average of tags in use
@@ -446,31 +490,64 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.sampled_refs                   412                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002427                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           221.643066                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006764                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 412                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  485                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 485                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      14163000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2513500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       16676500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      16676500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               413                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                486                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               486                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.997579                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.997942                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.997942                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34376.213592                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34431.506849                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34384.536082                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34384.536082                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    160.084939                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     61.558127                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004885                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001879                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006764                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          311                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          101                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          412                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          311                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          174                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           485                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          311                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          174                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          485                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10665000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3498000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14163000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2513500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2513500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     10665000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6011500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16676500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     10665000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6011500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16676500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          312                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          101                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          413                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          312                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          174                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          486                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          312                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          174                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          486                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996795                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996795                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996795                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34292.604502                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34633.663366                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34431.506849                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34292.604502                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34548.850575                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34292.604502                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34548.850575                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -479,30 +556,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            412                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             485                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            485                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12850000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2286000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     15136000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     15136000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997579                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.997942                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.997942                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31189.320388                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31315.068493                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31208.247423                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31208.247423                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          311                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          101                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          412                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          311                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          174                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          485                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          311                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          174                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          485                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9672000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3178000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12850000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2286000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2286000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9672000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5464000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15136000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9672000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5464000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15136000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996795                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996795                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996795                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31099.678457                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31465.346535                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31315.068493                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31099.678457                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31402.298851                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31099.678457                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31402.298851                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index df86e7077ef2c182d31a01607637afc8dd34dec3..f91bbd9dc62a9af5bab6c4c13959aeb743f255f3 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
index 9f50fe96061887c8aec3d41495743dcf4fc79482..2f9b31423e09a6a549d895c86ad358f8e352da9d 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 7ceb6a8be7c4005836694687587fb6d1624619f8..97b8faa6b8595a01e8ea257fae7c8a6730035f81 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     3215000                       # Number of ticks simulated
 final_tick                                    3215000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76916                       # Simulator instruction rate (inst/s)
-host_tick_rate                               38606134                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 198176                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  35037                       # Simulator instruction rate (inst/s)
+host_op_rate                                    35032                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               17585099                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 199940                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                             6431                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
index b9fd9c5f2ad53ca1ea32c464fed6c6749dcd63f2..dd4aa648f34d8d428935bffa18d887c586e960b7 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -66,7 +79,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -134,6 +147,7 @@ l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 to_l2_latency=1
 transitions_per_cycle=32
index c2d3c97afc18766e7319d4456e25618b5f4186a8..d2cdb9adab2e5b7465729c56db4e184c86e07ca0 100644 (file)
@@ -34,27 +34,26 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:21:55
+Real time: Feb/12/2012 15:33:22
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 2
-Elapsed_time_in_minutes: 0.0333333
-Elapsed_time_in_hours: 0.000555556
-Elapsed_time_in_days: 2.31481e-05
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.38
-Virtual_time_in_minutes: 0.00633333
-Virtual_time_in_hours:   0.000105556
-Virtual_time_in_days:    4.39815e-06
+Virtual_time_in_seconds: 1.01
+Virtual_time_in_minutes: 0.0168333
+Virtual_time_in_hours:   0.000280556
+Virtual_time_in_days:    1.16898e-05
 
 Ruby_current_time: 279353
 Ruby_start_time: 0
 Ruby_cycles: 279353
 
-mbytes_resident: 45.5547
-mbytes_total: 214.371
-resident_ratio: 0.212504
+mbytes_resident: 0
+mbytes_total: 0
 
 ruby_cycles_executed: [ 279354 ]
 
@@ -101,9 +100,9 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 1 max: 20 count: 9645 average: 0.064282 | standard deviation: 0.540462 | 9495 0 1 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ]
+Total_delay_cycles: [binsize: 1 max: 18 count: 9645 average: 0.0636599 | standard deviation: 0.52686 | 9495 0 1 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
 Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 6920 average: 0.000289017 | standard deviation: 0.0240441 | 6919 0 1 ]
-  virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 2725 average: 0.226789 | standard deviation: 0.997795 | 2576 0 0 0 147 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 2725 average: 0.224587 | standard deviation: 0.972266 | 2576 0 0 0 147 0 1 0 0 0 0 0 0 0 0 0 0 0 1 ]
   virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 1041 average:     0 | standard deviation: 0 | 1041 ]
   virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 5879 average: 0.000340194 | standard deviation: 0.0260865 | 5878 0 1 ]
@@ -119,11 +118,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11862
-page_faults: 127
+page_reclaims: 13214
+page_faults: 148
 swaps: 0
-block_inputs: 22816
-block_outputs: 96
+block_inputs: 2
+block_outputs: 4
 
 Network Stats
 -------------
@@ -320,11 +319,6 @@ M_I  Fwd_GETS [0 ] 0
 M_I  Fwd_GET_INSTR [0 ] 0
 M_I  WB_Ack [436 ] 436
 
-E_I  Load [0 ] 0
-E_I  Ifetch [0 ] 0
-E_I  Store [0 ] 0
-E_I  L1_Replacement [0 ] 0
-
 SINK_WB_ACK  Load [0 ] 0
 SINK_WB_ACK  Ifetch [0 ] 0
 SINK_WB_ACK  Store [0 ] 0
@@ -348,7 +342,7 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
  --- L2Cache ---
  - Event Counts -
 L1_GET_INSTR [691 ] 691
-L1_GETS [586 ] 586
+L1_GETS [585 ] 585
 L1_GETX [216 ] 216
 L1_UPGRADE [0 ] 0
 L1_PUTX [436 ] 436
@@ -405,7 +399,7 @@ MT  L2_Replacement_clean [352 ] 352
 MT  MEM_Inv [0 ] 0
 
 M_I  L1_GET_INSTR [0 ] 0
-M_I  L1_GETS [3 ] 3
+M_I  L1_GETS [2 ] 2
 M_I  L1_GETX [0 ] 0
 M_I  L1_UPGRADE [0 ] 0
 M_I  L1_PUTX [0 ] 0
index c93c8f8afb7dff5814a06a0b4aeb3bc7e0d8da12..a25a5c8791f31ad83f9d92e468a9717325bcd2d8 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:44:57
-gem5 started Jan 23 2012 04:21:53
-gem5 executing on zizzer
-command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 3bba58631c3b1dcf6c2a94eba96b6a7b3bb4a859..de3976298bd7947a3c9a19017d933519939932a3 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000279                       # Nu
 sim_ticks                                      279353                       # Number of ticks simulated
 final_tick                                     279353                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   2836                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 123728                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219520                       # Number of bytes of host memory used
-host_seconds                                     2.26                       # Real time elapsed on the host
+host_inst_rate                                  12170                       # Simulator instruction rate (inst/s)
+host_op_rate                                    12169                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 530781                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 270088                       # Number of bytes of host memory used
+host_seconds                                     0.53                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           279353                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
index 607ab419cdd7f89f368f002e84f5ff5bed3e6e00..38b836011c3a6843cd342424bbb3e64a90a2da91 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -132,6 +145,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index ed47704f67397cd9a7b8efc56d93838a46196a97..aa46612d8a11923bf8f451a292027ab5abdf44a3 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:47:36
-gem5 started Jan 23 2012 04:22:12
+gem5 compiled Feb 11 2012 13:06:37
+gem5 started Feb 11 2012 13:53:23
 gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
+command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 44a6426b248f6fd9fc9e12bcc698cb3a1134aa5b..02467cae93592c3f5fe3fb1b55be88c2f58b013a 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000224                       # Nu
 sim_ticks                                      223694                       # Number of ticks simulated
 final_tick                                     223694                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19611                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 684980                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 219636                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
+host_inst_rate                                  37589                       # Simulator instruction rate (inst/s)
+host_op_rate                                    37585                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1312743                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221408                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           223694                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
index e664ed4cffe499d0294a6d79b01387cba389e366..0617e8d3876dae64c8d8d2b065fb7701631bcc8d 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -141,6 +154,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index 6ef144b06230c09526a38f8a373f22992c729c92..0b4972a1727ac66a9227c233d2c1b9292f158603 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:50:16
-gem5 started Jan 23 2012 04:22:25
+gem5 compiled Feb 11 2012 13:07:02
+gem5 started Feb 11 2012 13:54:08
 gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
+command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 4911f0b0e1a8ed0abe47238f5e1ac65142277509..e1d06acb68b1d04cf00490993319edd23fe9a79c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000232                       # Nu
 sim_ticks                                      231701                       # Number of ticks simulated
 final_tick                                     231701                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23819                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 861729                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217800                       # Number of bytes of host memory used
-host_seconds                                     0.27                       # Real time elapsed on the host
+host_inst_rate                                  59077                       # Simulator instruction rate (inst/s)
+host_op_rate                                    59067                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2136733                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219660                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           231701                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
index aa987ffa69f2290aa5667422f40e2b9cd4f05a27..15b38dd1a2462b8ccad29c70c6b351d64e9c9033 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -147,6 +160,7 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index fa89dfcd6c9556a63b16df7207c29a66e8b4bcf1..9412b907c6595caacca98b111bd51923cf46a249 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:42:19
-gem5 started Jan 23 2012 04:21:43
+gem5 compiled Feb 11 2012 13:05:44
+gem5 started Feb 11 2012 13:52:39
 gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
+command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index dfbcac63cb7950fcaafb587865af2145aa7e719b..87ed3fb4b8bbb859930bf66ad328394e82b62420 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000208                       # Nu
 sim_ticks                                      208400                       # Number of ticks simulated
 final_tick                                     208400                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  24253                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 789193                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217184                       # Number of bytes of host memory used
-host_seconds                                     0.26                       # Real time elapsed on the host
+host_inst_rate                                  64619                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64607                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2102096                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218760                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           208400                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
index 0772d2ee56d34e8e5c7155bbfaa4b2460c928e20..3d3a73e3a23841cd23088ec802988b263efdc1fc 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -131,6 +144,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index 9cf8229011b947d6de18067d2655170968a33b88..05fd4efdde5ad19f79f41dc99b3df533af27b941 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing-ruby
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index beb747c4110c0069c368e5e2fb4a1c3243533d02..16827676450adebb5fcd0fa9c45d068dda8a63dc 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000343                       # Nu
 sim_ticks                                      342698                       # Number of ticks simulated
 final_tick                                     342698                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  32385                       # Simulator instruction rate (inst/s)
-host_tick_rate                                1732860                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 218476                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  61504                       # Simulator instruction rate (inst/s)
+host_op_rate                                    61493                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                3290073                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220236                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       34460                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  25656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     6696                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                           342698                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
index f51983ecf92fb5b06ba33ceb041d90e9b4741163..3b46c790f5f860550745012f2979a81449b026da 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index d977e688b727c4d2cea5d2f99e8231bb15c58d05..5e2927c579528448e307376cbb881177bd26d948 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:58:59
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:12
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/linux/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 84a161e812ae6b3b9ece6cb2b33977ef55c0b63d..6278fa87327c87af66a10eb1d6a84c77d75eb73c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000033                       # Nu
 sim_ticks                                    33007000                       # Number of ticks simulated
 final_tick                                   33007000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 110064                       # Simulator instruction rate (inst/s)
-host_tick_rate                              566999999                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206896                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  37663                       # Simulator instruction rate (inst/s)
+host_op_rate                                    37658                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              194071847                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209060                       # Number of bytes of host memory used
+host_seconds                                     0.17                       # Real time elapsed on the host
 sim_insts                                        6404                       # Number of instructions simulated
+sim_ops                                          6404                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28544                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  17792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls                   17                       # Nu
 system.cpu.numCycles                            66014                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             6404                       # Number of instructions executed
+system.cpu.committedInsts                        6404                       # Number of instructions committed
+system.cpu.committedOps                          6404                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  6331                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     10                       # Number of float alu accesses
 system.cpu.num_func_calls                         251                       # number of times a function call or return occured
@@ -78,26 +81,39 @@ system.cpu.icache.total_refs                     6136                       # To
 system.cpu.icache.sampled_refs                    279                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  21.992832                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            127.883393                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.062443                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   6136                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    6136                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   6136                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  279                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   279                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  279                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15582000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15582000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15582000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               6415                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                6415                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               6415                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.043492                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.043492                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.043492                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55849.462366                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55849.462366                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55849.462366                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     127.883393                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.062443                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.062443                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         6136                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            6136                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          6136                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             6136                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         6136                       # number of overall hits
+system.cpu.icache.overall_hits::total            6136                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           279                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            279                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          279                       # number of overall misses
+system.cpu.icache.overall_misses::total           279                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15582000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15582000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15582000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15582000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15582000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15582000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         6415                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6415                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6415                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6415                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6415                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6415                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.043492                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.043492                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.043492                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55849.462366                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55849.462366                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55849.462366                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             279                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              279                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             279                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     14745000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     14745000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     14745000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.043492                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.043492                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.043492                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52849.462366                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52849.462366                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52849.462366                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          279                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          279                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14745000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14745000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14745000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14745000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14745000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14745000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.043492                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52849.462366                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                103.680615                       # Cycle average of tags in use
@@ -133,32 +147,49 @@ system.cpu.dcache.total_refs                     1882                       # To
 system.cpu.dcache.sampled_refs                    168                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  11.202381                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            103.680615                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.025313                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1090                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   792                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1882                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1882                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   95                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  73                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   168                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  168                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5320000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       4088000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         9408000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        9408000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1185                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               865                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2050                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2050                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.080169                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.084393                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.081951                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.081951                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data     103.680615                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.025313                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.025313                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1090                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1090                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          792                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            792                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1882                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1882                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1882                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1882                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            95                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           73                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           73                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            168                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          168                       # number of overall misses
+system.cpu.dcache.overall_misses::total           168                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5320000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5320000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4088000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4088000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      9408000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      9408000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      9408000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      9408000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1185                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          865                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2050                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2050                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2050                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2050                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.080169                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084393                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.081951                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.081951                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -167,30 +198,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              95                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             73                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              168                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             168                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      5035000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      3869000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      8904000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      8904000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.080169                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.081951                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.081951                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           95                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           73                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          168                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          168                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      5035000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      5035000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      3869000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      3869000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      8904000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      8904000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      8904000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      8904000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.080169                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.081951                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               184.342479                       # Cycle average of tags in use
@@ -198,31 +229,64 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.sampled_refs                   373                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002681                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           184.342479                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005626                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 373                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                73                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  446                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 446                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      19396000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      3796000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       23192000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      23192000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               374                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              73                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                447                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               447                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.997326                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.997763                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.997763                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    127.900723                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     56.441756                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003903                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001722                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005626                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           95                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          373                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           73                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           73                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          168                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           446                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          168                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          446                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14456000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4940000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     19396000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      3796000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      3796000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     14456000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      8736000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23192000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     14456000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      8736000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23192000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          279                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           95                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          374                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           73                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          279                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          168                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          447                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          279                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          168                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          447                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996416                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996416                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996416                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -231,30 +295,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            373                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           73                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             446                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            446                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     14920000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2920000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     17840000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     17840000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.997326                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.997763                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.997763                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           95                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          373                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           73                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          168                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          446                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          168                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          446                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3800000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14920000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2920000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      6720000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17840000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      6720000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17840000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996416                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f0e8b9ebf2eda43349cf76a6b4a4849414452485..d74613835e4b98fd9e450aeb8769af390b989689 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 2afd9a6f8081b7502fbb6ce13e9ec4819e290eaf..6aed6d3ac46bdc4b79a691785405986254a70078 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:23
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index d94c5613db01ef7a5050ba86d209c826e88e7f6c..d93b581f0315ade20b495f5158ed910f77a09594 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000007                       # Nu
 sim_ticks                                     6833000                       # Number of ticks simulated
 final_tick                                    6833000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  46364                       # Simulator instruction rate (inst/s)
-host_tick_rate                              132671945                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207164                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                  16400                       # Simulator instruction rate (inst/s)
+host_op_rate                                    16398                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               46934615                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209144                       # Number of bytes of host memory used
+host_seconds                                     0.15                       # Real time elapsed on the host
 sim_insts                                        2387                       # Number of instructions simulated
+sim_ops                                          2387                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       17280                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  11840                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -269,6 +271,7 @@ system.cpu.iew.wb_rate                       0.261872                       # in
 system.cpu.iew.wb_fanout                     0.786143                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           2576                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             2576                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            2416                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls               4                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               149                       # The number of times a branch was mispredicted
@@ -289,7 +292,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total         5960                       # Number of insts commited each cycle
-system.cpu.commit.count                          2576                       # Number of instructions committed
+system.cpu.commit.committedInsts                 2576                       # Number of instructions committed
+system.cpu.commit.committedOps                   2576                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                            709                       # Number of memory references committed
 system.cpu.commit.loads                           415                       # Number of loads committed
@@ -305,6 +309,7 @@ system.cpu.rob.rob_writes                       10410                       # Th
 system.cpu.timesIdled                             139                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                            7284                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        2387                       # Number of Instructions Simulated
+system.cpu.committedOps                          2387                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  2387                       # Number of Instructions Simulated
 system.cpu.cpi                               5.725597                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         5.725597                       # CPI: Total CPI of All Threads
@@ -321,26 +326,39 @@ system.cpu.icache.total_refs                      700                       # To
 system.cpu.icache.sampled_refs                    185                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   3.783784                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0             91.574139                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.044714                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                    700                       # number of ReadReq hits
-system.cpu.icache.demand_hits                     700                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                    700                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  241                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   241                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  241                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency        8777500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency         8777500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency        8777500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses                941                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                 941                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses                941                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.256111                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.256111                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.256111                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36421.161826                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36421.161826                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36421.161826                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst      91.574139                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.044714                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.044714                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          700                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             700                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           700                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              700                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          700                       # number of overall hits
+system.cpu.icache.overall_hits::total             700                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          241                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           241                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          241                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            241                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          241                       # number of overall misses
+system.cpu.icache.overall_misses::total           241                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst      8777500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total      8777500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst      8777500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total      8777500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst      8777500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total      8777500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          941                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          941                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          941                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          941                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          941                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.256111                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.256111                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.256111                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36421.161826                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36421.161826                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36421.161826                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -349,27 +367,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                56                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 56                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                56                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             185                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              185                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             185                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency      6554500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency      6554500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency      6554500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.196599                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.196599                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.196599                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35429.729730                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35429.729730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35429.729730                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           56                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           56                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           56                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           56                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           56                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          185                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          185                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          185                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          185                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          185                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          185                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      6554500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total      6554500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst      6554500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total      6554500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst      6554500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total      6554500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.196599                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.196599                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.196599                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35429.729730                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35429.729730                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35429.729730                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 45.439198                       # Cycle average of tags in use
@@ -377,32 +398,49 @@ system.cpu.dcache.total_refs                      765                       # To
 system.cpu.dcache.sampled_refs                     85                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                          9                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             45.439198                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.011094                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                    543                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   222                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                     765                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                    765                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  101                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  72                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   173                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  173                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3605000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       2816500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         6421500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        6421500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses                644                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                 938                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses                938                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.156832                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.244898                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.184435                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.184435                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35693.069307                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 39118.055556                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 37118.497110                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 37118.497110                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      45.439198                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.011094                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.011094                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          543                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             543                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          222                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            222                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data           765                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              765                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          765                       # number of overall hits
+system.cpu.dcache.overall_hits::total             765                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          101                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           101                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           72                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           72                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          173                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            173                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          173                       # number of overall misses
+system.cpu.dcache.overall_misses::total           173                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3605000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3605000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2816500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2816500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      6421500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      6421500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      6421500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      6421500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          644                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          644                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data          938                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          938                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          938                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          938                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.156832                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.244898                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.184435                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.184435                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35693.069307                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39118.055556                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 37118.497110                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 37118.497110                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -411,32 +449,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                40                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits               48                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                 88                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                88                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              61                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             24                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses               85                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses              85                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2169000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency       872000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      3041000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      3041000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.094720                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.081633                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.090618                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.090618                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35557.377049                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36333.333333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35776.470588                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35776.470588                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           40                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data           48                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total           48                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           88                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           88                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           88                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           88                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           61                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           24                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           24                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total           85                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total           85                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2169000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2169000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data       872000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total       872000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      3041000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      3041000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3041000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      3041000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.094720                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081633                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.090618                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.090618                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35557.377049                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36333.333333                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35776.470588                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35776.470588                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               120.203882                       # Cycle average of tags in use
@@ -444,30 +488,58 @@ system.cpu.l2cache.total_refs                       0                       # To
 system.cpu.l2cache.sampled_refs                   246                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           120.203882                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.003668                       # Average percentage of cache occupancy
-system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     0                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 246                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                24                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  270                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 270                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency       8447500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency       831000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency        9278500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency       9278500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               246                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              24                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                270                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               270                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34339.430894                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        34625                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34364.814815                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34364.814815                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst     91.660485                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.543397                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.002797                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000871                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.003668                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_misses::cpu.inst          185                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           61                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          246                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           24                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           24                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          185                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data           85                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           270                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          185                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data           85                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          270                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      6346000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2101500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total      8447500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data       831000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total       831000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst      6346000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      2932500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total      9278500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst      6346000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      2932500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total      9278500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          185                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           61                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          246                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           24                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           24                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          185                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data           85                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          270                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          185                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data           85                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          270                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34302.702703                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34450.819672                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34625                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34302.702703                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        34500                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34302.702703                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        34500                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -476,30 +548,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            246                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           24                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             270                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            270                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      7661500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency       756000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency      8417500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency      8417500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31144.308943                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        31500                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31175.925926                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31175.925926                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          185                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           61                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          246                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           24                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           24                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          185                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data           85                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          270                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          185                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data           85                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          270                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      5756000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1905500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      7661500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data       756000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total       756000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      5756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      2661500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total      8417500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      5756000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      2661500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total      8417500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31113.513514                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31237.704918                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        31500                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31113.513514                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31311.764706                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31113.513514                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31311.764706                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index fad1e21b6c07836966f18bcf07369a22ee2431be..d4970301bb6c2d435f7a18c2790fe81f98c06b10 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
index fdc12b275d17953dccd1b8ad86e21a8700dd4828..8e9c64562b55907858d886183dae5f89f99dc3d3 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-atomic
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 23e50fd7f5f719a74f4b5e7a94428126a8a68a74..d3468c0e974c0301fcbd475db63eb9b9b3303a31 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000001                       # Nu
 sim_ticks                                     1297500                       # Number of ticks simulated
 final_tick                                    1297500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 182014                       # Simulator instruction rate (inst/s)
-host_tick_rate                               91451888                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 197324                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                  24554                       # Simulator instruction rate (inst/s)
+host_op_rate                                    24550                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               12358328                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 199092                       # Number of bytes of host memory used
+host_seconds                                     0.11                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                             2596                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
index 89c8aeac18aef6c9628036884efbdb1934b3be80..2a33a674c276d56fe79eee6ee29aaca423da3079 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -66,7 +79,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
+executable=tests/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -134,6 +147,7 @@ l2_select_num_bits=0
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 to_l2_latency=1
 transitions_per_cycle=32
index 1c4da6ce44bfe08ea5e57a3d9206531e41905abf..9c8b2434fd7bf6bb3908ff9d0a8d7817bdfc884d 100644 (file)
@@ -34,27 +34,26 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Jan/23/2012 04:21:58
+Real time: Feb/12/2012 15:33:21
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 2
-Elapsed_time_in_minutes: 0.0333333
-Elapsed_time_in_hours: 0.000555556
-Elapsed_time_in_days: 2.31481e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.26
-Virtual_time_in_minutes: 0.00433333
-Virtual_time_in_hours:   7.22222e-05
-Virtual_time_in_days:    3.00926e-06
+Virtual_time_in_seconds: 0.71
+Virtual_time_in_minutes: 0.0118333
+Virtual_time_in_hours:   0.000197222
+Virtual_time_in_days:    8.21759e-06
 
 Ruby_current_time: 104867
 Ruby_start_time: 0
 Ruby_cycles: 104867
 
-mbytes_resident: 43.0078
-mbytes_total: 212.113
-resident_ratio: 0.202759
+mbytes_resident: 0
+mbytes_total: 0
 
 ruby_cycles_executed: [ 104868 ]
 
@@ -101,9 +100,9 @@ filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN
 
 Message Delayed Cycles
 ----------------------
-Total_delay_cycles: [binsize: 1 max: 20 count: 3612 average: 0.0636766 | standard deviation: 0.653474 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+Total_delay_cycles: [binsize: 1 max: 18 count: 3612 average: 0.0625692 | standard deviation: 0.620431 | 3562 0 1 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
 Total_nonPF_delay_cycles: [binsize: 1 max: 2 count: 2644 average: 0.00075643 | standard deviation: 0.0389028 | 2643 0 1 ]
-  virtual_network_0_delay_cycles: [binsize: 1 max: 20 count: 968 average: 0.235537 | standard deviation: 1.24505 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
+  virtual_network_0_delay_cycles: [binsize: 1 max: 18 count: 968 average: 0.231405 | standard deviation: 1.18112 | 919 0 0 0 47 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ]
   virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
   virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 431 average:     0 | standard deviation: 0 | 431 ]
   virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 2213 average: 0.000903751 | standard deviation: 0.0425243 | 2212 0 1 ]
@@ -119,11 +118,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11317
-page_faults: 0
+page_reclaims: 12663
+page_faults: 71
 swaps: 0
 block_inputs: 0
-block_outputs: 88
+block_outputs: 0
 
 Network Stats
 -------------
@@ -320,11 +319,6 @@ M_I  Fwd_GETS [0 ] 0
 M_I  Fwd_GET_INSTR [0 ] 0
 M_I  WB_Ack [124 ] 124
 
-E_I  Load [0 ] 0
-E_I  Ifetch [0 ] 0
-E_I  Store [0 ] 0
-E_I  L1_Replacement [0 ] 0
-
 SINK_WB_ACK  Load [0 ] 0
 SINK_WB_ACK  Ifetch [0 ] 0
 SINK_WB_ACK  Store [0 ] 0
@@ -348,8 +342,8 @@ Cache Stats: system.l2_cntrl0.L2cacheMemory
  --- L2Cache ---
  - Event Counts -
 L1_GET_INSTR [300 ] 300
-L1_GETS [206 ] 206
-L1_GETX [70 ] 70
+L1_GETS [205 ] 205
+L1_GETX [69 ] 69
 L1_UPGRADE [0 ] 0
 L1_PUTX [124 ] 124
 L1_PUTX_old [0 ] 0
@@ -405,8 +399,8 @@ MT  L2_Replacement_clean [141 ] 141
 MT  MEM_Inv [0 ] 0
 
 M_I  L1_GET_INSTR [0 ] 0
-M_I  L1_GETS [2 ] 2
-M_I  L1_GETX [2 ] 2
+M_I  L1_GETS [1 ] 1
+M_I  L1_GETX [1 ] 1
 M_I  L1_UPGRADE [0 ] 0
 M_I  L1_PUTX [0 ] 0
 M_I  L1_PUTX_old [0 ] 0
index dc0ba29228ebcc2e6f3e74f17d7f6e4cfa9009c4..22e5bbd3fae3b13170687321d62eb8ccdc363092 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:44:57
-gem5 started Jan 23 2012 04:21:56
-gem5 executing on zizzer
-command line: build/ALPHA_SE_MESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
+command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index ebac3fa8311aea9ffeab270b8f22685e7ac7383f..bb0141a2a5fc88708d6d90ebdfbe997527c97b45 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000105                       # Nu
 sim_ticks                                      104867                       # Number of ticks simulated
 final_tick                                     104867                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1196                       # Simulator instruction rate (inst/s)
-host_tick_rate                                  48657                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217208                       # Number of bytes of host memory used
-host_seconds                                     2.16                       # Real time elapsed on the host
+host_inst_rate                                  10837                       # Simulator instruction rate (inst/s)
+host_op_rate                                    10836                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 440871                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 267756                       # Number of bytes of host memory used
+host_seconds                                     0.24                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                           104867                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
index e5748fef4ac35c06bb0a7eb75cd87df0ac4feea3..1d5a893ffda0a900ae2b9c52a57c6df044ce0908 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -132,6 +145,7 @@ number_of_TBEs=256
 recycle_latency=10
 request_latency=2
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index 0529ad1d82c1419c35a00378a7601188b605acf9..7ff04205562972458bc1d3489135f7084312be0d 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:47:36
-gem5 started Jan 23 2012 04:22:12
+gem5 compiled Feb 11 2012 13:06:37
+gem5 started Feb 11 2012 13:53:34
 gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_directory/gem5.opt -d build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
+command line: build/ALPHA_MOESI_CMP_directory/gem5.fast -d build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 8d97fa8c66061ed41b57577a726432ddb2450948..aeddd4cb4501c80a172d0d294076e9ac3b29f298 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000085                       # Nu
 sim_ticks                                       85418                       # Number of ticks simulated
 final_tick                                      85418                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  13096                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 434048                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217400                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  37008                       # Simulator instruction rate (inst/s)
+host_op_rate                                    36998                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1226055                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 219168                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                            85418                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
index 4c0569af0bec44ef5324d5e63934a66d435f8e00..d5f1dd8ea03f1310ff4d835c766385f97e75f6f3 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -141,6 +154,7 @@ number_of_TBEs=256
 recycle_latency=10
 retry_threshold=1
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index 476a0b5996e766de58dcadc6f42f732046bb1a5c..f1a5aa8ceef6ae457b45aa57ff6172ee532c7bc4 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:50:16
-gem5 started Jan 23 2012 04:22:25
+gem5 compiled Feb 11 2012 13:07:02
+gem5 started Feb 11 2012 13:54:19
 gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_CMP_token/gem5.opt -d build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
+command line: build/ALPHA_MOESI_CMP_token/gem5.fast -d build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index fd5600236a90008d836036493fd21f37de64b90e..bd362a91b07be1c59c40b9f7d322b1c209c3e80d 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                       87899                       # Number of ticks simulated
 final_tick                                      87899                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  12702                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 433208                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216416                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  58227                       # Simulator instruction rate (inst/s)
+host_op_rate                                    58203                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1984496                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218264                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                            87899                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
index 209bb4d8dbc5f10e3e46187f57aa5cf8d2b45d21..82df55c274cddcbd69105260bd5f9530e413f3c5 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -147,6 +160,7 @@ no_mig_atomic=true
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index 20c68eff3acc221433731d436dfbac184b4809c3..f44aeab207f2ea4c5c60c26048f967c0a5971d64 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:42:19
-gem5 started Jan 23 2012 04:21:49
+gem5 compiled Feb 11 2012 13:05:44
+gem5 started Feb 11 2012 13:52:40
 gem5 executing on zizzer
-command line: build/ALPHA_SE_MOESI_hammer/gem5.opt -d build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
+command line: build/ALPHA_MOESI_hammer/gem5.fast -d build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 5c579e1af26c7ad56fd8f11a4aca1c6d55180def..a79092ea7a21080ccf46535d66b76fb6ca233df1 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000078                       # Nu
 sim_ticks                                       78448                       # Number of ticks simulated
 final_tick                                      78448                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29294                       # Simulator instruction rate (inst/s)
-host_tick_rate                                 891567                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 215964                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  53931                       # Simulator instruction rate (inst/s)
+host_op_rate                                    53912                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1640583                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 217556                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                            78448                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
index 2d5b16f7e9d5a8a898887d9003f280f50b9f9b57..1b51d074e4fad2b828ba4d0da8201e59a7f62836 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=AlphaTLB
 size=64
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -131,6 +144,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index af1c569806f5af9a824598f6fd5f4ef921b434a1..acdbe4afbf1cd7e6238417bdf19b4d5fd9a530b8 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing-ruby
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index bcff12bb91cf2919b4d9b980c8e99d9fdec0cd79..22da3c1b5f90012297972d1e0155f3bba49ffe81 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000123                       # Nu
 sim_ticks                                      123378                       # Number of ticks simulated
 final_tick                                     123378                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  44691                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2138947                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 216404                       # Number of bytes of host memory used
-host_seconds                                     0.06                       # Real time elapsed on the host
+host_inst_rate                                  35379                       # Simulator instruction rate (inst/s)
+host_op_rate                                    35370                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                1692995                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218176                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       13356                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10340                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     2058                       # Number of bytes written to this memory
@@ -55,7 +57,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                           123378                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
index 72df6988288d3d7e8cc2d61ae3d0ce84e4f15d05..bcf14766cc09e5327bdd8444015bf0a864825d85 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 6a994fb76aa0d962583c13e39723bed09a5261e9..ec60c2fa252d169c893a6cab85262c0485d70851 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/00.hello/alpha/tru64/simple-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index e3a7a00a0c177ce537e916befbf6e3907bde249c..4d24e98d0366ea710ff95b3918024a6c58d810e8 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000017                       # Nu
 sim_ticks                                    16769000                       # Number of ticks simulated
 final_tick                                   16769000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 297044                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1928782837                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 206044                       # Number of bytes of host memory used
-host_seconds                                     0.01                       # Real time elapsed on the host
+host_inst_rate                                 142484                       # Simulator instruction rate (inst/s)
+host_op_rate                                   142326                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              925222654                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 208204                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
+sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       15680                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  10432                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -54,7 +56,8 @@ system.cpu.workload.num_syscalls                    4                       # Nu
 system.cpu.numCycles                            33538                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             2577                       # Number of instructions executed
+system.cpu.committedInsts                        2577                       # Number of instructions committed
+system.cpu.committedOps                          2577                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  2375                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      6                       # Number of float alu accesses
 system.cpu.num_func_calls                         140                       # number of times a function call or return occured
@@ -78,26 +81,39 @@ system.cpu.icache.total_refs                     2423                       # To
 system.cpu.icache.sampled_refs                    163                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  14.865031                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0             80.003762                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.039064                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   2423                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    2423                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   2423                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  163                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   163                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  163                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency        9128000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency         9128000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency        9128000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               2586                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                2586                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               2586                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.063032                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.063032                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.063032                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst      80.003762                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.039064                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.039064                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         2423                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            2423                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          2423                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             2423                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         2423                       # number of overall hits
+system.cpu.icache.overall_hits::total            2423                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           163                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          163                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            163                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          163                       # number of overall misses
+system.cpu.icache.overall_misses::total           163                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst      9128000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total      9128000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst      9128000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total      9128000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst      9128000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total      9128000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         2586                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         2586                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         2586                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         2586                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         2586                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         2586                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.063032                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.063032                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.063032                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        56000                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        56000                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -106,26 +122,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             163                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              163                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             163                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency      8639000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency      8639000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency      8639000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.063032                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.063032                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.063032                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          163                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          163                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          163                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          163                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          163                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      8639000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total      8639000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst      8639000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total      8639000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst      8639000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total      8639000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.063032                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        53000                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        53000                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 47.418751                       # Cycle average of tags in use
@@ -133,32 +147,49 @@ system.cpu.dcache.total_refs                      627                       # To
 system.cpu.dcache.sampled_refs                     82                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   7.646341                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             47.418751                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.011577                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                    360                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   267                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                     627                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                    627                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   55                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  27                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                    82                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                   82                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       1512000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         4592000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        4592000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses                415                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               294                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                 709                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses                709                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.132530                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.091837                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.115656                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.115656                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      47.418751                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.011577                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.011577                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          360                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             360                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          267                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            267                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data           627                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total              627                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data          627                       # number of overall hits
+system.cpu.dcache.overall_hits::total             627                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            55                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           27                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           27                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data           82                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total             82                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data           82                       # number of overall misses
+system.cpu.dcache.overall_misses::total            82                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3080000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3080000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      1512000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      1512000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      4592000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      4592000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      4592000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      4592000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          415                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          294                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data          709                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total          709                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data          709                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total          709                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.132530                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.091837                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.115656                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.115656                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -167,30 +198,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              55                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             27                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses               82                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses              82                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2915000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1431000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      4346000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      4346000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.132530                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.091837                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.115656                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.115656                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           27                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data           82                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total           82                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data           82                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total           82                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1431000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1431000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4346000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      4346000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4346000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      4346000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.132530                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.091837                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.115656                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               107.101205                       # Cycle average of tags in use
@@ -198,30 +229,58 @@ system.cpu.l2cache.total_refs                       0                       # To
 system.cpu.l2cache.sampled_refs                   218                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                         0                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           107.101205                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.003268                       # Average percentage of cache occupancy
-system.cpu.l2cache.demand_hits                      0                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     0                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 218                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                27                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  245                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 245                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      11336000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1404000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       12740000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      12740000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               218                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              27                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                245                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               245                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate                1                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate                 1                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate                1                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst     80.120406                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     26.980800                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.002445                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000823                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.003268                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_misses::cpu.inst          163                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          218                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           27                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           27                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          163                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data           82                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           245                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          163                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data           82                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          245                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      8476000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2860000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     11336000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1404000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1404000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst      8476000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4264000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     12740000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst      8476000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4264000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     12740000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          163                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          218                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           27                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          163                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data           82                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          245                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          163                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data           82                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          245                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst            1                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst            1                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -230,30 +289,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            218                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           27                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             245                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            245                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency      8720000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1080000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency      9800000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency      9800000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate            1                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate            1                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate            1                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          163                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          218                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           27                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          163                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data           82                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          245                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          163                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data           82                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          245                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      6520000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total      8720000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1080000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      6520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3280000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total      9800000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      6520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3280000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total      9800000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 7fe95aa88a5a5c033473b851fb0f5f989f539e80..a46f1b25de4acc65adc4f718805b58d7dbba0c7a 100644 (file)
@@ -136,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -444,20 +437,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -492,20 +478,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -534,7 +513,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
index 8159ae453808040a3e2ae96721525e78574b7399..ab1ef55e9f78464b7b1dfa574640764bffd8163a 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simout
-Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 10 2012 00:18:03
-gem5 started Feb 10 2012 07:27:01
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:35:50
+gem5 executing on zizzer
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 691966ecb1fedfc33209dddf42b5921945f93afe..0109339491a642c0e5f86c6563233d46eed54c44 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000010                       # Nu
 sim_ticks                                    10000500                       # Number of ticks simulated
 final_tick                                   10000500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  48981                       # Simulator instruction rate (inst/s)
-host_tick_rate                               85336508                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 252096                       # Number of bytes of host memory used
-host_seconds                                     0.12                       # Real time elapsed on the host
-sim_insts                                        5739                       # Number of instructions simulated
+host_inst_rate                                  72927                       # Simulator instruction rate (inst/s)
+host_op_rate                                    90959                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              158457261                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221260                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
+sim_insts                                        4600                       # Number of instructions simulated
+sim_ops                                          5739                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       25856                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  17856                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -278,7 +280,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       0.391961                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.506103                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts           5739                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts           4600                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             5739                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            5094                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              37                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               345                       # The number of times a branch was mispredicted
@@ -299,7 +302,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        10622                       # Number of insts commited each cycle
-system.cpu.commit.count                          5739                       # Number of instructions committed
+system.cpu.commit.committedInsts                 4600                       # Number of instructions committed
+system.cpu.commit.committedOps                   5739                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2139                       # Number of memory references committed
 system.cpu.commit.loads                          1201                       # Number of loads committed
@@ -314,12 +318,13 @@ system.cpu.rob.rob_reads                        21205                       # Th
 system.cpu.rob.rob_writes                       22566                       # The number of ROB writes
 system.cpu.timesIdled                             180                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                            8494                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        5739                       # Number of Instructions Simulated
-system.cpu.committedInsts_total                  5739                       # Number of Instructions Simulated
-system.cpu.cpi                               3.485276                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         3.485276                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.286921                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.286921                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                        4600                       # Number of Instructions Simulated
+system.cpu.committedOps                          5739                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                  4600                       # Number of Instructions Simulated
+system.cpu.cpi                               4.348261                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.348261                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.229977                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.229977                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    37816                       # number of integer regfile reads
 system.cpu.int_regfile_writes                    7658                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                        16                       # number of floating regfile reads
@@ -331,26 +336,39 @@ system.cpu.icache.total_refs                     1559                       # To
 system.cpu.icache.sampled_refs                    297                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   5.249158                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            148.855822                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.072684                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1559                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1559                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1559                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  360                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   360                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  360                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       12552000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        12552000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       12552000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1919                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1919                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1919                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.187598                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.187598                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.187598                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34866.666667                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34866.666667                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34866.666667                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     148.855822                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.072684                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.072684                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1559                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1559                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1559                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1559                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1559                       # number of overall hits
+system.cpu.icache.overall_hits::total            1559                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          360                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           360                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          360                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            360                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          360                       # number of overall misses
+system.cpu.icache.overall_misses::total           360                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12552000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12552000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12552000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12552000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12552000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12552000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1919                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1919                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1919                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1919                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1919                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1919                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.187598                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.187598                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.187598                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34866.666667                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34866.666667                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34866.666667                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -359,27 +377,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                63                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 63                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                63                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             297                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              297                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             297                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency      9945000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency      9945000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency      9945000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.154768                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.154768                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.154768                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 33484.848485                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 33484.848485                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 33484.848485                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           63                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           63                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           63                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           63                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           63                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           63                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          297                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          297                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          297                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          297                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          297                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          297                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst      9945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total      9945000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst      9945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total      9945000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst      9945000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total      9945000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.154768                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.154768                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.154768                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 33484.848485                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 33484.848485                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 33484.848485                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 89.085552                       # Cycle average of tags in use
@@ -387,40 +408,63 @@ system.cpu.dcache.total_refs                     2331                       # To
 system.cpu.dcache.sampled_refs                    154                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  15.136364                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             89.085552                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.021749                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1702                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   609                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits                9                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                    2311                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2311                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  169                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 304                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses              2                       # number of LoadLockedReq misses
-system.cpu.dcache.demand_misses                   473                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  473                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5350500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      10725000                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency        76500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.demand_miss_latency        16075500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       16075500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1871                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2784                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2784                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.090326                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.332968                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate     0.181818                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.demand_miss_rate           0.169899                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.169899                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 31659.763314                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 35279.605263                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency        38250                       # average LoadLockedReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33986.257928                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33986.257928                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      89.085552                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021749                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021749                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1702                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1702                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          609                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            609                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data            9                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total            9                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data          2311                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2311                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2311                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2311                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          169                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           169                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          304                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          304                       # number of WriteReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data            2                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::total            2                       # number of LoadLockedReq misses
+system.cpu.dcache.demand_misses::cpu.data          473                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            473                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          473                       # number of overall misses
+system.cpu.dcache.overall_misses::total           473                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5350500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5350500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     10725000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     10725000                       # number of WriteReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data        76500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::total        76500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16075500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16075500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16075500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16075500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1871                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2784                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2784                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2784                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2784                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.090326                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.332968                       # miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.181818                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.169899                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.169899                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 31659.763314                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35279.605263                       # average WriteReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data        38250                       # average LoadLockedReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33986.257928                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33986.257928                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -429,33 +473,40 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                57                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              262                       # number of WriteReq MSHR hits
-system.cpu.dcache.LoadLockedReq_mshr_hits            2                       # number of LoadLockedReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                319                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               319                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses             112                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             42                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              154                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             154                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      3230000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1505000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      4735000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      4735000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.059861                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.046002                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.055316                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.055316                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 28839.285714                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35833.333333                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 30746.753247                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 30746.753247                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           57                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           57                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          262                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          262                       # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total            2                       # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          319                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          319                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          319                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          319                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          112                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total          112                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           42                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           42                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          154                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          154                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          154                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          154                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3230000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3230000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      4735000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      4735000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      4735000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      4735000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.059861                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.046002                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.055316                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.055316                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 28839.285714                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35833.333333                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 30746.753247                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 30746.753247                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               188.110462                       # Cycle average of tags in use
@@ -463,31 +514,67 @@ system.cpu.l2cache.total_refs                      42                       # To
 system.cpu.l2cache.sampled_refs                   362                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.116022                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           188.110462                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005741                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                    42                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                     42                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                    42                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 367                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                42                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  409                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 409                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      12613500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1452000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       14065500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      14065500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               409                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              42                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                451                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               451                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.897311                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.906874                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.906874                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34369.209809                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34571.428571                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34389.975550                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34389.975550                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    140.315748                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     47.794714                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004282                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001459                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005741                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           18                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           24                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total             42                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           18                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           24                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total              42                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           18                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           24                       # number of overall hits
+system.cpu.l2cache.overall_hits::total             42                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          279                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           88                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          367                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           42                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           42                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          279                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          130                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           409                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          279                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          130                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          409                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst      9586000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3027500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     12613500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1452000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst      9586000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4479500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     14065500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst      9586000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4479500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     14065500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          297                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          112                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          409                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           42                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           42                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          297                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          154                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          451                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          297                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          154                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          451                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.939394                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.785714                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.939394                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.844156                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.939394                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.844156                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34358.422939                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34403.409091                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34571.428571                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34358.422939                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34457.692308                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34358.422939                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34457.692308                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -496,31 +583,48 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits                5                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits                 5                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                5                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            362                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           42                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             404                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            404                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11304000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1319000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     12623000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     12623000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.885086                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.895787                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.895787                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31226.519337                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31404.761905                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31245.049505                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31245.049505                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data            5                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::total            5                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data            5                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::total            5                       # number of overall MSHR hits
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          279                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           83                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          362                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           42                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           42                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          279                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          125                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          404                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          279                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          125                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          404                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      8692000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2612000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11304000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1319000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1319000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      8692000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3931000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     12623000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      8692000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3931000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     12623000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.939394                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.741071                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.939394                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.811688                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.939394                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.811688                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31154.121864                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31469.879518                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31404.761905                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31154.121864                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        31448                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31154.121864                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        31448                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 1ee45ad85458655101f11bca06e14bdeb4f21706..a2c85dbcda7eca2da3aa28ee8b225c2286b60dc8 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,32 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=ArmInterrupts
 
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -88,7 +119,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port
 
 [system.physmem]
 type=PhysicalMemory
index 13e73ddc38b10d7f2480a069cda985aaf1a66039..ef47c4ce8828b6921bed08771ce5899b6453b7b1 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:36:01
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-atomic
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 8e7751fe7973e76da9721006902559f0e6e2560f..1e73e7e3d8170ec7d2423c287d4ea90dcaeee88f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2875500                       # Number of ticks simulated
 final_tick                                    2875500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  25921                       # Simulator instruction rate (inst/s)
-host_tick_rate                               12986430                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208728                       # Number of bytes of host memory used
-host_seconds                                     0.22                       # Real time elapsed on the host
-sim_insts                                        5739                       # Number of instructions simulated
+host_inst_rate                                 866385                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1077395                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              538148768                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211284                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+sim_insts                                        4600                       # Number of instructions simulated
+sim_ops                                          5739                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       22944                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  18452                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     3648                       # Number of bytes written to this memory
@@ -65,7 +67,8 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.numCycles                             5752                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5739                       # Number of instructions executed
+system.cpu.committedInsts                        4600                       # Number of instructions committed
+system.cpu.committedOps                          5739                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                         185                       # number of times a function call or return occured
index d881a3977ef596bc79f0556e05ed9b1d4a2d6cbc..1d87891a219f59bc33fc53430446a3f70d790039 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,16 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +106,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +120,21 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=ArmInterrupts
+
 [system.cpu.itb]
 type=ArmTLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=ArmTableWalker
+max_backoff=100000
+min_backoff=0
+sys=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +147,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +169,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
index 25474862b29082d6a9fb1107c1e2085be02093d6..378a682d493255d8d1b53648dbad7aa59a525657 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:16:21
-gem5 started Jan 23 2012 04:24:50
+gem5 compiled Feb 11 2012 13:10:40
+gem5 started Feb 11 2012 15:36:11
 gem5 executing on zizzer
-command line: build/ARM_SE/gem5.opt -d build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM_SE/tests/opt/quick/00.hello/arm/linux/simple-timing
+command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/fast/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 9108e20ee27851ac6bae43dd1902ff81893ea597..a93efeca8fe513e436f1a534b5ae623d1819bef0 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000026                       # Nu
 sim_ticks                                    26361000                       # Number of ticks simulated
 final_tick                                   26361000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  20483                       # Simulator instruction rate (inst/s)
-host_tick_rate                               95024596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 217432                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
-sim_insts                                        5682                       # Number of instructions simulated
+host_inst_rate                                 456104                       # Simulator instruction rate (inst/s)
+host_op_rate                                   565540                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2619225899                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 220184                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
+sim_insts                                        4574                       # Number of instructions simulated
+sim_ops                                          5682                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       22400                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  14400                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -64,7 +66,8 @@ system.cpu.workload.num_syscalls                   13                       # Nu
 system.cpu.numCycles                            52722                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5682                       # Number of instructions executed
+system.cpu.committedInsts                        4574                       # Number of instructions committed
+system.cpu.committedOps                          5682                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  4985                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     16                       # Number of float alu accesses
 system.cpu.num_func_calls                         185                       # number of times a function call or return occured
@@ -88,26 +91,39 @@ system.cpu.icache.total_refs                     4373                       # To
 system.cpu.icache.sampled_refs                    241                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.145228                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            114.525744                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.055921                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   4373                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    4373                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   4373                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  241                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   241                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  241                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       12824000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        12824000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       12824000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               4614                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                4614                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               4614                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.052232                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.052232                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.052232                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 53211.618257                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 53211.618257                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 53211.618257                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     114.525744                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.055921                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.055921                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         4373                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4373                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4373                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4373                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4373                       # number of overall hits
+system.cpu.icache.overall_hits::total            4373                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          241                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           241                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          241                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            241                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          241                       # number of overall misses
+system.cpu.icache.overall_misses::total           241                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12824000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12824000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12824000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12824000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12824000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12824000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         4614                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         4614                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         4614                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         4614                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         4614                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         4614                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.052232                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.052232                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.052232                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53211.618257                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 53211.618257                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 53211.618257                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -116,26 +132,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             241                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              241                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             241                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     12101000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     12101000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     12101000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.052232                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.052232                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.052232                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 50211.618257                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 50211.618257                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          241                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          241                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          241                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          241                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          241                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          241                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12101000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12101000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12101000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12101000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12101000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.052232                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.052232                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.052232                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50211.618257                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.937979                       # Cycle average of tags in use
@@ -143,36 +157,57 @@ system.cpu.dcache.total_refs                     1941                       # To
 system.cpu.dcache.sampled_refs                    141                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.765957                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             82.937979                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020249                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1049                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   870                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits               11                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits                11                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits                    1919                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1919                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   98                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  43                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   141                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  141                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        4816000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       2408000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         7224000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        7224000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1147                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               913                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses           11                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses            11                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2060                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2060                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.085440                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.047097                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.068447                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.068447                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 49142.857143                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 51234.042553                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 51234.042553                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      82.937979                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020249                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020249                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1049                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1049                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          870                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            870                       # number of WriteReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data           11                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::total           11                       # number of LoadLockedReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data           11                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::total           11                       # number of StoreCondReq hits
+system.cpu.dcache.demand_hits::cpu.data          1919                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1919                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1919                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1919                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           98                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            98                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           43                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           43                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          141                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            141                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          141                       # number of overall misses
+system.cpu.dcache.overall_misses::total           141                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4816000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4816000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2408000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2408000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7224000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7224000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7224000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7224000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1147                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1147                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          913                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::total           11                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::total           11                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2060                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2060                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2060                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2060                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085440                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.047097                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.068447                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.068447                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49142.857143                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 51234.042553                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 51234.042553                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -181,30 +216,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              98                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             43                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              141                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             141                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      4522000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2279000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      6801000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      6801000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.085440                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.047097                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.068447                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.068447                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 46142.857143                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 48234.042553                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           98                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           98                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           43                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          141                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          141                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          141                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4522000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4522000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2279000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2279000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      6801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      6801000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      6801000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      6801000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.085440                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.047097                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.068447                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.068447                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46142.857143                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48234.042553                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               153.954484                       # Cycle average of tags in use
@@ -212,31 +247,67 @@ system.cpu.l2cache.total_refs                      32                       # To
 system.cpu.l2cache.sampled_refs                   307                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.104235                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           153.954484                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.004698                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                    32                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                     32                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                    32                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 307                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                43                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  350                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 350                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      15964000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2236000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       18200000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      18200000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               339                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              43                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                382                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               382                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.905605                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.916230                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.916230                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    105.806385                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     48.148099                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003229                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001469                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004698                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst           16                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data           16                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total             32                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst           16                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data           16                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total              32                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst           16                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data           16                       # number of overall hits
+system.cpu.l2cache.overall_hits::total             32                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          225                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           82                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          307                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           43                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           43                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          225                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          125                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           350                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          225                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          125                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          350                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11700000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4264000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     15964000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2236000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2236000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11700000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6500000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18200000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11700000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6500000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18200000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          241                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           98                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          339                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           43                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          241                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          141                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          382                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          241                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          141                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          382                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.933610                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.836735                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.933610                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.886525                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.933610                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.886525                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -245,30 +316,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            307                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           43                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             350                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            350                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12280000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1720000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     14000000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     14000000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.905605                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.916230                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.916230                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          225                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           82                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          307                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           43                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          225                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          125                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          350                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          225                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          125                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          350                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9000000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1720000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1720000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14000000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14000000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.836735                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.886525                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.933610                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.886525                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 1ccb30b9cdd056d5e09cff912e63a6a41136af6d..600677fb9691c695f948edef14d78e9f1f5fab5f 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=MipsInterrupts
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 677598e8719710e32f8fb10b5ea7f610be2d1faa..9f59be0cec13f12f5e56e812b95ac6c66b674a93 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:29
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:30
 gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/inorder-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 78172e7b6f91b9364465ee5fbdeaf8624b404218..6cd55fbff91d3256ac28c77169e461985884789c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000020                       # Nu
 sim_ticks                                    19785000                       # Number of ticks simulated
 final_tick                                   19785000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  71616                       # Simulator instruction rate (inst/s)
-host_tick_rate                              243111037                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208328                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                 101976                       # Simulator instruction rate (inst/s)
+host_op_rate                                   101944                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              346042004                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210372                       # Number of bytes of host memory used
+host_seconds                                     0.06                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       29120                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  20288                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -54,9 +56,10 @@ system.cpu.comNops                                657                       # Nu
 system.cpu.comNonSpec                              10                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                               2155                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5827                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total                  5827                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                        5827                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5827                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                  5827                       # Number of Instructions committed (Total)
 system.cpu.cpi                               6.790973                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         6.790973                       # CPI: Total CPI of All Threads
@@ -110,26 +113,39 @@ system.cpu.icache.total_refs                      443                       # To
 system.cpu.icache.sampled_refs                    319                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   1.388715                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            148.138598                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.072333                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                    443                       # number of ReadReq hits
-system.cpu.icache.demand_hits                     443                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                    443                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  341                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   341                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  341                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       19027500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        19027500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       19027500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses                784                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                 784                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses                784                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.434949                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.434949                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.434949                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55799.120235                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55799.120235                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55799.120235                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     148.138598                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.072333                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.072333                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          443                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             443                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           443                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              443                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          443                       # number of overall hits
+system.cpu.icache.overall_hits::total             443                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          341                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           341                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          341                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            341                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          341                       # number of overall misses
+system.cpu.icache.overall_misses::total           341                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19027500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19027500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19027500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19027500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19027500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19027500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst          784                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total          784                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst          784                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total          784                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst          784                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total          784                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.434949                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.434949                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.434949                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55799.120235                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55799.120235                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55799.120235                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        29000                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -138,27 +154,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets        29000                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                22                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 22                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                22                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             319                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              319                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             319                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     16952500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     16952500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     16952500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.406888                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.406888                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.406888                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53142.633229                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53142.633229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53142.633229                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           22                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           22                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           22                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           22                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           22                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           22                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          319                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          319                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          319                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          319                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          319                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          319                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     16952500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     16952500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     16952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     16952500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     16952500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     16952500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.406888                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.406888                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.406888                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53142.633229                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53142.633229                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53142.633229                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 89.732679                       # Cycle average of tags in use
@@ -166,32 +185,49 @@ system.cpu.dcache.total_refs                     1838                       # To
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.318841                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             89.732679                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.021907                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1075                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   763                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1838                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1838                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   89                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 162                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   251                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  251                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        5072500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       8912000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        13984500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       13984500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1164                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2089                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2089                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.076460                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.175135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.120153                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.120153                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 56994.382022                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55012.345679                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 55715.139442                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 55715.139442                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      89.732679                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021907                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021907                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1075                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1075                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          763                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            763                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1838                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1838                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1838                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1838                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           89                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            89                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          162                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          162                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          251                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            251                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          251                       # number of overall misses
+system.cpu.dcache.overall_misses::total           251                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      5072500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      5072500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      8912000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      8912000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13984500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13984500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13984500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13984500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2089                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.076460                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.175135                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.120153                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.120153                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56994.382022                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55012.345679                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55715.139442                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55715.139442                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      1153500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -200,32 +236,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 50152.173913                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                 2                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              111                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                113                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               113                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              87                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      4702500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2746000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7448500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7448500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.074742                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 54051.724138                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53843.137255                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53974.637681                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53974.637681                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            2                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            2                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          111                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          111                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          113                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          113                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          113                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4702500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4702500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2746000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2746000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7448500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7448500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7448500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7448500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54051.724138                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53843.137255                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53974.637681                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53974.637681                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               205.469583                       # Cycle average of tags in use
@@ -233,31 +275,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   404                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.004950                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           205.469583                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006270                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 404                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  455                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 455                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      21170500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2682500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       23853000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      23853000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               406                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                457                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               457                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.995074                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995624                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995624                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52402.227723                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52598.039216                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52424.175824                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52424.175824                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    149.779235                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     55.690348                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004571                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001700                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006270                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          317                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          404                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          317                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           455                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          317                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          455                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     16585500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4585000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     21170500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2682500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2682500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     16585500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7267500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     23853000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     16585500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7267500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     23853000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          319                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          406                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          319                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          457                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          319                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          457                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993730                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993730                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993730                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52320.189274                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52701.149425                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52598.039216                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52320.189274                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52663.043478                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52320.189274                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52663.043478                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -266,30 +341,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            404                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             455                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            455                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     16247000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2058000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     18305000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     18305000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.995074                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995624                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995624                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40215.346535                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40352.941176                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40230.769231                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40230.769231                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          317                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          404                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          317                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          455                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          317                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          455                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12717500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3529500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     16247000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2058000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2058000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12717500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5587500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     18305000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12717500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5587500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     18305000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993730                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40568.965517                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40352.941176                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40118.296530                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40489.130435                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 508c3cad4df613de863c3765ee8bedc54f25723e..00305a8e7a2dc4dafcd7b286214c50db2eb9092a 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=MipsInterrupts
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index eb1e6f70f57922521fe4ffdb6fc0dd035e88e973..afa2676780e192a5b0f63a3b1daf08ade0d8d473 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:41
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:39
 gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/o3-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index e49d82dd942143aa388ea819ef9a6459a1d3b962..9ff42644b397ef2ea53c6a9b8b4dbc7be0fa4169 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    12272500                       # Number of ticks simulated
 final_tick                                   12272500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  65845                       # Simulator instruction rate (inst/s)
-host_tick_rate                              156294886                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208908                       # Number of bytes of host memory used
-host_seconds                                     0.08                       # Real time elapsed on the host
+host_inst_rate                                  97350                       # Simulator instruction rate (inst/s)
+host_op_rate                                    97317                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              230983195                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211060                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5169                       # Number of instructions simulated
+sim_ops                                          5169                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30400                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  21312                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -255,6 +257,7 @@ system.cpu.iew.wb_rate                       0.289986                       # in
 system.cpu.iew.wb_fanout                     0.698936                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5826                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             5826                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            4197                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              10                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               357                       # The number of times a branch was mispredicted
@@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        11871                       # Number of insts commited each cycle
-system.cpu.commit.count                          5826                       # Number of instructions committed
+system.cpu.commit.committedInsts                 5826                       # Number of instructions committed
+system.cpu.commit.committedOps                   5826                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2089                       # Number of memory references committed
 system.cpu.commit.loads                          1164                       # Number of loads committed
@@ -291,6 +295,7 @@ system.cpu.rob.rob_writes                       20794                       # Th
 system.cpu.timesIdled                             251                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           11938                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5169                       # Number of Instructions Simulated
+system.cpu.committedOps                          5169                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5169                       # Number of Instructions Simulated
 system.cpu.cpi                               4.748694                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         4.748694                       # CPI: Total CPI of All Threads
@@ -307,26 +312,39 @@ system.cpu.icache.total_refs                     1363                       # To
 system.cpu.icache.sampled_refs                    336                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   4.056548                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            161.224498                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.078723                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1363                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1363                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1363                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  418                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   418                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  418                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15148000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15148000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15148000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1781                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1781                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1781                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.234700                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.234700                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.234700                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36239.234450                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36239.234450                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36239.234450                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     161.224498                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.078723                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.078723                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1363                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1363                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1363                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1363                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1363                       # number of overall hits
+system.cpu.icache.overall_hits::total            1363                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          418                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           418                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          418                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            418                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          418                       # number of overall misses
+system.cpu.icache.overall_misses::total           418                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15148000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15148000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15148000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15148000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15148000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15148000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1781                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1781                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1781                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1781                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1781                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1781                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.234700                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.234700                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.234700                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36239.234450                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36239.234450                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36239.234450                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -335,27 +353,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                82                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 82                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                82                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             336                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              336                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             336                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     11784000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     11784000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     11784000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.188658                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.188658                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.188658                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35071.428571                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35071.428571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35071.428571                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           82                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           82                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           82                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           82                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           82                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           82                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          336                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          336                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          336                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          336                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          336                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          336                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11784000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11784000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11784000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11784000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11784000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11784000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.188658                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.188658                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.188658                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35071.428571                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35071.428571                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35071.428571                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 92.121984                       # Cycle average of tags in use
@@ -363,32 +384,49 @@ system.cpu.dcache.total_refs                     2380                       # To
 system.cpu.dcache.sampled_refs                    142                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  16.760563                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             92.121984                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.022491                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1802                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   578                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2380                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2380                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  133                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 347                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   480                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  480                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        4767500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      11508000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        16275500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       16275500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1935                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2860                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2860                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.068734                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.375135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.167832                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.167832                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35845.864662                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33164.265130                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33907.291667                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33907.291667                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      92.121984                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.022491                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.022491                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1802                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1802                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          578                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            578                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2380                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2380                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2380                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2380                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          133                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           133                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          347                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          347                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          480                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            480                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          480                       # number of overall misses
+system.cpu.dcache.overall_misses::total           480                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4767500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4767500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     11508000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     11508000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     16275500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     16275500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     16275500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     16275500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1935                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1935                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2860                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2860                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2860                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2860                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.068734                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.375135                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.167832                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.167832                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35845.864662                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33164.265130                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33907.291667                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33907.291667                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -397,32 +435,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                42                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              296                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                338                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               338                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              91                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              142                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             142                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      3272000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1836000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      5108000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      5108000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.047028                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.049650                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.049650                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35956.043956                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        36000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35971.830986                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35971.830986                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           42                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           42                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          296                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          296                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          338                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          338                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          338                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          338                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           91                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          142                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          142                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      3272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      3272000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1836000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1836000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5108000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5108000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5108000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.047028                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.049650                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.049650                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35956.043956                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        36000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35971.830986                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35971.830986                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               221.521956                       # Cycle average of tags in use
@@ -430,31 +474,64 @@ system.cpu.l2cache.total_refs                       3                       # To
 system.cpu.l2cache.sampled_refs                   424                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.007075                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           221.521956                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006760                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     3                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 424                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  475                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 475                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      14561000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1760500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       16321500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      16321500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               427                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                478                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               478                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.992974                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.993724                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.993724                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34341.981132                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34519.607843                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34361.052632                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34361.052632                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    163.434563                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     58.087393                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004988                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001773                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006760                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            3                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            3                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            3                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          333                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           91                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          424                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          333                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          142                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           475                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          333                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          142                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          475                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11418500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      3142500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14561000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1760500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1760500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11418500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4903000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16321500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11418500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4903000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16321500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          336                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           91                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          427                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          336                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          142                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          478                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          336                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          142                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          478                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.991071                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.991071                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.991071                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34289.789790                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34532.967033                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34519.607843                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34289.789790                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34528.169014                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34289.789790                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34528.169014                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -463,30 +540,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            424                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             475                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            475                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     13198000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1598500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     14796500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     14796500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.992974                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.993724                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.993724                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31127.358491                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31343.137255                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31150.526316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31150.526316                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          333                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           91                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          424                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          333                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          142                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          475                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          333                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          142                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          475                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10340500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2857500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13198000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1598500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1598500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10340500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4456000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14796500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10340500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4456000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14796500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.991071                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.991071                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.991071                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31052.552553                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31401.098901                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31343.137255                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31052.552553                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31380.281690                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31052.552553                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31380.281690                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8bad8df1338e09c4aaf5087b6fda1eda0d8450ff..9563d85bf26307b965c84ac68acedfe465a5aff6 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=MipsTLB
 size=64
 
+[system.cpu.interrupts]
+type=MipsInterrupts
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
index 4b9270f18cb461198c51e0557849c6315a3dcb56..7716b33a4de04a7bbac8dce48be08d461132674b 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:47
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:41
 gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-atomic
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 397c3f1f63ce431d43f2c03fb6dcd2bf9bc53420..9ae16c4c69e5ab708051fd6e89fb79eaade8db3c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2913500                       # Number of ticks simulated
 final_tick                                    2913500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 231601                       # Simulator instruction rate (inst/s)
-host_tick_rate                              115720913                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 199128                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
+host_inst_rate                                1078442                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1075012                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              535874927                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 200784                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  23312                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     3658                       # Number of bytes written to this memory
@@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls                    8                       # Nu
 system.cpu.numCycles                             5828                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5827                       # Number of instructions executed
+system.cpu.committedInsts                        5827                       # Number of instructions committed
+system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
index e5b4b16c88a7beefe915f22a939720b0e6717d1a..da3c93787cbf9873c3de30f8bb41ab9129fd78a5 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=MipsTLB
 size=64
 
+[system.cpu.interrupts]
+type=MipsInterrupts
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
@@ -131,6 +144,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index f6eaf03f7ded350690794188f1a7ac109daddb41..ac3ff100c7b42a3839483fca6f0758c2be8f5458 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:56
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:52
 gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing-ruby
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 65d0aed82e1f170760665faa8d031561802449cc..8087912dcad884ba2b7113fa01666cddee66275b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000293                       # Nu
 sim_ticks                                      292960                       # Number of ticks simulated
 final_tick                                     292960                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55801                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2804966                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 220172                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                  71598                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71583                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                3598224                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221836                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27687                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  23312                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     3658                       # Number of bytes written to this memory
@@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls                    8                       # Nu
 system.cpu.numCycles                           292960                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5827                       # Number of instructions executed
+system.cpu.committedInsts                        5827                       # Number of instructions committed
+system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
index 36444e22de60b244286d2f38fe3de282af285a39..3cd70d03a4811d1e5ce4463f686f3a1d7f09686e 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=MipsInterrupts
+
 [system.cpu.itb]
 type=MipsTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 7525d1ad5e22e48746885c013bb52afdd65548fd..29b03eaffc7dbaf164fe62c4afe2fce943f6b894 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:56:13
-gem5 started Jan 23 2012 04:23:52
+gem5 compiled Feb 11 2012 13:07:32
+gem5 started Feb 11 2012 13:54:50
 gem5 executing on zizzer
-command line: build/MIPS_SE/gem5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
+command line: build/MIPS/gem5.fast -d build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/fast/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 566ce19a46ce9cf0f6538dc2e967b8d4034e4751..5a05207539336fc5836cada6f905f25419842f8f 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000032                       # Nu
 sim_ticks                                    32088000                       # Number of ticks simulated
 final_tick                                   32088000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 263412                       # Simulator instruction rate (inst/s)
-host_tick_rate                             1449372115                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 207940                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 603210                       # Simulator instruction rate (inst/s)
+host_op_rate                                   602100                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3309896144                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 209992                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5827                       # Number of instructions simulated
+sim_ops                                          5827                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28096                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  19264                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -40,7 +42,8 @@ system.cpu.workload.num_syscalls                    8                       # Nu
 system.cpu.numCycles                            64176                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5827                       # Number of instructions executed
+system.cpu.committedInsts                        5827                       # Number of instructions committed
+system.cpu.committedOps                          5827                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  5126                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      2                       # Number of float alu accesses
 system.cpu.num_func_calls                         194                       # number of times a function call or return occured
@@ -64,26 +67,39 @@ system.cpu.icache.total_refs                     5526                       # To
 system.cpu.icache.sampled_refs                    303                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  18.237624                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            132.493866                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.064694                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   5526                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    5526                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   5526                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  303                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   303                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  303                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       16884000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        16884000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       16884000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               5829                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                5829                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               5829                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.051981                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.051981                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.051981                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55722.772277                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55722.772277                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55722.772277                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     132.493866                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.064694                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.064694                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5526                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5526                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5526                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5526                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5526                       # number of overall hits
+system.cpu.icache.overall_hits::total            5526                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          303                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           303                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          303                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            303                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          303                       # number of overall misses
+system.cpu.icache.overall_misses::total           303                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     16884000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     16884000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     16884000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     16884000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     16884000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     16884000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5829                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5829                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5829                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5829                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5829                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5829                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.051981                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.051981                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.051981                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -92,26 +108,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             303                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              303                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             303                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     15975000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     15975000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     15975000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.051981                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.051981                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.051981                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52722.772277                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52722.772277                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52722.772277                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          303                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          303                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          303                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          303                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          303                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          303                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15975000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15975000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15975000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15975000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15975000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15975000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.051981                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 87.458397                       # Cycle average of tags in use
@@ -119,32 +133,49 @@ system.cpu.dcache.total_refs                     1951                       # To
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  14.137681                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             87.458397                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.021352                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1077                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   874                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1951                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1951                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   87                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  51                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        4872000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       2856000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        7728000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1164                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               925                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2089                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2089                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.074742                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.055135                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.066060                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.066060                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      87.458397                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.021352                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.021352                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1077                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1077                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          874                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            874                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1951                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1951                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1951                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1951                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            87                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           51                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           51                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.dcache.overall_misses::total           138                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      4872000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      4872000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2856000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2856000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1164                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          925                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2089                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2089                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2089                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2089                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.074742                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.055135                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.066060                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.066060                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -153,30 +184,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              87                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             51                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      4611000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2703000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.074742                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.055135                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.066060                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.066060                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           87                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           51                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      4611000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      4611000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2703000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2703000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.074742                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.055135                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.066060                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               188.045319                       # Cycle average of tags in use
@@ -184,31 +215,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   388                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005155                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           188.045319                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005739                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 388                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                51                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  439                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 439                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      20176000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2652000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       22828000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      22828000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               390                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              51                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                441                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               441                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.994872                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995465                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995465                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    133.837577                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     54.207742                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004084                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001654                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005739                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          301                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           87                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          388                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           51                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           51                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          301                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           439                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          301                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          439                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15652000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      4524000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     20176000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2652000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2652000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15652000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7176000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     22828000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15652000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7176000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22828000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          303                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           87                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          390                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           51                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          303                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          441                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          303                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          441                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993399                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993399                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993399                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -217,30 +281,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            388                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           51                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             439                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            439                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     15520000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2040000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     17560000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     17560000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994872                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995465                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995465                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           87                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          388                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           51                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          439                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          439                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     12040000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      3480000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     15520000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2040000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     12040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17560000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     12040000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17560000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993399                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index fb36c719f94a8d57c843fd7d900e5744b76bb545..eed88a81d4052169a57865066eb5ac22b402f8d1 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -53,6 +60,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -70,6 +78,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -81,6 +90,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -89,6 +99,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -126,20 +137,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -425,20 +429,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -446,6 +443,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=PowerInterrupts
+
 [system.cpu.itb]
 type=PowerTLB
 size=64
@@ -461,20 +461,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 8cb2415425b3f3784669d74e505c25b3d0464550..8e7d0115901aa92dcf9ee2f2c9b351a6631b0c27 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:58:39
-gem5 started Jan 23 2012 04:24:00
+gem5 compiled Feb 11 2012 13:07:55
+gem5 started Feb 11 2012 13:55:01
 gem5 executing on zizzer
-command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/o3-timing
+command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 5a2ad1a0a46c8714c05fc87fa77d90176a01ba5a..7c789f56819732050571088f94eeeec4f7cc285c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000011                       # Nu
 sim_ticks                                    10910500                       # Number of ticks simulated
 final_tick                                   10910500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  80565                       # Simulator instruction rate (inst/s)
-host_tick_rate                              151515044                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 205800                       # Number of bytes of host memory used
-host_seconds                                     0.07                       # Real time elapsed on the host
+host_inst_rate                                 114395                       # Simulator instruction rate (inst/s)
+host_op_rate                                   114354                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              215042277                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207892                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                        5800                       # Number of instructions simulated
+sim_ops                                          5800                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28608                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  22016                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -255,6 +257,7 @@ system.cpu.iew.wb_rate                       0.361058                       # in
 system.cpu.iew.wb_fanout                     0.623674                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts           5800                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             5800                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            4208                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              16                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               252                       # The number of times a branch was mispredicted
@@ -275,7 +278,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total         9777                       # Number of insts commited each cycle
-system.cpu.commit.count                          5800                       # Number of instructions committed
+system.cpu.commit.committedInsts                 5800                       # Number of instructions committed
+system.cpu.commit.committedOps                   5800                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           2008                       # Number of memory references committed
 system.cpu.commit.loads                           962                       # Number of loads committed
@@ -291,6 +295,7 @@ system.cpu.rob.rob_writes                       20673                       # Th
 system.cpu.timesIdled                             218                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                           11389                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                        5800                       # Number of Instructions Simulated
+system.cpu.committedOps                          5800                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                  5800                       # Number of Instructions Simulated
 system.cpu.cpi                               3.762414                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         3.762414                       # CPI: Total CPI of All Threads
@@ -306,26 +311,39 @@ system.cpu.icache.total_refs                     1291                       # To
 system.cpu.icache.sampled_refs                    351                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   3.678063                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            169.539680                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.082783                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1291                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1291                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1291                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  420                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   420                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  420                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15114500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15114500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15114500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1711                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1711                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1711                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.245470                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.245470                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.245470                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 35986.904762                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 35986.904762                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 35986.904762                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     169.539680                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.082783                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.082783                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1291                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1291                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1291                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1291                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1291                       # number of overall hits
+system.cpu.icache.overall_hits::total            1291                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          420                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           420                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          420                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            420                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          420                       # number of overall misses
+system.cpu.icache.overall_misses::total           420                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15114500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15114500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15114500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15114500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15114500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15114500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1711                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1711                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1711                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1711                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1711                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1711                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.245470                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.245470                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.245470                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35986.904762                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35986.904762                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35986.904762                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -334,27 +352,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                69                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 69                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                69                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             351                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              351                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             351                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     12207500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     12207500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     12207500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.205143                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.205143                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.205143                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 34779.202279                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 34779.202279                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 34779.202279                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           69                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           69                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           69                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           69                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           69                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           69                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          351                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          351                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          351                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          351                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          351                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          351                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12207500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12207500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12207500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12207500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12207500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12207500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.205143                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.205143                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.205143                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34779.202279                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34779.202279                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34779.202279                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 66.296919                       # Cycle average of tags in use
@@ -362,32 +383,49 @@ system.cpu.dcache.total_refs                     2156                       # To
 system.cpu.dcache.sampled_refs                    105                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  20.533333                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             66.296919                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.016186                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1428                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   728                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2156                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2156                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   88                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 318                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   406                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  406                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        2947000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      10802500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        13749500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       13749500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1516                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses              1046                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2562                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2562                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.058047                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.304015                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.158470                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.158470                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 33488.636364                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 33970.125786                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 33865.763547                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 33865.763547                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      66.296919                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.016186                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.016186                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1428                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1428                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          728                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            728                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2156                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2156                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2156                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2156                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           88                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            88                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          318                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          318                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          406                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            406                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          406                       # number of overall misses
+system.cpu.dcache.overall_misses::total           406                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      2947000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      2947000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     10802500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     10802500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     13749500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     13749500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     13749500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     13749500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1516                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1516                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data         1046                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total         1046                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2562                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2562                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2562                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2562                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.058047                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.304015                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.158470                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.158470                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 33488.636364                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33970.125786                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 33865.763547                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 33865.763547                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -396,32 +434,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                31                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              270                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                301                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               301                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              57                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             48                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              105                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             105                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      1963500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      1751000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      3714500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      3714500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.037599                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.045889                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.040984                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.040984                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 34447.368421                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 36479.166667                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35376.190476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35376.190476                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           31                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           31                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          270                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          270                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          301                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          301                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          301                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           57                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           57                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           48                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           48                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          105                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          105                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          105                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          105                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      1963500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      1963500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      1751000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      1751000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      3714500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      3714500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      3714500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      3714500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.037599                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.045889                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.040984                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.040984                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 34447.368421                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36479.166667                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35376.190476                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35376.190476                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               200.613051                       # Cycle average of tags in use
@@ -429,31 +473,67 @@ system.cpu.l2cache.total_refs                       9                       # To
 system.cpu.l2cache.sampled_refs                   399                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.022556                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           200.613051                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006122                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     9                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      9                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     9                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 399                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                48                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  447                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 447                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      13714000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      1678500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       15392500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      15392500                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               408                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              48                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                456                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               456                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.977941                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.980263                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.980263                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34370.927318                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34968.750000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34435.123043                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34435.123043                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    168.132824                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     32.480228                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005131                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000991                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006122                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            7                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              9                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            7                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               9                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            7                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              9                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          344                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          399                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           48                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           48                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          344                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          103                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           447                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          344                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          103                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          447                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11818500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      1895500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     13714000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      1678500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      1678500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11818500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      3574000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     15392500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11818500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      3574000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     15392500                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          351                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           57                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          408                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           48                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           48                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          351                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          105                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          456                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          351                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          105                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          456                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.980057                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.964912                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.980057                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.980952                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.980057                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.980952                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34356.104651                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34463.636364                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34968.750000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34356.104651                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34699.029126                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34356.104651                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34699.029126                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -462,30 +542,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            399                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           48                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             447                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            447                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12434000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      1526000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     13960000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     13960000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.977941                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.980263                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.980263                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31162.907268                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31791.666667                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31230.425056                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31230.425056                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          344                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          399                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           48                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           48                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          344                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          103                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          447                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          344                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          103                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          447                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10708500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1725500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12434000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      1526000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      1526000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10708500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      3251500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     13960000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10708500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      3251500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     13960000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.980057                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.964912                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.980057                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.980952                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.980057                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.980952                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31129.360465                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31372.727273                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31791.666667                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31129.360465                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31567.961165                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31129.360465                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31567.961165                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f4325cdaeefb192927f349c056291fb4074e81ca..252e46831d4a799062d18c15742f0338a49f0319 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,17 +30,19 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 UnifiedTLB=true
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -41,6 +50,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -55,6 +65,9 @@ icache_port=system.membus.port[2]
 type=PowerTLB
 size=64
 
+[system.cpu.interrupts]
+type=PowerInterrupts
+
 [system.cpu.itb]
 type=PowerTLB
 size=64
index ef2f9ace605fb0d42bdeee5968e19331c8813f9f..2b3bb9fb6ff2de3a81f89432ad12ca96d5c0692b 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 03:58:39
-gem5 started Jan 23 2012 04:24:03
+gem5 compiled Feb 11 2012 13:07:55
+gem5 started Feb 11 2012 13:55:02
 gem5 executing on zizzer
-command line: build/POWER_SE/gem5.opt -d build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER_SE/tests/opt/quick/00.hello/power/linux/simple-atomic
+command line: build/POWER/gem5.fast -d build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/fast/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 5070ee2a1f9d106d286d965436162a758eea19e7..5d83b2bac6053740b0b5fca7a70f0bfd73f9b8d0 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2900000                       # Number of ticks simulated
 final_tick                                    2900000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 305071                       # Simulator instruction rate (inst/s)
-host_tick_rate                              152367478                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 196296                       # Number of bytes of host memory used
-host_seconds                                     0.02                       # Real time elapsed on the host
+host_inst_rate                                 430782                       # Simulator instruction rate (inst/s)
+host_op_rate                                   430227                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              214814147                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 197864                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5801                       # Number of instructions simulated
+sim_ops                                          5801                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26925                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  23204                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     4209                       # Number of bytes written to this memory
@@ -41,7 +43,8 @@ system.cpu.workload.num_syscalls                    9                       # Nu
 system.cpu.numCycles                             5801                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5801                       # Number of instructions executed
+system.cpu.committedInsts                        5801                       # Number of instructions committed
+system.cpu.committedOps                          5801                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  5706                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                     22                       # Number of float alu accesses
 system.cpu.num_func_calls                         200                       # number of times a function call or return occured
index 32a7f4ad9f9c19adbb94a755437beca21dd0df19..eed996339db1803a7d60d1b85847847ec7c528fb 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 024efc4d5c92cb0d880be32db1fb26f903c54bab..13c85267ecd18a28744a0a895bed43b99d63340b 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:09
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:12
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 18201500 because target called exit()
index 1ce5039d0b656bd3db2eba2033dc9910f1351e8a..99d0ed042493584c95c054cb95a1371ad634944d 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18201500                       # Number of ticks simulated
 final_tick                                   18201500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  29731                       # Simulator instruction rate (inst/s)
-host_tick_rate                              101330259                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213072                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                  71915                       # Simulator instruction rate (inst/s)
+host_op_rate                                    71898                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              245008016                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211144                       # Number of bytes of host memory used
+host_seconds                                     0.07                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27072                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  18496                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -36,9 +38,10 @@ system.cpu.comNops                                173                       # Nu
 system.cpu.comNonSpec                             106                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                               2537                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                        5340                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total                  5340                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                        5340                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                          5340                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                  5340                       # Number of Instructions committed (Total)
 system.cpu.cpi                               6.817228                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         6.817228                       # CPI: Total CPI of All Threads
@@ -92,26 +95,39 @@ system.cpu.icache.total_refs                      791                       # To
 system.cpu.icache.sampled_refs                    291                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   2.718213                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            136.669321                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.066733                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                    791                       # number of ReadReq hits
-system.cpu.icache.demand_hits                     791                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                    791                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  347                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   347                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  347                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       19110500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        19110500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       19110500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1138                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1138                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1138                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.304921                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.304921                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.304921                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55073.487032                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55073.487032                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55073.487032                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     136.669321                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.066733                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.066733                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst          791                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total             791                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst           791                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total              791                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst          791                       # number of overall hits
+system.cpu.icache.overall_hits::total             791                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          347                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           347                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          347                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            347                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          347                       # number of overall misses
+system.cpu.icache.overall_misses::total           347                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     19110500                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     19110500                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     19110500                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     19110500                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     19110500                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     19110500                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1138                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1138                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1138                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1138                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1138                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1138                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.304921                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.304921                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.304921                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55073.487032                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55073.487032                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55073.487032                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets       104500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -120,27 +136,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets 34833.333333                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                56                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 56                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                56                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             291                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              291                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             291                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     15470000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     15470000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     15470000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.255712                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.255712                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.255712                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 53161.512027                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 53161.512027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 53161.512027                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           56                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           56                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           56                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           56                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           56                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           56                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          291                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          291                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          291                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          291                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          291                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          291                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15470000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15470000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15470000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15470000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15470000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15470000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.255712                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.255712                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.255712                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53161.512027                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53161.512027                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53161.512027                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.859932                       # Cycle average of tags in use
@@ -148,32 +167,49 @@ system.cpu.dcache.total_refs                     1049                       # To
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   7.770370                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             82.859932                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020229                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                    657                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   392                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1049                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1049                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   59                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 281                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   340                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  340                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3290500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      15457500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        18748000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       18748000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses                716                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                1389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               1389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.082402                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.417533                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.244780                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.244780                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 55771.186441                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 55008.896797                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 55141.176471                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 55141.176471                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      82.859932                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020229                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020229                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          657                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             657                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          392                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            392                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1049                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1049                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1049                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1049                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           59                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            59                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          281                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          281                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          340                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            340                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          340                       # number of overall misses
+system.cpu.dcache.overall_misses::total           340                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3290500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3290500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     15457500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     15457500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     18748000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     18748000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     18748000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     18748000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          673                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         1389                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.082402                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.417533                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.244780                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.244780                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55771.186441                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55008.896797                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55141.176471                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55141.176471                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      2259500                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -182,32 +218,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 50211.111111                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                 5                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              200                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                205                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               205                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             81                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              135                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             135                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2865500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      4327000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7192500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7192500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.075419                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.120357                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.097192                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.097192                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53064.814815                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53419.753086                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 53277.777778                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 53277.777778                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          200                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          200                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          205                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          205                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          205                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          205                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           54                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           81                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           81                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2865500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2865500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4327000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4327000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7192500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7192500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7192500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53064.814815                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53419.753086                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53277.777778                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53277.777778                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               162.297266                       # Cycle average of tags in use
@@ -215,31 +257,67 @@ system.cpu.l2cache.total_refs                       3                       # To
 system.cpu.l2cache.sampled_refs                   342                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.008772                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           162.297266                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.004953                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     3                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 342                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                81                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  423                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 423                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      17918500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      4230500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       22149000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      22149000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               345                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              81                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                426                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               426                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.991304                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.992958                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.992958                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52393.274854                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52228.395062                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52361.702128                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52361.702128                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    136.185515                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     26.111751                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004156                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000797                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004953                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          289                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          342                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           81                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           81                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          289                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           423                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          289                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          423                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15132500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2786000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     17918500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4230500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4230500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15132500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7016500                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     22149000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15132500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7016500                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22149000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          291                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          345                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           81                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           81                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          291                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          135                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          426                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          291                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          135                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          426                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993127                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993127                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993127                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52361.591696                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52228.395062                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52361.591696                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52361.940299                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52361.591696                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52361.940299                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -248,30 +326,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            342                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           81                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             423                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            423                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     13747000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      3255500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     17002500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     17002500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.991304                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.992958                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.992958                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40195.906433                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40191.358025                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 40195.035461                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 40195.035461                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          289                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          342                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           81                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           81                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          289                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          423                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          289                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          423                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11603500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2143500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13747000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3255500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3255500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11603500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5399000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17002500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11603500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5399000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17002500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993127                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40443.396226                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40191.358025                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40291.044776                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40150.519031                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40291.044776                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8aa4dc70795ce27573e977a79fd14938f885a70e..328fede16308e8f323eee532ba70bfdbcb89fc08 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
index 9cbff76e87f569535086b9bec54556e4d2a3d5e0..51b7334cc9c71095bf433704741804ca6af321a2 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:11
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:13
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 2701000 because target called exit()
index 57eaeacb053bdbede28e6c268a8add6f80c77986..12998e98f72cb98faf66b17f569cf0d9b8cf1014 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000003                       # Nu
 sim_ticks                                     2701000                       # Number of ticks simulated
 final_tick                                    2701000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 117056                       # Simulator instruction rate (inst/s)
-host_tick_rate                               59184907                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 203964                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 963329                       # Simulator instruction rate (inst/s)
+host_op_rate                                   960313                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              484321069                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 201636                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  21532                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     5065                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                             5403                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5340                       # Number of instructions executed
+system.cpu.committedInsts                        5340                       # Number of instructions committed
+system.cpu.committedOps                          5340                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         146                       # number of times a function call or return occured
index e13b78d74106d88d27b4ca31d19916ed6e3f4538..bca11e4c0f7133a387412ad4dc22a4ee4c621d77 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -51,6 +61,9 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -131,6 +144,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
index 8b55b99bfc2a4f5baeb06b62f25cbf0d89e8d196..f70d252d3673c2c6a25f8dbfa9021309a49f7b31 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:20
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:24
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing-ruby
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 253364 because target called exit()
index 5fbe4680b70d6b7dd6d0d4c7962209e5fa82fe8e..a13bd41616e6d9e9aa9afecb0c657765072cbd4c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000253                       # Nu
 sim_ticks                                      253364                       # Number of ticks simulated
 final_tick                                     253364                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  57666                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2735530                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 224736                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                  70723                       # Simulator instruction rate (inst/s)
+host_op_rate                                    70707                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                3354080                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 222404                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26135                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  21532                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     5065                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                           253364                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5340                       # Number of instructions executed
+system.cpu.committedInsts                        5340                       # Number of instructions committed
+system.cpu.committedOps                          5340                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         146                       # number of times a function call or return occured
index 31f964ca0a26f5434ca6986ac000aa4d3d5ad0ad..a618274661f5276104733dc1f29ac40497f887b4 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index a3d57b80d1c1850e24316b0f398336d9d7e3f0c7..5f1c3c546085249c97688cf618f2720d0660eb8d 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:14
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:23
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/00.hello/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello World!Exiting @ tick 28206000 because target called exit()
index 0e1d1294b259c9023f672bdc270923ce3053bdf4..e8bbbf4c9ec1f9a6e82b764154f8ba43a5d7a289 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000028                       # Nu
 sim_ticks                                    28206000                       # Number of ticks simulated
 final_tick                                   28206000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 103151                       # Simulator instruction rate (inst/s)
-host_tick_rate                              544654705                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212680                       # Number of bytes of host memory used
-host_seconds                                     0.05                       # Real time elapsed on the host
+host_inst_rate                                 534426                       # Simulator instruction rate (inst/s)
+host_op_rate                                   533460                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2812998715                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210748                       # Number of bytes of host memory used
+host_seconds                                     0.01                       # Real time elapsed on the host
 sim_insts                                        5340                       # Number of instructions simulated
+sim_ops                                          5340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       24896                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  16320                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                            56412                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             5340                       # Number of instructions executed
+system.cpu.committedInsts                        5340                       # Number of instructions committed
+system.cpu.committedOps                          5340                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  4517                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         146                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu.icache.total_refs                     5127                       # To
 system.cpu.icache.sampled_refs                    257                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  19.949416                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            116.975932                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.057117                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   5127                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    5127                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   5127                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  257                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   257                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  257                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       14308000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        14308000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       14308000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               5384                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                5384                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               5384                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.047734                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.047734                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.047734                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55673.151751                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55673.151751                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55673.151751                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     116.975932                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.057117                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.057117                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         5127                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            5127                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          5127                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             5127                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         5127                       # number of overall hits
+system.cpu.icache.overall_hits::total            5127                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          257                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           257                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          257                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            257                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          257                       # number of overall misses
+system.cpu.icache.overall_misses::total           257                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     14308000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     14308000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     14308000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     14308000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     14308000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     14308000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         5384                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         5384                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         5384                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         5384                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         5384                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         5384                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.047734                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.047734                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.047734                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55673.151751                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55673.151751                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             257                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              257                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             257                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     13537000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     13537000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     13537000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.047734                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.047734                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.047734                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52673.151751                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52673.151751                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          257                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          257                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          257                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          257                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          257                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          257                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     13537000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     13537000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     13537000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     13537000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     13537000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     13537000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.047734                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52673.151751                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 82.065697                       # Cycle average of tags in use
@@ -101,32 +115,49 @@ system.cpu.dcache.total_refs                     1254                       # To
 system.cpu.dcache.sampled_refs                    135                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                   9.288889                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             82.065697                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020036                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                    662                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   592                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1254                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1254                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   54                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  81                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   135                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  135                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        2982000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       4536000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         7518000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        7518000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses                716                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               673                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                1389                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               1389                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.075419                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.120357                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.097192                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.097192                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 55222.222222                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 55688.888889                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 55688.888889                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      82.065697                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020036                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020036                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data          662                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total             662                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          592                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            592                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1254                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1254                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1254                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1254                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           54                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            54                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           81                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           81                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          135                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            135                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          135                       # number of overall misses
+system.cpu.dcache.overall_misses::total           135                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      2982000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      2982000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4536000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4536000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7518000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7518000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7518000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7518000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data          716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total          716                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          673                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          673                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         1389                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1389                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1389                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1389                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.075419                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.120357                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.097192                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.097192                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55222.222222                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 55688.888889                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -135,30 +166,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              54                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             81                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              135                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             135                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2820000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      4293000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7113000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7113000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.075419                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.120357                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.097192                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.097192                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 52222.222222                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 52688.888889                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           54                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           54                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           81                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           81                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          135                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          135                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          135                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2820000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2820000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4293000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4293000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7113000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7113000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7113000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7113000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.075419                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.120357                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.097192                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52222.222222                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52688.888889                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52688.888889                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               142.102892                       # Cycle average of tags in use
@@ -166,31 +197,67 @@ system.cpu.l2cache.total_refs                       3                       # To
 system.cpu.l2cache.sampled_refs                   308                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.009740                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           142.102892                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.004337                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     3                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      3                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     3                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 308                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                81                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  389                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 389                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      16016000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      4212000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       20228000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      20228000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               311                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              81                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                392                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               392                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.990354                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.992347                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.992347                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    116.450335                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     25.652557                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003554                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000783                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004337                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              3                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               3                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.data            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              3                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          255                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          308                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           81                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           81                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          255                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           389                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          255                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          389                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     13260000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2756000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     16016000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4212000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4212000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     13260000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6968000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     20228000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     13260000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6968000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     20228000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          257                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           54                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          311                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           81                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           81                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          257                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          135                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          392                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          257                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          135                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          392                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992218                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data     0.981481                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992218                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data     0.992593                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992218                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data     0.992593                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -199,30 +266,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            308                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           81                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             389                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            389                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12320000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      3240000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     15560000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     15560000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.990354                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.992347                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.992347                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          255                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          308                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           81                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           81                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          255                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          389                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          255                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          389                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12320000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3240000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10200000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     15560000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10200000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     15560000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.981481                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992218                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.992593                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 8f8ece24e409bb3f2741540c66acea1a466d6b77..7b5ea1d5912f8dbea28d109fa0251350e9cfca92 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -89,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -126,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -149,7 +152,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.fuPool]
 type=FUPool
@@ -425,20 +435,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -446,9 +449,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -461,25 +480,18 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -490,7 +502,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -503,7 +515,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -522,7 +534,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index b49f2b57222c223af3462736949aac38f0eef606..ac1cd3610b1b1109cccc6b223b261cf1d68cce78 100755 (executable)
@@ -1,12 +1,10 @@
-Redirecting stdout to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simout
-Redirecting stderr to build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 28 2012 12:11:40
-gem5 started Jan 28 2012 12:11:57
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/o3-timing
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:05
+gem5 executing on zizzer
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 8477728c88558a11a2efb480ac1fb5c8a63453d1..658a056fbee6b77ac0693cb3abc1ba7ab1553198 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000012                       # Nu
 sim_ticks                                    11989500                       # Number of ticks simulated
 final_tick                                   11989500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                   1330                       # Simulator instruction rate (inst/s)
-host_tick_rate                                1625690                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 239860                       # Number of bytes of host memory used
-host_seconds                                     7.38                       # Real time elapsed on the host
-sim_insts                                        9809                       # Number of instructions simulated
+host_inst_rate                                  61798                       # Simulator instruction rate (inst/s)
+host_op_rate                                   111900                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              136747555                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 218292                       # Number of bytes of host memory used
+host_seconds                                     0.09                       # Real time elapsed on the host
+sim_insts                                        5416                       # Number of instructions simulated
+sim_ops                                          9809                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       28288                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  18944                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -235,7 +237,8 @@ system.cpu.iew.wb_penalized                         0                       # nu
 system.cpu.iew.wb_rate                       0.651043                       # insts written-back per cycle
 system.cpu.iew.wb_fanout                     0.677483                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitCommittedInsts           9809                       # The number of committed instructions
+system.cpu.commit.commitCommittedInsts           5416                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps             9809                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts           10533                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              13                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               495                       # The number of times a branch was mispredicted
@@ -256,7 +259,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        14495                       # Number of insts commited each cycle
-system.cpu.commit.count                          9809                       # Number of instructions committed
+system.cpu.commit.committedInsts                 5416                       # Number of instructions committed
+system.cpu.commit.committedOps                   9809                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           1990                       # Number of memory references committed
 system.cpu.commit.loads                          1056                       # Number of loads committed
@@ -271,12 +275,13 @@ system.cpu.rob.rob_reads                        34653                       # Th
 system.cpu.rob.rob_writes                       42403                       # The number of ROB writes
 system.cpu.timesIdled                             150                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                            7798                       # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts                        9809                       # Number of Instructions Simulated
-system.cpu.committedInsts_total                  9809                       # Number of Instructions Simulated
-system.cpu.cpi                               2.444694                       # CPI: Cycles Per Instruction
-system.cpu.cpi_total                         2.444694                       # CPI: Total CPI of All Threads
-system.cpu.ipc                               0.409049                       # IPC: Instructions Per Cycle
-system.cpu.ipc_total                         0.409049                       # IPC: Total IPC of All Threads
+system.cpu.committedInsts                        5416                       # Number of Instructions Simulated
+system.cpu.committedOps                          9809                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total                  5416                       # Number of Instructions Simulated
+system.cpu.cpi                               4.427622                       # CPI: Cycles Per Instruction
+system.cpu.cpi_total                         4.427622                       # CPI: Total CPI of All Threads
+system.cpu.ipc                               0.225855                       # IPC: Instructions Per Cycle
+system.cpu.ipc_total                         0.225855                       # IPC: Total IPC of All Threads
 system.cpu.int_regfile_reads                    23430                       # number of integer regfile reads
 system.cpu.int_regfile_writes                   14518                       # number of integer regfile writes
 system.cpu.fp_regfile_reads                         4                       # number of floating regfile reads
@@ -287,26 +292,39 @@ system.cpu.icache.total_refs                     1498                       # To
 system.cpu.icache.sampled_refs                    298                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   5.026846                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            140.870525                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.068784                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   1498                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    1498                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   1498                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  368                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   368                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  368                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       13394000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        13394000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       13394000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               1866                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                1866                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               1866                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.197213                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.197213                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.197213                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 36396.739130                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 36396.739130                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 36396.739130                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     140.870525                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.068784                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.068784                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         1498                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            1498                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          1498                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             1498                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         1498                       # number of overall hits
+system.cpu.icache.overall_hits::total            1498                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          368                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           368                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          368                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            368                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          368                       # number of overall misses
+system.cpu.icache.overall_misses::total           368                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     13394000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     13394000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     13394000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     13394000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     13394000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     13394000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         1866                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         1866                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         1866                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         1866                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         1866                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         1866                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.197213                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.197213                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.197213                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36396.739130                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 36396.739130                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 36396.739130                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -315,27 +333,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                70                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 70                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                70                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             298                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              298                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             298                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     10471500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     10471500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     10471500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.159700                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.159700                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.159700                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35139.261745                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35139.261745                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35139.261745                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           70                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           70                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           70                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           70                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           70                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           70                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          298                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          298                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          298                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          298                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          298                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          298                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     10471500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     10471500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     10471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     10471500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     10471500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     10471500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.159700                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.159700                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.159700                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35139.261745                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35139.261745                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35139.261745                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 83.526549                       # Cycle average of tags in use
@@ -343,32 +364,49 @@ system.cpu.dcache.total_refs                     2275                       # To
 system.cpu.dcache.sampled_refs                    145                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  15.689655                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             83.526549                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.020392                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1417                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   858                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    2275                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   2275                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  111                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  76                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   187                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  187                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3859500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       2916500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         6776000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        6776000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1528                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                2462                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               2462                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.072644                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.081370                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.075955                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.075955                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 34770.270270                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        38375                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 36235.294118                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 36235.294118                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      83.526549                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.020392                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.020392                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1417                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1417                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          858                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            858                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          2275                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             2275                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         2275                       # number of overall hits
+system.cpu.dcache.overall_hits::total            2275                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          111                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           111                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           76                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           76                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          187                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            187                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          187                       # number of overall misses
+system.cpu.dcache.overall_misses::total           187                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3859500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3859500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      2916500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      2916500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      6776000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      6776000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      6776000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      6776000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1528                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1528                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         2462                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         2462                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         2462                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         2462                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.072644                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.081370                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.075955                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.075955                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 34770.270270                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        38375                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 36235.294118                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 36235.294118                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -377,31 +415,36 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                41                       # number of ReadReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                 41                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                41                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              70                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             76                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2463000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2688500                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      5151500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      5151500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.045812                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.081370                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.059301                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.059301                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35185.714286                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        35375                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35284.246575                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35284.246575                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           41                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           41                       # number of ReadReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data           41                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total           41                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data           41                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total           41                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           70                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           70                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           76                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           76                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2463000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2463000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2688500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2688500                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5151500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5151500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5151500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5151500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.045812                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.081370                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.059301                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.059301                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35185.714286                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        35375                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35284.246575                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35284.246575                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               173.809724                       # Cycle average of tags in use
@@ -409,31 +452,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   365                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005479                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           173.809724                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005304                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 366                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                76                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  442                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 442                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      12541000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2603000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       15144000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      15144000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               368                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              76                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                444                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               444                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.994565                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995495                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995495                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34265.027322                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        34250                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34262.443439                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34262.443439                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    140.468506                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     33.341218                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004287                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001017                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005304                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          296                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           70                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          366                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           76                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           76                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          296                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          146                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           442                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          296                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          146                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          442                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     10158000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2383000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     12541000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2603000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2603000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     10158000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      4986000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     15144000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     10158000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      4986000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     15144000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          298                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           70                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          368                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           76                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           76                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          298                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          444                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          298                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          444                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993289                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993289                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993289                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34317.567568                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34042.857143                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        34250                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34317.567568                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34150.684932                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34317.567568                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34150.684932                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -442,30 +518,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            366                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           76                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             442                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            442                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11369000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2368500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     13737500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     13737500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994565                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995495                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995495                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31062.841530                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31164.473684                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31080.316742                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31080.316742                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          296                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           70                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           76                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           76                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          296                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          442                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          296                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          442                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9202000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2167000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11369000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2368500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2368500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9202000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4535500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     13737500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9202000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4535500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     13737500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993289                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993289                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993289                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31087.837838                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 30957.142857                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31164.473684                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31087.837838                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31065.068493                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31087.837838                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31065.068493                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index e5a1ce348fda18d53519777204f7ed3d8ac49564..8e464f4fcbf6c2b101f49e92deb0594801853571 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -52,11 +62,34 @@ icache_port=system.membus.port[2]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[5]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[7]
+pio=system.membus.port[6]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.membus.port[4]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -88,7 +121,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port
+port=system.system_port system.physmem.port[0] system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index de652c174708f58af46cfa68944867a0c407dce8..51c6cbf482d8328493801a6144fdb4cfb5c86d62 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:38
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:16
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-atomic
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index e2f539833d0fbe0021b568e78d3d65de8111b136..d15c91451b5d61b8e034ac71cbfadf5c4a5b36f5 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000006                       # Nu
 sim_ticks                                     5651000                       # Number of ticks simulated
 final_tick                                    5651000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 225004                       # Simulator instruction rate (inst/s)
-host_tick_rate                              129531520                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 202604                       # Number of bytes of host memory used
-host_seconds                                     0.04                       # Real time elapsed on the host
-sim_insts                                        9810                       # Number of instructions simulated
+host_inst_rate                                 364793                       # Simulator instruction rate (inst/s)
+host_op_rate                                   659825                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              379660541                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 207748                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+sim_insts                                        5417                       # Number of instructions simulated
+sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  55280                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     7110                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                            11303                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             9810                       # Number of instructions executed
+system.cpu.committedInsts                        5417                       # Number of instructions committed
+system.cpu.committedOps                          9810                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index 3ef5774b9ae1943a402f085f4b36f551436d4a7e..95be41a118609360829b207ecc7f862d133a1dad 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000
 time_sync_spin_threshold=100000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000
 [system]
 type=System
 children=cpu dir_cntrl0 l1_cntrl0 physmem ruby sys_port_proxy
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.sys_port_proxy.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=1
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -49,11 +59,34 @@ icache_port=system.l1_cntrl0.sequencer.port[0]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.l1_cntrl0.sequencer.port[3]
+
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1
+pio_addr=2305843009213693952
+pio_latency=1
+system=system
+int_port=system.l1_cntrl0.sequencer.port[5]
+pio=system.l1_cntrl0.sequencer.port[4]
 
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.l1_cntrl0.sequencer.port[2]
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -131,6 +164,7 @@ issue_latency=2
 number_of_TBEs=256
 recycle_latency=10
 ruby_system=system.ruby
+send_evictions=false
 sequencer=system.l1_cntrl0.sequencer
 transitions_per_cycle=32
 version=0
@@ -157,7 +191,7 @@ using_network_tester=false
 using_ruby_tester=false
 version=0
 physMemPort=system.physmem.port[0]
-port=system.cpu.icache_port system.cpu.dcache_port
+port=system.cpu.icache_port system.cpu.dcache_port system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index 9c1cf6357ec85c0b9db12518e5df0b042641dd59..f8a22f9cadf30961e0855efab4c433e996c4db3d 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:43
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:37
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing-ruby
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index 49089d2272512b72a42f52aca70990a40e2d4340..31a5db86eb77fafc1f34cdb9a127f66fec570ee4 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000276                       # Nu
 sim_ticks                                      276484                       # Number of ticks simulated
 final_tick                                     276484                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  88128                       # Simulator instruction rate (inst/s)
-host_tick_rate                                2483404                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 223444                       # Number of bytes of host memory used
+host_inst_rate                                  47191                       # Simulator instruction rate (inst/s)
+host_op_rate                                    85448                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                2407911                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 228676                       # Number of bytes of host memory used
 host_seconds                                     0.11                       # Real time elapsed on the host
-sim_insts                                        9810                       # Number of instructions simulated
+sim_insts                                        5417                       # Number of instructions simulated
+sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       62348                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  55280                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     7110                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                           276484                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             9810                       # Number of instructions executed
+system.cpu.committedInsts                        5417                       # Number of instructions committed
+system.cpu.committedOps                          9810                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
index 36b722b34847be54e804b4acdb8b3f4b0afec60c..7bd202ff4036179b1c6904902dae5060e144bfa9 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -81,7 +84,14 @@ mem_side=system.cpu.toL2Bus.port[1]
 
 [system.cpu.dtb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.dtb.walker
+
+[system.cpu.dtb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[3]
 
 [system.cpu.icache]
 type=BaseCache
@@ -94,20 +104,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,9 +118,25 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=X86LocalApic
+int_latency=1000
+pio_addr=2305843009213693952
+pio_latency=1000
+system=system
+int_port=system.membus.port[4]
+pio=system.membus.port[3]
+
 [system.cpu.itb]
 type=X86TLB
+children=walker
 size=64
+walker=system.cpu.itb.walker
+
+[system.cpu.itb.walker]
+type=X86PagetableWalker
+system=system
+port=system.cpu.toL2Bus.port[2]
 
 [system.cpu.l2cache]
 type=BaseCache
@@ -130,25 +149,18 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
 write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
+cpu_side=system.cpu.toL2Bus.port[4]
 mem_side=system.membus.port[2]
 
 [system.cpu.toL2Bus]
@@ -159,7 +171,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port system.cpu.l2cache.cpu_side
 
 [system.cpu.tracer]
 type=ExeTracer
@@ -191,7 +203,7 @@ clock=1000
 header_cycles=1
 use_default_range=false
 width=64
-port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side
+port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side system.cpu.interrupts.pio system.cpu.interrupts.int_port
 
 [system.physmem]
 type=PhysicalMemory
index 074c5468cb3d5259b4eacd7c569d29122d34f624..89203c6bcdd0ab94f39c048b5e9bbe113bbd61ad 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:08:34
-gem5 started Jan 23 2012 04:24:38
+gem5 compiled Feb 11 2012 13:08:53
+gem5 started Feb 11 2012 14:04:26
 gem5 executing on zizzer
-command line: build/X86_SE/gem5.opt -d build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing -re tests/run.py build/X86_SE/tests/opt/quick/00.hello/x86/linux/simple-timing
+command line: build/X86/gem5.fast -d build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/fast/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
index dcf7af574da09a4063b181a8b8caaa1f04a1f997..c2e4355d3cda72f95381dcf0b85fc24488f61d4a 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000029                       # Nu
 sim_ticks                                    28768000                       # Number of ticks simulated
 final_tick                                   28768000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 320748                       # Simulator instruction rate (inst/s)
-host_tick_rate                              940055576                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 211332                       # Number of bytes of host memory used
-host_seconds                                     0.03                       # Real time elapsed on the host
-sim_insts                                        9810                       # Number of instructions simulated
+host_inst_rate                                 265683                       # Simulator instruction rate (inst/s)
+host_op_rate                                   480724                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1408532008                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 216996                       # Number of bytes of host memory used
+host_seconds                                     0.02                       # Real time elapsed on the host
+sim_insts                                        5417                       # Number of instructions simulated
+sim_ops                                          9810                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       23104                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  14528                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls                   11                       # Nu
 system.cpu.numCycles                            57536                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                             9810                       # Number of instructions executed
+system.cpu.committedInsts                        5417                       # Number of instructions committed
+system.cpu.committedOps                          9810                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                  9715                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                           0                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu.icache.total_refs                     6683                       # To
 system.cpu.icache.sampled_refs                    228                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  29.311404                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            105.363985                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.051447                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   6683                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    6683                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   6683                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  228                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   228                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  228                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       12726000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        12726000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       12726000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               6911                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                6911                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               6911                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.032991                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.032991                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.032991                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 55815.789474                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 55815.789474                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 55815.789474                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     105.363985                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.051447                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.051447                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         6683                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            6683                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          6683                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             6683                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         6683                       # number of overall hits
+system.cpu.icache.overall_hits::total            6683                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          228                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           228                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          228                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            228                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          228                       # number of overall misses
+system.cpu.icache.overall_misses::total           228                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     12726000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     12726000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     12726000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     12726000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     12726000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     12726000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         6911                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         6911                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         6911                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         6911                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         6911                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         6911                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.032991                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.032991                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.032991                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55815.789474                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 55815.789474                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             228                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              228                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             228                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     12042000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     12042000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     12042000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.032991                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.032991                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.032991                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52815.789474                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52815.789474                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52815.789474                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          228                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          228                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          228                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          228                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          228                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          228                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     12042000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     12042000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     12042000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     12042000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     12042000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     12042000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.032991                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52815.789474                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 80.668870                       # Cycle average of tags in use
@@ -101,32 +115,49 @@ system.cpu.dcache.total_refs                     1856                       # To
 system.cpu.dcache.sampled_refs                    134                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  13.850746                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             80.668870                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.019695                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   1001                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                   855                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    1856                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   1856                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   55                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  79                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   134                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  134                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3080000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       4424000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         7504000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        7504000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               1056                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses               934                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                1990                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               1990                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.052083                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.084582                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.067337                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.067337                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      80.668870                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.019695                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.019695                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         1001                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            1001                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data          855                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total            855                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          1856                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             1856                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         1856                       # number of overall hits
+system.cpu.dcache.overall_hits::total            1856                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            55                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           79                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           79                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            134                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          134                       # number of overall misses
+system.cpu.dcache.overall_misses::total           134                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3080000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3080000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4424000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4424000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7504000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7504000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7504000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7504000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         1056                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         1056                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data          934                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total          934                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         1990                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         1990                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         1990                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         1990                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.052083                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.084582                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.067337                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.067337                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -135,30 +166,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              55                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             79                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              134                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             134                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2915000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      4187000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7102000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7102000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.052083                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.084582                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.067337                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.067337                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           55                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           79                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           79                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          134                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          134                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2915000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4187000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4187000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7102000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7102000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7102000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7102000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.052083                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084582                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.067337                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.067337                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               133.809342                       # Cycle average of tags in use
@@ -166,31 +197,64 @@ system.cpu.l2cache.total_refs                       1                       # To
 system.cpu.l2cache.sampled_refs                   282                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.003546                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           133.809342                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.004084                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     1                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      1                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     1                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 282                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                79                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  361                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 361                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      14664000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      4108000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       18772000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      18772000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               283                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              79                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                362                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               362                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.996466                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.997238                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.997238                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    105.370729                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     28.438613                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.003216                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000868                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.004084                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            1                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              1                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            1                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               1                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            1                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              1                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          227                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           55                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          282                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           79                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           79                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          227                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          134                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           361                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          227                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          134                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          361                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11804000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2860000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     14664000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4108000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4108000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11804000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      6968000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     18772000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11804000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      6968000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     18772000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          228                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           55                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          283                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           79                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           79                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          228                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          134                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          362                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          228                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          134                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          362                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.995614                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.995614                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.995614                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -199,30 +263,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            282                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           79                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             361                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            361                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     11280000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      3160000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     14440000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     14440000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.996466                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.997238                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.997238                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          227                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           55                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          282                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           79                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           79                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          227                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          134                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          361                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          227                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          134                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          361                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst      9080000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2200000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     11280000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3160000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3160000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst      9080000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5360000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14440000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst      9080000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5360000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14440000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.995614                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 5ef0030d0f9377df1170dbba046bdf235f8ba0f7..14cc5821d04e6fbee235b8950d18f7b1c0db5a90 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload0 workload1
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload0 workload1
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=2
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=AlphaInterrupts
+
 [system.cpu.itb]
 type=AlphaTLB
 size=48
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index ab4ed6a092a3f5dd881c649e7d08553c094eb9f5..4edc89b33234e3e749fd9208f695c9effbca9de9 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:27
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:24
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA_SE/tests/opt/quick/01.hello-2T-smt/alpha/linux/o3-timing
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/fast/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
index 6ec84dd27dc37cb9693c452a18dd84bc8f59d866..292756fa3b89002396b0920b805ea23dcaaf45cd 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000013                       # Nu
 sim_ticks                                    13202000                       # Number of ticks simulated
 final_tick                                   13202000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  76140                       # Simulator instruction rate (inst/s)
-host_tick_rate                               78688554                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 208616                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_inst_rate                                  91406                       # Simulator instruction rate (inst/s)
+host_op_rate                                    91394                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               94452628                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210624                       # Number of bytes of host memory used
+host_seconds                                     0.14                       # Real time elapsed on the host
 sim_insts                                       12773                       # Number of instructions simulated
+sim_ops                                         12773                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       62144                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  39936                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -385,6 +387,7 @@ system.cpu.iew.wb_penalized_rate::0                 0                       # fr
 system.cpu.iew.wb_penalized_rate::1                 0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.iew.wb_penalized_rate::total             0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts          12807                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps            12807                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            9596                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls              34                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               953                       # The number of times a branch was mispredicted
@@ -405,9 +408,12 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        20176                       # Number of insts commited each cycle
-system.cpu.commit.count::0                       6403                       # Number of instructions committed
-system.cpu.commit.count::1                       6404                       # Number of instructions committed
-system.cpu.commit.count::total                  12807                       # Number of instructions committed
+system.cpu.commit.committedInsts::0              6403                       # Number of instructions committed
+system.cpu.commit.committedInsts::1              6404                       # Number of instructions committed
+system.cpu.commit.committedInsts::total         12807                       # Number of instructions committed
+system.cpu.commit.committedOps::0                6403                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::1                6404                       # Number of ops (including micro ops) committed
+system.cpu.commit.committedOps::total           12807                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count::0                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::1                      0                       # Number of s/w prefetches committed
 system.cpu.commit.swp_count::total                  0                       # Number of s/w prefetches committed
@@ -442,6 +448,8 @@ system.cpu.timesIdled                             233                       # Nu
 system.cpu.idleCycles                            6204                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts::0                     6386                       # Number of Instructions Simulated
 system.cpu.committedInsts::1                     6387                       # Number of Instructions Simulated
+system.cpu.committedOps::0                       6386                       # Number of Ops (including micro ops) Simulated
+system.cpu.committedOps::1                       6387                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 12773                       # Number of Instructions Simulated
 system.cpu.cpi::0                            4.134826                       # CPI: Cycles Per Instruction
 system.cpu.cpi::1                            4.134179                       # CPI: Cycles Per Instruction
@@ -463,36 +471,39 @@ system.cpu.icache.total_refs                     3236                       # To
 system.cpu.icache.sampled_refs                    626                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                   5.169329                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            314.165301                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.153401                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   3236                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    3236                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   3236                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  855                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   855                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  855                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::0     30710500                       # number of ReadReq miss cycles
+system.cpu.icache.occ_blocks::cpu.inst     314.165301                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.153401                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.153401                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         3236                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            3236                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          3236                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             3236                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         3236                       # number of overall hits
+system.cpu.icache.overall_hits::total            3236                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          855                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           855                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          855                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            855                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          855                       # number of overall misses
+system.cpu.icache.overall_misses::total           855                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     30710500                       # number of ReadReq miss cycles
 system.cpu.icache.ReadReq_miss_latency::total     30710500                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency::0     30710500                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_latency::1            0                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     30710500                       # number of demand (read+write) miss cycles
 system.cpu.icache.demand_miss_latency::total     30710500                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency::0     30710500                       # number of overall miss cycles
-system.cpu.icache.overall_miss_latency::1            0                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     30710500                       # number of overall miss cycles
 system.cpu.icache.overall_miss_latency::total     30710500                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               4091                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                4091                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               4091                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.208995                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.208995                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.208995                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::0 35918.713450                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 35918.713450                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::0 35918.713450                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 35918.713450                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::0 35918.713450                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 35918.713450                       # average overall miss latency
+system.cpu.icache.ReadReq_accesses::cpu.inst         4091                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         4091                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         4091                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         4091                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         4091                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         4091                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.208995                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.208995                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.208995                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35918.713450                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 35918.713450                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 35918.713450                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -501,63 +512,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks::0                     0                       # number of writebacks
-system.cpu.icache.writebacks::1                     0                       # number of writebacks
-system.cpu.icache.writebacks::total                 0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits::0            229                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          229                       # number of ReadReq MSHR hits
 system.cpu.icache.ReadReq_mshr_hits::total          229                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits::0             229                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_hits::1               0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          229                       # number of demand (read+write) MSHR hits
 system.cpu.icache.demand_mshr_hits::total          229                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits::0            229                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_hits::1              0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          229                       # number of overall MSHR hits
 system.cpu.icache.overall_mshr_hits::total          229                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::0          626                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          626                       # number of ReadReq MSHR misses
 system.cpu.icache.ReadReq_mshr_misses::total          626                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::0           626                       # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::1             0                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          626                       # number of demand (read+write) MSHR misses
 system.cpu.icache.demand_mshr_misses::total          626                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::0          626                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::1            0                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          626                       # number of overall MSHR misses
 system.cpu.icache.overall_mshr_misses::total          626                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses::0            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::1            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.overall_mshr_uncacheable_misses::total            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency::0     22267000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     22267000                       # number of ReadReq MSHR miss cycles
 system.cpu.icache.ReadReq_mshr_miss_latency::total     22267000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::0     22267000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::1            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     22267000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.icache.demand_mshr_miss_latency::total     22267000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::0     22267000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::1            0                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     22267000                       # number of overall MSHR miss cycles
 system.cpu.icache.overall_mshr_miss_latency::total     22267000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::0            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::1            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_latency::total            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::0     0.153019                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total     0.153019                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::0     0.153019                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total     0.153019                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::0     0.153019                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total     0.153019                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency::0 35570.287540                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::0 35570.287540                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::0 35570.287540                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::0     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::1     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency::total     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events::0                0                       # number of times MSHR cap was activated
-system.cpu.icache.mshr_cap_events::1                0                       # number of times MSHR cap was activated
-system.cpu.icache.mshr_cap_events::total            0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full::0            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.soft_prefetch_mshr_full::1            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.soft_prefetch_mshr_full::total            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.153019                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.153019                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.153019                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35570.287540                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35570.287540                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35570.287540                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements::0                   0                       # number of replacements
 system.cpu.dcache.replacements::1                   0                       # number of replacements
@@ -567,44 +545,49 @@ system.cpu.dcache.total_refs                     4323                       # To
 system.cpu.dcache.sampled_refs                    347                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  12.458213                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            216.133399                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.052767                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   3303                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                  1020                       # number of WriteReq hits
-system.cpu.dcache.demand_hits                    4323                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   4323                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  308                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 710                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                  1018                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                 1018                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::0     11179500                       # number of ReadReq miss cycles
+system.cpu.dcache.occ_blocks::cpu.data     216.133399                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.052767                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.052767                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         3303                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            3303                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1020                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1020                       # number of WriteReq hits
+system.cpu.dcache.demand_hits::cpu.data          4323                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             4323                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         4323                       # number of overall hits
+system.cpu.dcache.overall_hits::total            4323                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          308                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           308                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          710                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          710                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data         1018                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total           1018                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data         1018                       # number of overall misses
+system.cpu.dcache.overall_misses::total          1018                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data     11179500                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total     11179500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::0     24106500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     24106500                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total     24106500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::0     35286000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::1            0                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     35286000                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total     35286000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::0     35286000                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::1            0                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     35286000                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total     35286000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               3611                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses              1730                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                5341                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               5341                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.085295                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.410405                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.190601                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.190601                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::0 36297.077922                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_miss_latency::total 36297.077922                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::0 33952.816901                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::total 33952.816901                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::0 34662.082515                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dcache.demand_avg_miss_latency::total 34662.082515                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::0 34662.082515                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::total 34662.082515                       # average overall miss latency
+system.cpu.dcache.ReadReq_accesses::cpu.data         3611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         3611                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data         1730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total         1730                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         5341                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         5341                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         5341                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         5341                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.085295                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.410405                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.190601                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.190601                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36297.077922                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33952.816901                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 34662.082515                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 34662.082515                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -613,72 +596,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks::0                     0                       # number of writebacks
-system.cpu.dcache.writebacks::1                     0                       # number of writebacks
-system.cpu.dcache.writebacks::total                 0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::0            107                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data          107                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total          107                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::          564                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          564                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total          564                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::0             671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_hits::1               0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          671                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total          671                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::0            671                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_hits::1              0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          671                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total          671                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::0          201                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data          201                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total          201                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::0          146                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data          146                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total          146                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::0           347                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.demand_mshr_misses::1             0                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          347                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total          347                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::0          347                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_misses::1            0                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          347                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total          347                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::0            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::1            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.overall_mshr_uncacheable_misses::total            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::0      7376000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      7376000                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total      7376000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::0      5298000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      5298000                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total      5298000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::0     12674000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::1            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data     12674000                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total     12674000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::0     12674000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::1            0                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data     12674000                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total     12674000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::0            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::1            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::total            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::0     0.055663                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.055663                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::0     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.084393                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::0     0.064969                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_miss_rate::total     0.064969                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::0     0.064969                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_miss_rate::total     0.064969                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::0 36696.517413                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::0 36287.671233                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::0 36524.495677                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::0 36524.495677                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::0     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::1     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events::0                0                       # number of times MSHR cap was activated
-system.cpu.dcache.mshr_cap_events::1                0                       # number of times MSHR cap was activated
-system.cpu.dcache.mshr_cap_events::total            0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full::0            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.soft_prefetch_mshr_full::1            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.soft_prefetch_mshr_full::total            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.055663                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.084393                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.064969                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.064969                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 36696.517413                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36287.671233                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36524.495677                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36524.495677                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements::0                  0                       # number of replacements
 system.cpu.l2cache.replacements::1                  0                       # number of replacements
@@ -688,43 +637,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   825                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.002424                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           435.235373                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.013282                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 825                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses               146                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  971                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 971                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency::0     28470000                       # number of ReadReq miss cycles
+system.cpu.l2cache.occ_blocks::cpu.inst    314.499531                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data    120.735842                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.009598                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.003685                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.013282                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          624                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data          201                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          825                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data          146                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total          146                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          624                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          347                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           971                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          624                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          347                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          971                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     21475000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      6995000                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::total     28470000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::0      5066000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      5066000                       # number of ReadExReq miss cycles
 system.cpu.l2cache.ReadExReq_miss_latency::total      5066000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency::0     33536000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::1            0                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     21475000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data     12061000                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::total     33536000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency::0     33536000                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::1            0                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     21475000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data     12061000                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::total     33536000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               827                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses             146                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                973                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               973                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.997582                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.997945                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.997945                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency::0 34509.090909                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::total 34509.090909                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::0 34698.630137                       # average ReadExReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34698.630137                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency::0 34537.590113                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.l2cache.demand_avg_miss_latency::total 34537.590113                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::0 34537.590113                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::1            0                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::total 34537.590113                       # average overall miss latency
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          626                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data          201                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          827                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data          146                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total          146                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          626                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          347                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          973                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          626                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          347                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          973                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.996805                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.996805                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.996805                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34415.064103                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34800.995025                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34698.630137                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34415.064103                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34757.925072                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34415.064103                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34757.925072                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs        21000                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                4                       # number of cycles access was blocked
@@ -733,68 +703,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs         5250
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks::0                    0                       # number of writebacks
-system.cpu.l2cache.writebacks::1                    0                       # number of writebacks
-system.cpu.l2cache.writebacks::total                0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits::0              0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::1              0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_hits::total            0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::0             0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::1             0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_hits::total            0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses::0          825                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          624                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data          201                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total          825                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::0          146                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          146                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total          146                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses::0          971                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::1            0                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          624                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          347                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total          971                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses::0          971                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::1            0                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          624                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          347                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total          971                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::0            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::1            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses::total            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency::0     25887000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     19514500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      6372500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total     25887000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::0      4614000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      4614000                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      4614000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::0     30501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::1            0                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     19514500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data     10986500                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total     30501000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::0     30501000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::1            0                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     19514500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data     10986500                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total     30501000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::0            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::1            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::total            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate::0     0.997582                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.997582                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::0            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::0     0.997945                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::1            0                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total     0.997945                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::0     0.997945                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::1            0                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total     0.997945                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::0 31378.181818                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::0 31602.739726                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::0 31411.946447                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::0 31411.946447                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::1     no_value                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total     no_value                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::0     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::1     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events::0               0                       # number of times MSHR cap was activated
-system.cpu.l2cache.mshr_cap_events::1               0                       # number of times MSHR cap was activated
-system.cpu.l2cache.mshr_cap_events::total            0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full::0            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.soft_prefetch_mshr_full::1            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.soft_prefetch_mshr_full::total            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.996805                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31273.237179                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31703.980100                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31602.739726                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31273.237179                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31661.383285                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31273.237179                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31661.383285                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 7db48bf0e7b1a5038cdaa41c1170fe285bfa53ea..a2e6b752334ad6d14d4c9e107288d464cf8753ac 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=InOrderCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 RASSize=16
@@ -45,6 +52,7 @@ div32RepeatRate=1
 div8Latency=1
 div8RepeatRate=1
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchBuffSize=4
@@ -57,6 +65,7 @@ globalCtrBits=2
 globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 localCtrBits=2
 localHistoryBits=11
@@ -72,6 +81,7 @@ multRepeatRate=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 stageTracing=false
 stageWidth=4
@@ -93,20 +103,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -129,20 +132,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -150,6 +146,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -165,20 +164,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 38fdee47370e3389c57f8ec7501bc18420771ef2..71793d455ea4b8130e472835f6b9c73e559b2a8d 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:21
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:34
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/inorder-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
index 7b0904682b856bbfa4f47a4d25af1634cee55cef..f7efdf641a8f7623f9325dcae039e0d0ae857f27 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000025                       # Nu
 sim_ticks                                    25058500                       # Number of ticks simulated
 final_tick                                   25058500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  55020                       # Simulator instruction rate (inst/s)
-host_tick_rate                               90849063                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212976                       # Number of bytes of host memory used
-host_seconds                                     0.28                       # Real time elapsed on the host
+host_inst_rate                                  93467                       # Simulator instruction rate (inst/s)
+host_op_rate                                    93457                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              154309649                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211048                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       27904                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  19072                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -36,9 +38,10 @@ system.cpu.comNops                                726                       # Nu
 system.cpu.comNonSpec                             222                       # Number of Non-Speculative instructions committed
 system.cpu.comInts                               7177                       # Number of Integer instructions committed
 system.cpu.comFloats                                0                       # Number of Floating Point instructions committed
-system.cpu.committedInsts                       15175                       # Number of Instructions Simulated (Per-Thread)
-system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions Simulated (Per-Thread)
-system.cpu.committedInsts_total                 15175                       # Number of Instructions Simulated (Total)
+system.cpu.committedInsts                       15175                       # Number of Instructions committed (Per-Thread)
+system.cpu.committedOps                         15175                       # Number of Ops committed (Per-Thread)
+system.cpu.smtCommittedInsts                        0                       # Number of SMT Instructions committed (Per-Thread)
+system.cpu.committedInsts_total                 15175                       # Number of Instructions committed (Total)
 system.cpu.cpi                               3.302669                       # CPI: Cycles Per Instruction (Per-Thread)
 system.cpu.smt_cpi                           no_value                       # CPI: Total SMT-CPI
 system.cpu.cpi_total                         3.302669                       # CPI: Total CPI of All Threads
@@ -92,26 +95,39 @@ system.cpu.icache.total_refs                     3085                       # To
 system.cpu.icache.sampled_refs                    299                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  10.317726                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            165.645515                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.080882                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   3085                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    3085                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   3085                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  366                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   366                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  366                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       20100000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        20100000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       20100000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               3451                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                3451                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               3451                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.106056                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.106056                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.106056                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 54918.032787                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 54918.032787                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 54918.032787                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     165.645515                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.080882                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.080882                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         3085                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            3085                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          3085                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             3085                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         3085                       # number of overall hits
+system.cpu.icache.overall_hits::total            3085                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          366                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           366                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          366                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            366                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          366                       # number of overall misses
+system.cpu.icache.overall_misses::total           366                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     20100000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     20100000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     20100000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     20100000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     20100000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     20100000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         3451                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         3451                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         3451                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         3451                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         3451                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         3451                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.106056                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.106056                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.106056                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54918.032787                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 54918.032787                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 54918.032787                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets        19500                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -120,27 +136,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets        19500                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits                65                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                 65                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                65                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             301                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              301                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             301                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     15872000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     15872000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     15872000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.087221                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.087221                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.087221                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 52730.897010                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 52730.897010                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 52730.897010                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst           65                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total           65                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst           65                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total           65                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst           65                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total           65                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          301                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          301                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          301                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          301                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          301                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          301                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     15872000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     15872000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     15872000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     15872000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     15872000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     15872000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.087221                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.087221                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.087221                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52730.897010                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52730.897010                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52730.897010                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 97.082868                       # Cycle average of tags in use
@@ -148,34 +167,53 @@ system.cpu.dcache.total_refs                     3316                       # To
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  24.028986                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             97.082868                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.023702                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   2168                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                  1142                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                    3310                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   3310                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   58                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 300                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   358                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  358                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3282500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      16398000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        19680500                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       19680500                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               2226                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                3668                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               3668                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.026056                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.208044                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.097601                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.097601                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 56594.827586                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        54660                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 54973.463687                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 54973.463687                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      97.082868                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023702                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023702                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         2168                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2168                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1142                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1142                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data          3310                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3310                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3310                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3310                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           58                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            58                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          300                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          300                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          358                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            358                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          358                       # number of overall misses
+system.cpu.dcache.overall_misses::total           358                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3282500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3282500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     16398000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     16398000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     19680500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     19680500                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     19680500                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     19680500                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         3668                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         3668                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         3668                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         3668                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.026056                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.208044                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.097601                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.097601                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56594.827586                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        54660                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 54973.463687                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 54973.463687                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets      2208000                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -184,32 +222,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets 50181.818182                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                 5                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              215                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                220                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               220                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             85                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2838000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      4545000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7383000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7383000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.023810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.037623                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53547.169811                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53470.588235                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53500                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data            5                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total            5                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          215                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          215                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          220                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          220                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          220                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          220                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2838000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2838000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4545000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4545000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7383000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7383000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7383000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7383000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023810                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53547.169811                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53470.588235                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53500                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               196.307447                       # Cycle average of tags in use
@@ -217,31 +261,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   350                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005714                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           196.307447                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005991                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 352                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                85                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  437                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 437                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      18310500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      4442500                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       22753000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      22753000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               354                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                439                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               439                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.994350                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995444                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995444                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 52018.465909                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 52264.705882                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 52066.361556                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 52066.361556                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    165.036640                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.270807                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005037                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000954                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005991                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          299                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          352                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          299                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           437                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          299                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          437                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     15533000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2777500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     18310500                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4442500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4442500                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     15533000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7220000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     22753000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     15533000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7220000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     22753000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          301                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          354                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          301                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          439                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          301                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          439                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993355                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993355                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993355                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51949.832776                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52405.660377                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52264.705882                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51949.832776                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52318.840580                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51949.832776                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52318.840580                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -250,30 +327,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            352                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             437                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            437                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     14048500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      3416000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     17464500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     17464500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994350                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995444                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995444                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 39910.511364                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40188.235294                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 39964.530892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 39964.530892                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          299                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          352                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          299                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          437                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          299                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          437                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11916000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2132500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     14048500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3416000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3416000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11916000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5548500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     17464500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11916000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5548500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     17464500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993355                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39852.842809                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40235.849057                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40188.235294                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39852.842809                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40206.521739                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39852.842809                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40206.521739                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 6652fe60b7319e40a84843ff11ce47580033f351..a7b62ffbfd54f06f9aaea28401cfaeecb7483f11 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb l2cache toL2Bus tracer workload
+children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -460,20 +460,13 @@ is_top_level=false
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index 14970f00ad6267ff6ef396e817acc6fa4474c0b1..2cf0bff32431155ce7d241456f6acef9fc5b0bb7 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:22
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:35
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/o3-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
index 3a1cfc4e9aad1763cc81546341d6ee64322ffc31..b636617605a916a6babe4b4b7420b50065a7d777 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000018                       # Nu
 sim_ticks                                    18114000                       # Number of ticks simulated
 final_tick                                   18114000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  74785                       # Simulator instruction rate (inst/s)
-host_tick_rate                               93746300                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 213808                       # Number of bytes of host memory used
-host_seconds                                     0.19                       # Real time elapsed on the host
+host_inst_rate                                 120891                       # Simulator instruction rate (inst/s)
+host_op_rate                                   120873                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              151511225                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 211580                       # Number of bytes of host memory used
+host_seconds                                     0.12                       # Real time elapsed on the host
 sim_insts                                       14449                       # Number of instructions simulated
+sim_ops                                         14449                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       30464                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  21120                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -234,6 +236,7 @@ system.cpu.iew.wb_rate                       0.481079                       # in
 system.cpu.iew.wb_fanout                     0.835184                       # average fanout of values written-back
 system.cpu.iew.wb_penalized_rate                    0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu.commit.commitCommittedInsts          15175                       # The number of committed instructions
+system.cpu.commit.commitCommittedOps            15175                       # The number of committed instructions
 system.cpu.commit.commitSquashedInsts            5794                       # The number of squashed insts skipped by commit
 system.cpu.commit.commitNonSpecStalls             475                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu.commit.branchMispredicts               847                       # The number of times a branch was mispredicted
@@ -254,7 +257,8 @@ system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.
 system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu.commit.committed_per_cycle::total        26259                       # Number of insts commited each cycle
-system.cpu.commit.count                         15175                       # Number of instructions committed
+system.cpu.commit.committedInsts                15175                       # Number of instructions committed
+system.cpu.commit.committedOps                  15175                       # Number of ops (including micro ops) committed
 system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
 system.cpu.commit.refs                           3674                       # Number of memory references committed
 system.cpu.commit.loads                          2226                       # Number of loads committed
@@ -270,6 +274,7 @@ system.cpu.rob.rob_writes                       43308                       # Th
 system.cpu.timesIdled                             181                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu.idleCycles                            8623                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu.committedInsts                       14449                       # Number of Instructions Simulated
+system.cpu.committedOps                         14449                       # Number of Ops (including micro ops) Simulated
 system.cpu.committedInsts_total                 14449                       # Number of Instructions Simulated
 system.cpu.cpi                               2.507371                       # CPI: Cycles Per Instruction
 system.cpu.cpi_total                         2.507371                       # CPI: Total CPI of All Threads
@@ -285,26 +290,39 @@ system.cpu.icache.total_refs                     4151                       # To
 system.cpu.icache.sampled_refs                    332                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  12.503012                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            193.216525                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.094344                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                   4151                       # number of ReadReq hits
-system.cpu.icache.demand_hits                    4151                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                   4151                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  457                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   457                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  457                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15956000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15956000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15956000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses               4608                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses                4608                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses               4608                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.099175                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.099175                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.099175                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency 34914.660832                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency 34914.660832                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency 34914.660832                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     193.216525                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.094344                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.094344                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst         4151                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total            4151                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst          4151                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total             4151                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst         4151                       # number of overall hits
+system.cpu.icache.overall_hits::total            4151                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          457                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           457                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          457                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            457                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          457                       # number of overall misses
+system.cpu.icache.overall_misses::total           457                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15956000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15956000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15956000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15956000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15956000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15956000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst         4608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total         4608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst         4608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total         4608                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst         4608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total         4608                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.099175                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.099175                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.099175                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 34914.660832                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst 34914.660832                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 34914.660832                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -313,27 +331,30 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.ReadReq_mshr_hits               125                       # number of ReadReq MSHR hits
-system.cpu.icache.demand_mshr_hits                125                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits               125                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             332                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              332                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             332                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     11653500                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     11653500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     11653500                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.072049                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.072049                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.072049                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency 35100.903614                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency 35100.903614                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency 35100.903614                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_hits::cpu.inst          125                       # number of ReadReq MSHR hits
+system.cpu.icache.ReadReq_mshr_hits::total          125                       # number of ReadReq MSHR hits
+system.cpu.icache.demand_mshr_hits::cpu.inst          125                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_hits::total          125                       # number of demand (read+write) MSHR hits
+system.cpu.icache.overall_mshr_hits::cpu.inst          125                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_hits::total          125                       # number of overall MSHR hits
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          332                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          332                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          332                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          332                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          332                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          332                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     11653500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     11653500                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     11653500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     11653500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     11653500                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     11653500                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.072049                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.072049                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.072049                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35100.903614                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35100.903614                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35100.903614                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                102.149831                       # Cycle average of tags in use
@@ -341,34 +362,53 @@ system.cpu.dcache.total_refs                     3712                       # To
 system.cpu.dcache.sampled_refs                    146                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  25.424658                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0            102.149831                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.024939                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   2672                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                  1034                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                    3706                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   3706                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                  114                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                 408                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   522                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  522                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        3994500                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency      14649500                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency        18644000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency       18644000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               2786                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                4228                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               4228                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.040919                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.282940                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.123463                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.123463                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency 35039.473684                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency 35905.637255                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency 35716.475096                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency 35716.475096                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data     102.149831                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.024939                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.024939                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         2672                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2672                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1034                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1034                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data          3706                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3706                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3706                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3706                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data          114                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total           114                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data          408                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total          408                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          522                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            522                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          522                       # number of overall misses
+system.cpu.dcache.overall_misses::total           522                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      3994500                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      3994500                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data     14649500                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total     14649500                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data     18644000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total     18644000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data     18644000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total     18644000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2786                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2786                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         4228                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         4228                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         4228                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         4228                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.040919                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.282940                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.123463                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.123463                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35039.473684                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35905.637255                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 35716.475096                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 35716.475096                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -377,32 +417,38 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits                51                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits              325                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits                376                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits               376                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              63                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             83                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              146                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             146                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2241500                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      2985000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      5226500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      5226500                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.022613                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.057559                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.034532                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.034532                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency 35579.365079                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency 35963.855422                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency 35797.945205                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency 35797.945205                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data           51                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::total           51                       # number of ReadReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data          325                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::total          325                       # number of WriteReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data          376                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total          376                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data          376                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total          376                       # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           63                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           83                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           83                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          146                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          146                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2241500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2241500                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      2985000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      2985000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      5226500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      5226500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      5226500                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      5226500                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.022613                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.057559                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.034532                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.034532                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35579.365079                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 35963.855422                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35797.945205                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35797.945205                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               228.374360                       # Cycle average of tags in use
@@ -410,31 +456,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   393                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.005089                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           228.374360                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.006969                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 393                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                83                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  476                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 476                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      13475000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      2872000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       16347000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      16347000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               395                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              83                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                478                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               478                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.994937                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995816                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995816                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency 34287.531807                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency 34602.409639                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency 34342.436975                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency 34342.436975                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    192.484909                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     35.889452                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.005874                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.001095                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.006969                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          330                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           63                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          393                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           83                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           83                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          330                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          146                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           476                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          330                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          146                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          476                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     11308000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2167000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     13475000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      2872000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      2872000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     11308000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      5039000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     16347000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     11308000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      5039000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     16347000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          332                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           63                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          395                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           83                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           83                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          332                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          146                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          478                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          332                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          146                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          478                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.993976                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.993976                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.993976                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34266.666667                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34396.825397                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34602.409639                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34266.666667                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34513.698630                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34266.666667                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34513.698630                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -443,30 +522,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            393                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           83                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             476                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            476                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     12215000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      2608500                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     14823500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     14823500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.994937                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995816                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995816                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 31081.424936                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 31427.710843                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency 31141.806723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency 31141.806723                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          330                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           63                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          393                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           83                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           83                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          330                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          146                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          476                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          330                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          146                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          476                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     10246500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      1968500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     12215000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      2608500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      2608500                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     10246500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      4577000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     14823500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     10246500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      4577000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     14823500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.993976                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.993976                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.993976                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        31050                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31246.031746                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31427.710843                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        31050                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31349.315068                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        31050                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31349.315068                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 421dd8a46efbe7270929b50e953da59234893558..b6cf50e7b29198453126de7bb2f517d5a74acfb3 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb itb tracer workload
+children=dtb interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -54,6 +64,9 @@ icache_port=system.membus.port[2]
 type=SparcTLB
 size=64
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
index df7964c68991214f39d00c625896cf9e77c51966..15efcd3a3349afe89f4400ca74e3d5e8a106c213 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:24
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:45
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-atomic
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
index 389636d62ba67c6101601958f27dcff27c6ee885..de9d99a5d5eef1dbda4aa6098b11af7f1f578cf4 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000008                       # Nu
 sim_ticks                                     7618500                       # Number of ticks simulated
 final_tick                                    7618500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 296178                       # Simulator instruction rate (inst/s)
-host_tick_rate                              148615294                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 203776                       # Number of bytes of host memory used
+host_inst_rate                                 298140                       # Simulator instruction rate (inst/s)
+host_op_rate                                   298037                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              149578582                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 201436                       # Number of bytes of host memory used
 host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       72223                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  60880                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                     9042                       # Number of bytes written to this memory
@@ -23,7 +25,8 @@ system.cpu.workload.num_syscalls                   18                       # Nu
 system.cpu.numCycles                            15238                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                            15175                       # Number of instructions executed
+system.cpu.committedInsts                       15175                       # Number of instructions committed
+system.cpu.committedOps                         15175                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         385                       # number of times a function call or return occured
index fb5a1cb831ea62b186ae1f7a89b9e0b4b348ab80..a5f3d508888eed0202106bec5c8f65cff19a0f6a 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu membus physmem
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[0]
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache itb l2cache toL2Bus tracer workload
+children=dcache dtb icache interrupts itb l2cache toL2Bus tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu.interrupts
 itb=system.cpu.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=262144
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=131072
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.port[0]
 
+[system.cpu.interrupts]
+type=SparcInterrupts
+
 [system.cpu.itb]
 type=SparcTLB
 size=64
@@ -130,20 +129,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=10
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=2097152
 subblock_size=0
+system=system
 tgts_per_mshr=5
 trace_addr=0
 two_queue=false
index d982745c0e0da0eaaa0578841e415d1b1427a752..6f63071eb5b58ad04c380fb60511048973dc60af 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:28
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:45
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC_SE/tests/opt/quick/02.insttest/sparc/linux/simple-timing
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/fast/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Begining test of difficult SPARC instructions...
index f528906379f3c600efbfddd640c6a2a731cc8abd..f7405d428d8ca01eb01401c2d404c2b3ec47de5d 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000042                       # Nu
 sim_ticks                                    41800000                       # Number of ticks simulated
 final_tick                                   41800000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 146106                       # Simulator instruction rate (inst/s)
-host_tick_rate                              402347608                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 212484                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_inst_rate                                 399467                       # Simulator instruction rate (inst/s)
+host_op_rate                                   399277                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1099343547                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 210560                       # Number of bytes of host memory used
+host_seconds                                     0.04                       # Real time elapsed on the host
 sim_insts                                       15175                       # Number of instructions simulated
+sim_ops                                         15175                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       26624                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  17792                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu.workload.num_syscalls                   18                       # Nu
 system.cpu.numCycles                            83600                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
 system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
-system.cpu.num_insts                            15175                       # Number of instructions executed
+system.cpu.committedInsts                       15175                       # Number of instructions committed
+system.cpu.committedOps                         15175                       # Number of ops (including micro ops) committed
 system.cpu.num_int_alu_accesses                 12231                       # Number of integer alu accesses
 system.cpu.num_fp_alu_accesses                      0                       # Number of float alu accesses
 system.cpu.num_func_calls                         385                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu.icache.total_refs                    14941                       # To
 system.cpu.icache.sampled_refs                    280                       # Sample count of references to valid blocks.
 system.cpu.icache.avg_refs                  53.360714                       # Average number of references to valid blocks.
 system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::0            153.436702                       # Average occupied blocks per context
-system.cpu.icache.occ_percent::0             0.074920                       # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits                  14941                       # number of ReadReq hits
-system.cpu.icache.demand_hits                   14941                       # number of demand (read+write) hits
-system.cpu.icache.overall_hits                  14941                       # number of overall hits
-system.cpu.icache.ReadReq_misses                  280                       # number of ReadReq misses
-system.cpu.icache.demand_misses                   280                       # number of demand (read+write) misses
-system.cpu.icache.overall_misses                  280                       # number of overall misses
-system.cpu.icache.ReadReq_miss_latency       15596000                       # number of ReadReq miss cycles
-system.cpu.icache.demand_miss_latency        15596000                       # number of demand (read+write) miss cycles
-system.cpu.icache.overall_miss_latency       15596000                       # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses              15221                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.demand_accesses               15221                       # number of demand (read+write) accesses
-system.cpu.icache.overall_accesses              15221                       # number of overall (read+write) accesses
-system.cpu.icache.ReadReq_miss_rate          0.018396                       # miss rate for ReadReq accesses
-system.cpu.icache.demand_miss_rate           0.018396                       # miss rate for demand accesses
-system.cpu.icache.overall_miss_rate          0.018396                       # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency        55700                       # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency        55700                       # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency        55700                       # average overall miss latency
+system.cpu.icache.occ_blocks::cpu.inst     153.436702                       # Average occupied blocks per requestor
+system.cpu.icache.occ_percent::cpu.inst      0.074920                       # Average percentage of cache occupancy
+system.cpu.icache.occ_percent::total         0.074920                       # Average percentage of cache occupancy
+system.cpu.icache.ReadReq_hits::cpu.inst        14941                       # number of ReadReq hits
+system.cpu.icache.ReadReq_hits::total           14941                       # number of ReadReq hits
+system.cpu.icache.demand_hits::cpu.inst         14941                       # number of demand (read+write) hits
+system.cpu.icache.demand_hits::total            14941                       # number of demand (read+write) hits
+system.cpu.icache.overall_hits::cpu.inst        14941                       # number of overall hits
+system.cpu.icache.overall_hits::total           14941                       # number of overall hits
+system.cpu.icache.ReadReq_misses::cpu.inst          280                       # number of ReadReq misses
+system.cpu.icache.ReadReq_misses::total           280                       # number of ReadReq misses
+system.cpu.icache.demand_misses::cpu.inst          280                       # number of demand (read+write) misses
+system.cpu.icache.demand_misses::total            280                       # number of demand (read+write) misses
+system.cpu.icache.overall_misses::cpu.inst          280                       # number of overall misses
+system.cpu.icache.overall_misses::total           280                       # number of overall misses
+system.cpu.icache.ReadReq_miss_latency::cpu.inst     15596000                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_latency::total     15596000                       # number of ReadReq miss cycles
+system.cpu.icache.demand_miss_latency::cpu.inst     15596000                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_latency::total     15596000                       # number of demand (read+write) miss cycles
+system.cpu.icache.overall_miss_latency::cpu.inst     15596000                       # number of overall miss cycles
+system.cpu.icache.overall_miss_latency::total     15596000                       # number of overall miss cycles
+system.cpu.icache.ReadReq_accesses::cpu.inst        15221                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_accesses::total        15221                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.demand_accesses::cpu.inst        15221                       # number of demand (read+write) accesses
+system.cpu.icache.demand_accesses::total        15221                       # number of demand (read+write) accesses
+system.cpu.icache.overall_accesses::cpu.inst        15221                       # number of overall (read+write) accesses
+system.cpu.icache.overall_accesses::total        15221                       # number of overall (read+write) accesses
+system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.018396                       # miss rate for ReadReq accesses
+system.cpu.icache.demand_miss_rate::cpu.inst     0.018396                       # miss rate for demand accesses
+system.cpu.icache.overall_miss_rate::cpu.inst     0.018396                       # miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst        55700                       # average ReadReq miss latency
+system.cpu.icache.demand_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst        55700                       # average overall miss latency
 system.cpu.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.icache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses             280                       # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses              280                       # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses             280                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.ReadReq_mshr_miss_latency     14756000                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency     14756000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency     14756000                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.018396                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate      0.018396                       # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate     0.018396                       # mshr miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_mshr_miss_latency        52700                       # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency        52700                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.ReadReq_mshr_misses::cpu.inst          280                       # number of ReadReq MSHR misses
+system.cpu.icache.ReadReq_mshr_misses::total          280                       # number of ReadReq MSHR misses
+system.cpu.icache.demand_mshr_misses::cpu.inst          280                       # number of demand (read+write) MSHR misses
+system.cpu.icache.demand_mshr_misses::total          280                       # number of demand (read+write) MSHR misses
+system.cpu.icache.overall_mshr_misses::cpu.inst          280                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_misses::total          280                       # number of overall MSHR misses
+system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst     14756000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_latency::total     14756000                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::cpu.inst     14756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_latency::total     14756000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::cpu.inst     14756000                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_latency::total     14756000                       # number of overall MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for demand accesses
+system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.018396                       # mshr miss rate for overall accesses
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst        52700                       # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst        52700                       # average overall mshr miss latency
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.dcache.replacements                      0                       # number of replacements
 system.cpu.dcache.tagsinuse                 97.842991                       # Cycle average of tags in use
@@ -101,34 +115,53 @@ system.cpu.dcache.total_refs                     3536                       # To
 system.cpu.dcache.sampled_refs                    138                       # Sample count of references to valid blocks.
 system.cpu.dcache.avg_refs                  25.623188                       # Average number of references to valid blocks.
 system.cpu.dcache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.occ_blocks::0             97.842991                       # Average occupied blocks per context
-system.cpu.dcache.occ_percent::0             0.023887                       # Average percentage of cache occupancy
-system.cpu.dcache.ReadReq_hits                   2173                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits                  1357                       # number of WriteReq hits
-system.cpu.dcache.SwapReq_hits                      6                       # number of SwapReq hits
-system.cpu.dcache.demand_hits                    3530                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits                   3530                       # number of overall hits
-system.cpu.dcache.ReadReq_misses                   53                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses                  85                       # number of WriteReq misses
-system.cpu.dcache.demand_misses                   138                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses                  138                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency        2968000                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency       4760000                       # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency         7728000                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency        7728000                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses               2226                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses              1442                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.SwapReq_accesses                  6                       # number of SwapReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses                3668                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses               3668                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate          0.023810                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate         0.058946                       # miss rate for WriteReq accesses
-system.cpu.dcache.demand_miss_rate           0.037623                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate          0.037623                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency        56000                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency        56000                       # average WriteReq miss latency
-system.cpu.dcache.demand_avg_miss_latency        56000                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency        56000                       # average overall miss latency
+system.cpu.dcache.occ_blocks::cpu.data      97.842991                       # Average occupied blocks per requestor
+system.cpu.dcache.occ_percent::cpu.data      0.023887                       # Average percentage of cache occupancy
+system.cpu.dcache.occ_percent::total         0.023887                       # Average percentage of cache occupancy
+system.cpu.dcache.ReadReq_hits::cpu.data         2173                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total            2173                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data         1357                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total           1357                       # number of WriteReq hits
+system.cpu.dcache.SwapReq_hits::cpu.data            6                       # number of SwapReq hits
+system.cpu.dcache.SwapReq_hits::total               6                       # number of SwapReq hits
+system.cpu.dcache.demand_hits::cpu.data          3530                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total             3530                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data         3530                       # number of overall hits
+system.cpu.dcache.overall_hits::total            3530                       # number of overall hits
+system.cpu.dcache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::total            53                       # number of ReadReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data           85                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::total           85                       # number of WriteReq misses
+system.cpu.dcache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::total            138                       # number of demand (read+write) misses
+system.cpu.dcache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.dcache.overall_misses::total           138                       # number of overall misses
+system.cpu.dcache.ReadReq_miss_latency::cpu.data      2968000                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::total      2968000                       # number of ReadReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data      4760000                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::total      4760000                       # number of WriteReq miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data      7728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::total      7728000                       # number of demand (read+write) miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data      7728000                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::total      7728000                       # number of overall miss cycles
+system.cpu.dcache.ReadReq_accesses::cpu.data         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total         2226                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total         1442                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::cpu.data            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.SwapReq_accesses::total            6                       # number of SwapReq accesses(hits+misses)
+system.cpu.dcache.demand_accesses::cpu.data         3668                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total         3668                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data         3668                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total         3668                       # number of overall (read+write) accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.023810                       # miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.058946                       # miss rate for WriteReq accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.037623                       # miss rate for demand accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.037623                       # miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data        56000                       # average ReadReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data        56000                       # average WriteReq miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data        56000                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data        56000                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked::no_mshrs                 0                       # number of cycles access was blocked
@@ -137,30 +170,30 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.writebacks                        0                       # number of writebacks
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses              53                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses             85                       # number of WriteReq MSHR misses
-system.cpu.dcache.demand_mshr_misses              138                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses             138                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.ReadReq_mshr_miss_latency      2809000                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency      4505000                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency      7314000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency      7314000                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.023810                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.058946                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.demand_mshr_miss_rate      0.037623                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate     0.037623                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency        53000                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency        53000                       # average WriteReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency        53000                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total           53                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data           85                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total           85                       # number of WriteReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total          138                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total          138                       # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data      2809000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total      2809000                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data      4505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total      4505000                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total      7314000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total      7314000                       # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.023810                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.058946                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.037623                       # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data        53000                       # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data        53000                       # average WriteReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data        53000                       # average overall mshr miss latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.l2cache.replacements                     0                       # number of replacements
 system.cpu.l2cache.tagsinuse               184.236128                       # Cycle average of tags in use
@@ -168,31 +201,64 @@ system.cpu.l2cache.total_refs                       2                       # To
 system.cpu.l2cache.sampled_refs                   331                       # Sample count of references to valid blocks.
 system.cpu.l2cache.avg_refs                  0.006042                       # Average number of references to valid blocks.
 system.cpu.l2cache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.occ_blocks::0           184.236128                       # Average occupied blocks per context
-system.cpu.l2cache.occ_percent::0            0.005622                       # Average percentage of cache occupancy
-system.cpu.l2cache.ReadReq_hits                     2                       # number of ReadReq hits
-system.cpu.l2cache.demand_hits                      2                       # number of demand (read+write) hits
-system.cpu.l2cache.overall_hits                     2                       # number of overall hits
-system.cpu.l2cache.ReadReq_misses                 331                       # number of ReadReq misses
-system.cpu.l2cache.ReadExReq_misses                85                       # number of ReadExReq misses
-system.cpu.l2cache.demand_misses                  416                       # number of demand (read+write) misses
-system.cpu.l2cache.overall_misses                 416                       # number of overall misses
-system.cpu.l2cache.ReadReq_miss_latency      17212000                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency      4420000                       # number of ReadExReq miss cycles
-system.cpu.l2cache.demand_miss_latency       21632000                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.overall_miss_latency      21632000                       # number of overall miss cycles
-system.cpu.l2cache.ReadReq_accesses               333                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses              85                       # number of ReadExReq accesses(hits+misses)
-system.cpu.l2cache.demand_accesses                418                       # number of demand (read+write) accesses
-system.cpu.l2cache.overall_accesses               418                       # number of overall (read+write) accesses
-system.cpu.l2cache.ReadReq_miss_rate         0.993994                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate              1                       # miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_miss_rate          0.995215                       # miss rate for demand accesses
-system.cpu.l2cache.overall_miss_rate         0.995215                       # miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_miss_latency        52000                       # average ReadReq miss latency
-system.cpu.l2cache.ReadExReq_avg_miss_latency        52000                       # average ReadExReq miss latency
-system.cpu.l2cache.demand_avg_miss_latency        52000                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency        52000                       # average overall miss latency
+system.cpu.l2cache.occ_blocks::cpu.inst    152.765242                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_blocks::cpu.data     31.470886                       # Average occupied blocks per requestor
+system.cpu.l2cache.occ_percent::cpu.inst     0.004662                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::cpu.data     0.000960                       # Average percentage of cache occupancy
+system.cpu.l2cache.occ_percent::total        0.005622                       # Average percentage of cache occupancy
+system.cpu.l2cache.ReadReq_hits::cpu.inst            2                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::total              2                       # number of ReadReq hits
+system.cpu.l2cache.demand_hits::cpu.inst            2                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::total               2                       # number of demand (read+write) hits
+system.cpu.l2cache.overall_hits::cpu.inst            2                       # number of overall hits
+system.cpu.l2cache.overall_hits::total              2                       # number of overall hits
+system.cpu.l2cache.ReadReq_misses::cpu.inst          278                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::cpu.data           53                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_misses::total          331                       # number of ReadReq misses
+system.cpu.l2cache.ReadExReq_misses::cpu.data           85                       # number of ReadExReq misses
+system.cpu.l2cache.ReadExReq_misses::total           85                       # number of ReadExReq misses
+system.cpu.l2cache.demand_misses::cpu.inst          278                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data          138                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::total           416                       # number of demand (read+write) misses
+system.cpu.l2cache.overall_misses::cpu.inst          278                       # number of overall misses
+system.cpu.l2cache.overall_misses::cpu.data          138                       # number of overall misses
+system.cpu.l2cache.overall_misses::total          416                       # number of overall misses
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst     14456000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.data      2756000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::total     17212000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::cpu.data      4420000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.ReadExReq_miss_latency::total      4420000                       # number of ReadExReq miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.inst     14456000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::cpu.data      7176000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_latency::total     21632000                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst     14456000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.data      7176000                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::total     21632000                       # number of overall miss cycles
+system.cpu.l2cache.ReadReq_accesses::cpu.inst          280                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::cpu.data           53                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_accesses::total          333                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::cpu.data           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.ReadExReq_accesses::total           85                       # number of ReadExReq accesses(hits+misses)
+system.cpu.l2cache.demand_accesses::cpu.inst          280                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::cpu.data          138                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_accesses::total          418                       # number of demand (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.inst          280                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::cpu.data          138                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_accesses::total          418                       # number of overall (read+write) accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.992857                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_miss_rate::cpu.data            1                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_miss_rate::cpu.data            1                       # miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_miss_rate::cpu.inst     0.992857                       # miss rate for demand accesses
+system.cpu.l2cache.demand_miss_rate::cpu.data            1                       # miss rate for demand accesses
+system.cpu.l2cache.overall_miss_rate::cpu.inst     0.992857                       # miss rate for overall accesses
+system.cpu.l2cache.overall_miss_rate::cpu.data            1                       # miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data        52000                       # average ReadReq miss latency
+system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data        52000                       # average ReadExReq miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst        52000                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data        52000                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -201,30 +267,42 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu.l2cache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.writebacks                       0                       # number of writebacks
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.ReadReq_mshr_misses            331                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses           85                       # number of ReadExReq MSHR misses
-system.cpu.l2cache.demand_mshr_misses             416                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.overall_mshr_misses            416                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency     13240000                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency      3400000                       # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency     16640000                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency     16640000                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.993994                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate            1                       # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate     0.995215                       # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate     0.995215                       # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency        40000                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency        40000                       # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency        40000                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst          278                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data           53                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::total          331                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::total           85                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst          278                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data          138                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::total          416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst          278                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data          138                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::total          416                       # number of overall MSHR misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst     11120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data      2120000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::total     13240000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data      3400000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::total      3400000                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst     11120000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data      5520000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::total     16640000                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst     11120000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data      5520000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::total     16640000                       # number of overall MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data            1                       # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.992857                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data            1                       # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data        40000                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst        40000                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data        40000                       # average overall mshr miss latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index eb497bb9073b778d3ef34749772cdf244cd5a3dc..bb8df191a787a9869778f27d21899bbbf6976bc6 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,7 +30,7 @@ system_port=system.membus.port[2]
 
 [system.cpu0]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer workload
+children=dcache dtb fuPool icache interrupts itb tracer workload
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -52,6 +59,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
 fetchToDecodeDelay=1
@@ -69,6 +77,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu0.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu0.itb
@@ -80,6 +89,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -88,6 +98,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -125,20 +136,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -424,20 +428,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -445,6 +442,9 @@ write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.port[1]
 
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
 [system.cpu0.itb]
 type=SparcTLB
 size=64
@@ -473,7 +473,7 @@ uid=100
 
 [system.cpu1]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -502,6 +502,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
 fetchToDecodeDelay=1
@@ -519,6 +520,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu1.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu1.itb
@@ -530,6 +532,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -538,6 +541,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -575,20 +579,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -874,20 +871,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -895,6 +885,9 @@ write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.port[3]
 
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
 [system.cpu1.itb]
 type=SparcTLB
 size=64
@@ -904,7 +897,7 @@ type=ExeTracer
 
 [system.cpu2]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -933,6 +926,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu2.dtb
 fetchToDecodeDelay=1
@@ -950,6 +944,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu2.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu2.itb
@@ -961,6 +956,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -969,6 +965,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -1006,20 +1003,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -1305,20 +1295,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -1326,6 +1309,9 @@ write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.port[5]
 
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
 [system.cpu2.itb]
 type=SparcTLB
 size=64
@@ -1335,7 +1321,7 @@ type=ExeTracer
 
 [system.cpu3]
 type=DerivO3CPU
-children=dcache dtb fuPool icache itb tracer
+children=dcache dtb fuPool icache interrupts itb tracer
 BTBEntries=4096
 BTBTagSize=16
 LFSTSize=1024
@@ -1364,6 +1350,7 @@ decodeWidth=8
 defer_registration=false
 dispatchWidth=8
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu3.dtb
 fetchToDecodeDelay=1
@@ -1381,6 +1368,7 @@ iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
 instShiftAmt=2
+interrupts=system.cpu3.interrupts
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu3.itb
@@ -1392,6 +1380,7 @@ max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
 max_loads_any_thread=0
+needsTSO=false
 numIQEntries=64
 numPhysFloatRegs=256
 numPhysIntRegs=256
@@ -1400,6 +1389,7 @@ numRobs=1
 numThreads=1
 phase=0
 predType=tournament
+profile=0
 progress_interval=0
 renameToDecodeDelay=1
 renameToFetchDelay=1
@@ -1437,20 +1427,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -1736,20 +1719,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=20
 trace_addr=0
 two_queue=false
@@ -1757,6 +1733,9 @@ write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.port[7]
 
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
 [system.cpu3.itb]
 type=SparcTLB
 size=64
@@ -1775,20 +1754,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
index 0491d51410c0c6e93ea5a73fc68e93cdefc44fd2..2bb2951e29297f76cee24d740a531742a0be917e 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:31
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:55
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
index 191a420605bb33bb13887619b4c280ba004ef622..befe09ef81c60854332f151840568c0a1d1bc63c 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000104                       # Nu
 sim_ticks                                   104317500                       # Number of ticks simulated
 final_tick                                  104317500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 132902                       # Simulator instruction rate (inst/s)
-host_tick_rate                               13605540                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 226920                       # Number of bytes of host memory used
-host_seconds                                     7.67                       # Real time elapsed on the host
+host_inst_rate                                 190796                       # Simulator instruction rate (inst/s)
+host_op_rate                                   190795                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               19532213                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 225896                       # Number of bytes of host memory used
+host_seconds                                     5.34                       # Real time elapsed on the host
 sim_insts                                     1018993                       # Number of instructions simulated
+sim_ops                                       1018993                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       41984                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  28224                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -234,6 +236,7 @@ system.cpu0.iew.wb_rate                      1.886424                       # in
 system.cpu0.iew.wb_fanout                    0.991039                       # average fanout of values written-back
 system.cpu0.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu0.commit.commitCommittedInsts        462799                       # The number of committed instructions
+system.cpu0.commit.commitCommittedOps          462799                       # The number of committed instructions
 system.cpu0.commit.commitSquashedInsts           9535                       # The number of squashed insts skipped by commit
 system.cpu0.commit.commitNonSpecStalls            559                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu0.commit.branchMispredicts             1043                       # The number of times a branch was mispredicted
@@ -254,7 +257,8 @@ system.cpu0.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu0.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu0.commit.committed_per_cycle::total       188840                       # Number of insts commited each cycle
-system.cpu0.commit.count                       462799                       # Number of instructions committed
+system.cpu0.commit.committedInsts              462799                       # Number of instructions committed
+system.cpu0.commit.committedOps                462799                       # Number of ops (including micro ops) committed
 system.cpu0.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu0.commit.refs                        226109                       # Number of memory references committed
 system.cpu0.commit.loads                       150402                       # Number of loads committed
@@ -270,6 +274,7 @@ system.cpu0.rob.rob_writes                     946703                       # Th
 system.cpu0.timesIdled                            320                       # Number of times that the entire CPU went into an idle state and unscheduled itself
 system.cpu0.idleCycles                          17790                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu0.committedInsts                     388389                       # Number of Instructions Simulated
+system.cpu0.committedOps                       388389                       # Number of Ops (including micro ops) Simulated
 system.cpu0.committedInsts_total               388389                       # Number of Instructions Simulated
 system.cpu0.cpi                              0.537183                       # CPI: Cycles Per Instruction
 system.cpu0.cpi_total                        0.537183                       # CPI: Total CPI of All Threads
@@ -286,26 +291,39 @@ system.cpu0.icache.total_refs                    4810                       # To
 system.cpu0.icache.sampled_refs                   581                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                  8.278830                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           244.353680                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.477253                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits                  4810                       # number of ReadReq hits
-system.cpu0.icache.demand_hits                   4810                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits                  4810                       # number of overall hits
-system.cpu0.icache.ReadReq_misses                 705                       # number of ReadReq misses
-system.cpu0.icache.demand_misses                  705                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses                 705                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency      27622000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency       27622000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency      27622000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses              5515                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses               5515                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses              5515                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate         0.127833                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate          0.127833                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate         0.127833                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39180.141844                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39180.141844                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39180.141844                       # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst   244.353680                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.477253                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.477253                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst         4810                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total           4810                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst         4810                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total            4810                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst         4810                       # number of overall hits
+system.cpu0.icache.overall_hits::total           4810                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          705                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          705                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          705                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           705                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          705                       # number of overall misses
+system.cpu0.icache.overall_misses::total          705                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     27622000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     27622000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     27622000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     27622000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     27622000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     27622000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst         5515                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total         5515                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst         5515                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total         5515                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst         5515                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total         5515                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.127833                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.127833                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.127833                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39180.141844                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39180.141844                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39180.141844                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs        15500                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -314,68 +332,90 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs        15500
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.icache.ReadReq_mshr_hits              123                       # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits               123                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits              123                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses            582                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses             582                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses            582                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency     21369000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency     21369000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency     21369000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate     0.105530                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate     0.105530                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate     0.105530                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36716.494845                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36716.494845                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36716.494845                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst          123                       # number of ReadReq MSHR hits
+system.cpu0.icache.ReadReq_mshr_hits::total          123                       # number of ReadReq MSHR hits
+system.cpu0.icache.demand_mshr_hits::cpu0.inst          123                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.demand_mshr_hits::total          123                       # number of demand (read+write) MSHR hits
+system.cpu0.icache.overall_mshr_hits::cpu0.inst          123                       # number of overall MSHR hits
+system.cpu0.icache.overall_mshr_hits::total          123                       # number of overall MSHR hits
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          582                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          582                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          582                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          582                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          582                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          582                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     21369000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     21369000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     21369000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     21369000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     21369000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     21369000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.105530                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.105530                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.105530                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36716.494845                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36716.494845                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36716.494845                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     9                       # number of replacements
-system.cpu0.dcache.tagsinuse               138.901719                       # Cycle average of tags in use
+system.cpu0.dcache.tagsinuse               140.432794                       # Cycle average of tags in use
 system.cpu0.dcache.total_refs                   97328                       # Total number of references to valid blocks.
 system.cpu0.dcache.sampled_refs                   174                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                559.356322                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           140.432794                       # Average occupied blocks per context
-system.cpu0.dcache.occ_blocks::1            -1.531076                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.274283                       # Average percentage of cache occupancy
-system.cpu0.dcache.occ_percent::1           -0.002990                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits                 77005                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits                75125                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits                    23                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits                 152130                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits                152130                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses                 517                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses                540                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses                  19                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses                 1057                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses                1057                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency      14734500                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency     24692984                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency        371000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency       39427484                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency      39427484                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses             77522                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses            75665                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses             153187                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses            153187                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate         0.006669                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate        0.007137                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate         0.452381                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate          0.006900                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate         0.006900                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency        28500                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency 45727.748148                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency 19526.315789                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency 37301.309366                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency 37301.309366                       # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data   140.432794                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.274283                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.274283                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        77005                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          77005                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        75125                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         75125                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           23                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             23                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data       152130                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total          152130                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data       152130                       # number of overall hits
+system.cpu0.dcache.overall_hits::total         152130                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          517                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          517                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          540                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          540                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           19                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           19                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data         1057                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total          1057                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data         1057                       # number of overall misses
+system.cpu0.dcache.overall_misses::total         1057                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data     14734500                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total     14734500                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data     24692984                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total     24692984                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       371000                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       371000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     39427484                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     39427484                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     39427484                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     39427484                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        77522                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        77522                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        75665                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        75665                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data       153187                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total       153187                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data       153187                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total       153187                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.006669                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007137                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.452381                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.006900                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.006900                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data        28500                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45727.748148                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19526.315789                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 37301.309366                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 37301.309366                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs       180500                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs               21                       # number of cycles access was blocked
@@ -384,36 +424,46 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs  8595.238095
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                       6                       # number of writebacks
-system.cpu0.dcache.ReadReq_mshr_hits              327                       # number of ReadReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_hits             368                       # number of WriteReq MSHR hits
-system.cpu0.dcache.demand_mshr_hits               695                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits              695                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses            190                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses           172                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses             19                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses             362                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses            362                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency      5255000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency      6251500                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency       314000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency     11506500                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency     11506500                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate     0.002451                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate     0.002273                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate     0.452381                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate     0.002363                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate     0.002363                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 27657.894737                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36345.930233                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 16526.315789                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31785.911602                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31785.911602                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
+system.cpu0.dcache.writebacks::total                6                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data          327                       # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total          327                       # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data          368                       # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total          368                       # number of WriteReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data          695                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total          695                       # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data          695                       # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total          695                       # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          190                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          190                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          172                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          172                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           19                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           19                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          362                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          362                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          362                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          362                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      5255000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      5255000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6251500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6251500                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       314000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       314000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     11506500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     11506500                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     11506500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     11506500                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.002451                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.002273                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.452381                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.002363                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.002363                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 27657.894737                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36345.930233                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 16526.315789                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31785.911602                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31785.911602                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                          174305                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
@@ -631,6 +681,7 @@ system.cpu1.iew.wb_rate                      1.379140                       # in
 system.cpu1.iew.wb_fanout                    0.968192                       # average fanout of values written-back
 system.cpu1.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu1.commit.commitCommittedInsts        275667                       # The number of committed instructions
+system.cpu1.commit.commitCommittedOps          275667                       # The number of committed instructions
 system.cpu1.commit.commitSquashedInsts           9533                       # The number of squashed insts skipped by commit
 system.cpu1.commit.commitNonSpecStalls           5427                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu1.commit.branchMispredicts             1085                       # The number of times a branch was mispredicted
@@ -651,7 +702,8 @@ system.cpu1.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu1.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu1.commit.committed_per_cycle::total       163203                       # Number of insts commited each cycle
-system.cpu1.commit.count                       275667                       # Number of instructions committed
+system.cpu1.commit.committedInsts              275667                       # Number of instructions committed
+system.cpu1.commit.committedOps                275667                       # Number of ops (including micro ops) committed
 system.cpu1.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu1.commit.refs                        118493                       # Number of memory references committed
 system.cpu1.commit.loads                        80399                       # Number of loads committed
@@ -668,6 +720,7 @@ system.cpu1.timesIdled                            225                       # Nu
 system.cpu1.idleCycles                           2707                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu1.quiesceCycles                       34329                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu1.committedInsts                     231385                       # Number of Instructions Simulated
+system.cpu1.committedOps                       231385                       # Number of Ops (including micro ops) Simulated
 system.cpu1.committedInsts_total               231385                       # Number of Instructions Simulated
 system.cpu1.cpi                              0.753312                       # CPI: Cycles Per Instruction
 system.cpu1.cpi_total                        0.753312                       # CPI: Total CPI of All Threads
@@ -684,26 +737,39 @@ system.cpu1.icache.total_refs                   17870                       # To
 system.cpu1.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                 41.850117                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0            84.541118                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.165119                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits                 17870                       # number of ReadReq hits
-system.cpu1.icache.demand_hits                  17870                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits                 17870                       # number of overall hits
-system.cpu1.icache.ReadReq_misses                 471                       # number of ReadReq misses
-system.cpu1.icache.demand_misses                  471                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses                 471                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency       7203000                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency        7203000                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency       7203000                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses             18341                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses              18341                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses             18341                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate         0.025680                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate          0.025680                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate         0.025680                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency 15292.993631                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency 15292.993631                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency 15292.993631                       # average overall miss latency
+system.cpu1.icache.occ_blocks::cpu1.inst    84.541118                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.165119                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.165119                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst        17870                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total          17870                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst        17870                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total           17870                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst        17870                       # number of overall hits
+system.cpu1.icache.overall_hits::total          17870                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          471                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          471                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          471                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           471                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          471                       # number of overall misses
+system.cpu1.icache.overall_misses::total          471                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7203000                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      7203000                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      7203000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      7203000                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      7203000                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      7203000                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst        18341                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total        18341                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst        18341                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total        18341                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst        18341                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total        18341                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.025680                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.025680                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.025680                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15292.993631                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15292.993631                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15292.993631                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -712,68 +778,90 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                       0                       # number of writebacks
-system.cpu1.icache.ReadReq_mshr_hits               44                       # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits                44                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits               44                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses            427                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses            427                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency      5374000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency      5374000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency      5374000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate     0.023281                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate     0.023281                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate     0.023281                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 12585.480094                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 12585.480094                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 12585.480094                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst           44                       # number of ReadReq MSHR hits
+system.cpu1.icache.ReadReq_mshr_hits::total           44                       # number of ReadReq MSHR hits
+system.cpu1.icache.demand_mshr_hits::cpu1.inst           44                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.demand_mshr_hits::total           44                       # number of demand (read+write) MSHR hits
+system.cpu1.icache.overall_mshr_hits::cpu1.inst           44                       # number of overall MSHR hits
+system.cpu1.icache.overall_mshr_hits::total           44                       # number of overall MSHR hits
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          427                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          427                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          427                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          427                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          427                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          427                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      5374000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      5374000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      5374000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      5374000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      5374000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      5374000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.023281                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.023281                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.023281                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12585.480094                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 12585.480094                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 12585.480094                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     2                       # number of replacements
-system.cpu1.dcache.tagsinuse                18.588243                       # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse                24.401572                       # Cycle average of tags in use
 system.cpu1.dcache.total_refs                   44082                       # Total number of references to valid blocks.
 system.cpu1.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs               1469.400000                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0            24.401572                       # Average occupied blocks per context
-system.cpu1.dcache.occ_blocks::1            -5.813330                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.047659                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::1           -0.011354                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits                 46660                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits                37905                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits                    13                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits                  84565                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits                 84565                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses                 478                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses                124                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses                  52                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses                  602                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses                 602                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency      10261500                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency      2943000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency       1149500                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency       13204500                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency      13204500                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses             47138                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses            38029                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses                65                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses              85167                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses             85167                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate         0.010140                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate        0.003261                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate         0.800000                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate          0.007068                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate         0.007068                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency 21467.573222                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency 23733.870968                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency 22105.769231                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency 21934.385382                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency 21934.385382                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::cpu1.data    24.401572                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.047659                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.047659                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data        46660                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          46660                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        37905                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         37905                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           13                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        84565                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           84565                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        84565                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          84565                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          478                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          478                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          124                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          124                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           52                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           52                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          602                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           602                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          602                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          602                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data     10261500                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total     10261500                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      2943000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      2943000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data      1149500                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total      1149500                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data     13204500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total     13204500                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data     13204500                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total     13204500                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        47138                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        47138                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        38029                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        38029                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           65                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           65                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        85167                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        85167                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        85167                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        85167                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.010140                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.003261                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.800000                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.007068                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.007068                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 21467.573222                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23733.870968                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 22105.769231                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21934.385382                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21934.385382                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -782,36 +870,46 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                       1                       # number of writebacks
-system.cpu1.dcache.ReadReq_mshr_hits              323                       # number of ReadReq MSHR hits
-system.cpu1.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
-system.cpu1.dcache.demand_mshr_hits               341                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits              341                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses            155                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses           106                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses             52                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses             261                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses            261                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency      2079000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency      1617000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency       993500                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency      3696000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency      3696000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate     0.003288                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate     0.002787                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate     0.003065                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate     0.003065                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 13412.903226                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 15254.716981                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency 19105.769231                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 14160.919540                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 14160.919540                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu1.dcache.writebacks::total                1                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data          323                       # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total          323                       # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data           18                       # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total           18                       # number of WriteReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data          341                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total          341                       # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data          341                       # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total          341                       # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          155                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          155                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total          106                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           52                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           52                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          261                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          261                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          261                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          261                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      2079000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      2079000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1617000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1617000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       993500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       993500                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      3696000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      3696000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      3696000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      3696000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.003288                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.002787                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.003065                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.003065                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13412.903226                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 15254.716981                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 19105.769231                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 14160.919540                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 14160.919540                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.numCycles                          174018                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
@@ -1029,6 +1127,7 @@ system.cpu2.iew.wb_rate                      1.290855                       # in
 system.cpu2.iew.wb_fanout                    0.966435                       # average fanout of values written-back
 system.cpu2.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu2.commit.commitCommittedInsts        256708                       # The number of committed instructions
+system.cpu2.commit.commitCommittedOps          256708                       # The number of committed instructions
 system.cpu2.commit.commitSquashedInsts          10074                       # The number of squashed insts skipped by commit
 system.cpu2.commit.commitNonSpecStalls           5686                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu2.commit.branchMispredicts             1149                       # The number of times a branch was mispredicted
@@ -1049,7 +1148,8 @@ system.cpu2.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu2.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu2.commit.committed_per_cycle::total       160519                       # Number of insts commited each cycle
-system.cpu2.commit.count                       256708                       # Number of instructions committed
+system.cpu2.commit.committedInsts              256708                       # Number of instructions committed
+system.cpu2.commit.committedOps                256708                       # Number of ops (including micro ops) committed
 system.cpu2.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu2.commit.refs                        108759                       # Number of memory references committed
 system.cpu2.commit.loads                        73984                       # Number of loads committed
@@ -1066,6 +1166,7 @@ system.cpu2.timesIdled                            232                       # Nu
 system.cpu2.idleCycles                           5048                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu2.quiesceCycles                       34616                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu2.committedInsts                     215254                       # Number of Instructions Simulated
+system.cpu2.committedOps                       215254                       # Number of Ops (including micro ops) Simulated
 system.cpu2.committedInsts_total               215254                       # Number of Instructions Simulated
 system.cpu2.cpi                              0.808431                       # CPI: Cycles Per Instruction
 system.cpu2.cpi_total                        0.808431                       # CPI: Total CPI of All Threads
@@ -1082,26 +1183,39 @@ system.cpu2.icache.total_refs                   18578                       # To
 system.cpu2.icache.sampled_refs                   427                       # Sample count of references to valid blocks.
 system.cpu2.icache.avg_refs                 43.508197                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::0            85.227474                       # Average occupied blocks per context
-system.cpu2.icache.occ_percent::0            0.166460                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits                 18578                       # number of ReadReq hits
-system.cpu2.icache.demand_hits                  18578                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits                 18578                       # number of overall hits
-system.cpu2.icache.ReadReq_misses                 481                       # number of ReadReq misses
-system.cpu2.icache.demand_misses                  481                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses                 481                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency      10446500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency       10446500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency      10446500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses             19059                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses              19059                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses             19059                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate         0.025237                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate          0.025237                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate         0.025237                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency 21718.295218                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency 21718.295218                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency 21718.295218                       # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst    85.227474                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.166460                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.166460                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst        18578                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total          18578                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst        18578                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total           18578                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst        18578                       # number of overall hits
+system.cpu2.icache.overall_hits::total          18578                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          481                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          481                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          481                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           481                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          481                       # number of overall misses
+system.cpu2.icache.overall_misses::total          481                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst     10446500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total     10446500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst     10446500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total     10446500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst     10446500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total     10446500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst        19059                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total        19059                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst        19059                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total        19059                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst        19059                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total        19059                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.025237                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.025237                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.025237                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 21718.295218                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 21718.295218                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 21718.295218                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs        33000                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                1                       # number of cycles access was blocked
@@ -1110,68 +1224,90 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs        33000
 system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.writebacks                       0                       # number of writebacks
-system.cpu2.icache.ReadReq_mshr_hits               54                       # number of ReadReq MSHR hits
-system.cpu2.icache.demand_mshr_hits                54                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits               54                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses            427                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses             427                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses            427                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.icache.ReadReq_mshr_miss_latency      8026500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency      8026500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency      8026500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate     0.022404                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate     0.022404                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate     0.022404                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 18797.423888                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 18797.423888                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 18797.423888                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst           54                       # number of ReadReq MSHR hits
+system.cpu2.icache.ReadReq_mshr_hits::total           54                       # number of ReadReq MSHR hits
+system.cpu2.icache.demand_mshr_hits::cpu2.inst           54                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.demand_mshr_hits::total           54                       # number of demand (read+write) MSHR hits
+system.cpu2.icache.overall_mshr_hits::cpu2.inst           54                       # number of overall MSHR hits
+system.cpu2.icache.overall_mshr_hits::total           54                       # number of overall MSHR hits
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          427                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          427                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          427                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          427                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          427                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          427                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      8026500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      8026500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      8026500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      8026500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      8026500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      8026500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.022404                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.022404                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.022404                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 18797.423888                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 18797.423888                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 18797.423888                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     2                       # number of replacements
-system.cpu2.dcache.tagsinuse                19.370911                       # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse                26.582846                       # Cycle average of tags in use
 system.cpu2.dcache.total_refs                   40686                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    30                       # Sample count of references to valid blocks.
 system.cpu2.dcache.avg_refs               1356.200000                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::0            26.582846                       # Average occupied blocks per context
-system.cpu2.dcache.occ_blocks::1            -7.211935                       # Average occupied blocks per context
-system.cpu2.dcache.occ_percent::0            0.051920                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::1           -0.014086                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits                 43569                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits                34581                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits                    13                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits                  78150                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits                 78150                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses                 459                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses                120                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses                  61                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses                  579                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses                 579                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency      10999500                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency      2980500                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency       1343500                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency       13980000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency      13980000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses             44028                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses            34701                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses                74                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses              78729                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses             78729                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate         0.010425                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate        0.003458                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate         0.824324                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate          0.007354                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate         0.007354                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency 23964.052288                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency 24837.500000                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency 22024.590164                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency 24145.077720                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency 24145.077720                       # average overall miss latency
+system.cpu2.dcache.occ_blocks::cpu2.data    26.582846                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.051920                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.051920                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data        43569                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          43569                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        34581                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         34581                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           13                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             13                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        78150                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           78150                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        78150                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          78150                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          459                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          459                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          120                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          120                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           61                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           61                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          579                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           579                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          579                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          579                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data     10999500                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total     10999500                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2980500                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      2980500                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data      1343500                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total      1343500                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data     13980000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total     13980000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data     13980000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total     13980000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        44028                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        44028                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        34701                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        34701                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           74                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           74                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        78729                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        78729                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        78729                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        78729                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.010425                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.003458                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.824324                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.007354                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.007354                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 23964.052288                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 24837.500000                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 22024.590164                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 24145.077720                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 24145.077720                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1180,36 +1316,46 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks                       1                       # number of writebacks
-system.cpu2.dcache.ReadReq_mshr_hits              297                       # number of ReadReq MSHR hits
-system.cpu2.dcache.WriteReq_mshr_hits              18                       # number of WriteReq MSHR hits
-system.cpu2.dcache.demand_mshr_hits               315                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits              315                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses           102                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses             61                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses             264                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses            264                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency      2380000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency      1660000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency      1160500                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency      4040000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency      4040000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003679                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate     0.002939                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate     0.824324                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate     0.003353                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate     0.003353                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 14691.358025                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16274.509804                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency 19024.590164                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency 15303.030303                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency 15303.030303                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu2.dcache.writebacks::total                1                       # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data          297                       # number of ReadReq MSHR hits
+system.cpu2.dcache.ReadReq_mshr_hits::total          297                       # number of ReadReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data           18                       # number of WriteReq MSHR hits
+system.cpu2.dcache.WriteReq_mshr_hits::total           18                       # number of WriteReq MSHR hits
+system.cpu2.dcache.demand_mshr_hits::cpu2.data          315                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.demand_mshr_hits::total          315                       # number of demand (read+write) MSHR hits
+system.cpu2.dcache.overall_mshr_hits::cpu2.data          315                       # number of overall MSHR hits
+system.cpu2.dcache.overall_mshr_hits::total          315                       # number of overall MSHR hits
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          102                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          102                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           61                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           61                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          264                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          264                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          264                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          264                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2380000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2380000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1660000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1660000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data      1160500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total      1160500                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      4040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      4040000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      4040000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      4040000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003679                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.002939                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.824324                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.003353                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.003353                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 14691.358025                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16274.509804                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 19024.590164                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 15303.030303                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 15303.030303                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.numCycles                          173752                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
@@ -1427,6 +1573,7 @@ system.cpu3.iew.wb_rate                      1.121909                       # in
 system.cpu3.iew.wb_fanout                    0.961453                       # average fanout of values written-back
 system.cpu3.iew.wb_penalized_rate                   0                       # fraction of instructions written-back that wrote to 'other' IQ
 system.cpu3.commit.commitCommittedInsts        222296                       # The number of committed instructions
+system.cpu3.commit.commitCommittedOps          222296                       # The number of committed instructions
 system.cpu3.commit.commitSquashedInsts           9409                       # The number of squashed insts skipped by commit
 system.cpu3.commit.commitNonSpecStalls           7641                       # The number of times commit has been forced to stall to communicate backwards
 system.cpu3.commit.branchMispredicts             1065                       # The number of times a branch was mispredicted
@@ -1447,7 +1594,8 @@ system.cpu3.commit.committed_per_cycle::overflows            0      0.00%    100
 system.cpu3.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
 system.cpu3.commit.committed_per_cycle::total       162652                       # Number of insts commited each cycle
-system.cpu3.commit.count                       222296                       # Number of instructions committed
+system.cpu3.commit.committedInsts              222296                       # Number of instructions committed
+system.cpu3.commit.committedOps                222296                       # Number of ops (including micro ops) committed
 system.cpu3.commit.swp_count                        0                       # Number of s/w prefetches committed
 system.cpu3.commit.refs                         89597                       # Number of memory references committed
 system.cpu3.commit.loads                        61865                       # Number of loads committed
@@ -1464,6 +1612,7 @@ system.cpu3.timesIdled                            234                       # Nu
 system.cpu3.idleCycles                           2770                       # Total number of cycles that the CPU has spent unscheduled due to idling
 system.cpu3.quiesceCycles                       34882                       # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
 system.cpu3.committedInsts                     183965                       # Number of Instructions Simulated
+system.cpu3.committedOps                       183965                       # Number of Ops (including micro ops) Simulated
 system.cpu3.committedInsts_total               183965                       # Number of Instructions Simulated
 system.cpu3.cpi                              0.944484                       # CPI: Cycles Per Instruction
 system.cpu3.cpi_total                        0.944484                       # CPI: Total CPI of All Threads
@@ -1480,26 +1629,39 @@ system.cpu3.icache.total_refs                   22493                       # To
 system.cpu3.icache.sampled_refs                   426                       # Sample count of references to valid blocks.
 system.cpu3.icache.avg_refs                 52.800469                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::0            80.006059                       # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0            0.156262                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits                 22493                       # number of ReadReq hits
-system.cpu3.icache.demand_hits                  22493                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits                 22493                       # number of overall hits
-system.cpu3.icache.ReadReq_misses                 466                       # number of ReadReq misses
-system.cpu3.icache.demand_misses                  466                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses                 466                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency       6527000                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency        6527000                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency       6527000                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses             22959                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses              22959                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses             22959                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate         0.020297                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate          0.020297                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate         0.020297                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency 14006.437768                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency 14006.437768                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency 14006.437768                       # average overall miss latency
+system.cpu3.icache.occ_blocks::cpu3.inst    80.006059                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.156262                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.156262                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst        22493                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total          22493                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst        22493                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total           22493                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst        22493                       # number of overall hits
+system.cpu3.icache.overall_hits::total          22493                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          466                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          466                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          466                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           466                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          466                       # number of overall misses
+system.cpu3.icache.overall_misses::total          466                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      6527000                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      6527000                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      6527000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      6527000                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      6527000                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      6527000                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst        22959                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total        22959                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst        22959                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total        22959                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst        22959                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total        22959                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.020297                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.020297                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.020297                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14006.437768                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14006.437768                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14006.437768                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1508,68 +1670,90 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.writebacks                       0                       # number of writebacks
-system.cpu3.icache.ReadReq_mshr_hits               40                       # number of ReadReq MSHR hits
-system.cpu3.icache.demand_mshr_hits                40                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits               40                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses            426                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses             426                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses            426                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.icache.ReadReq_mshr_miss_latency      4833500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency      4833500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency      4833500                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate     0.018555                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate     0.018555                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate     0.018555                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 11346.244131                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 11346.244131                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 11346.244131                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst           40                       # number of ReadReq MSHR hits
+system.cpu3.icache.ReadReq_mshr_hits::total           40                       # number of ReadReq MSHR hits
+system.cpu3.icache.demand_mshr_hits::cpu3.inst           40                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.demand_mshr_hits::total           40                       # number of demand (read+write) MSHR hits
+system.cpu3.icache.overall_mshr_hits::cpu3.inst           40                       # number of overall MSHR hits
+system.cpu3.icache.overall_mshr_hits::total           40                       # number of overall MSHR hits
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          426                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          426                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          426                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          426                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          426                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          426                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4833500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      4833500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4833500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      4833500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4833500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      4833500                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.018555                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.018555                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.018555                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11346.244131                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11346.244131                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11346.244131                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     2                       # number of replacements
-system.cpu3.dcache.tagsinuse                13.455705                       # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse                23.407477                       # Cycle average of tags in use
 system.cpu3.dcache.total_refs                   33584                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
 system.cpu3.dcache.avg_refs               1158.068966                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::0            23.407477                       # Average occupied blocks per context
-system.cpu3.dcache.occ_blocks::1            -9.951772                       # Average occupied blocks per context
-system.cpu3.dcache.occ_percent::0            0.045718                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::1           -0.019437                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits                 38412                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits                27537                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits                    14                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits                  65949                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits                 65949                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses                 448                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses                125                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses                  56                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses                  573                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses                 573                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency       9358000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency      2911000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency       1350500                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency       12269000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency      12269000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses             38860                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses            27662                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses              66522                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses             66522                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate         0.011529                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate        0.004519                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate         0.800000                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate          0.008614                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate         0.008614                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency 20888.392857                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency        23288                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency 24116.071429                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency 21411.867365                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency 21411.867365                       # average overall miss latency
+system.cpu3.dcache.occ_blocks::cpu3.data    23.407477                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.045718                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.045718                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data        38412                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          38412                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        27537                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         27537                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           14                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        65949                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           65949                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        65949                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          65949                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          448                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          448                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          125                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          125                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           56                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           56                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          573                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           573                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          573                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          573                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      9358000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      9358000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2911000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      2911000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data      1350500                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total      1350500                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data     12269000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total     12269000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data     12269000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total     12269000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        38860                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        38860                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        27662                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        27662                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        66522                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        66522                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        66522                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        66522                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.011529                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.004519                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.800000                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.008614                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.008614                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 20888.392857                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data        23288                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 24116.071429                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 21411.867365                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 21411.867365                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -1578,36 +1762,46 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks                       1                       # number of writebacks
-system.cpu3.dcache.ReadReq_mshr_hits              279                       # number of ReadReq MSHR hits
-system.cpu3.dcache.WriteReq_mshr_hits              17                       # number of WriteReq MSHR hits
-system.cpu3.dcache.demand_mshr_hits               296                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits              296                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses            169                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses           108                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses             56                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses             277                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses            277                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency      2218000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency      1624500                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency      1182500                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency      3842500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency      3842500                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate     0.004349                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate     0.003904                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate     0.800000                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate     0.004164                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate     0.004164                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13124.260355                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 15041.666667                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency 21116.071429                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 13871.841155                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 13871.841155                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu3.dcache.writebacks::total                1                       # number of writebacks
+system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data          279                       # number of ReadReq MSHR hits
+system.cpu3.dcache.ReadReq_mshr_hits::total          279                       # number of ReadReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data           17                       # number of WriteReq MSHR hits
+system.cpu3.dcache.WriteReq_mshr_hits::total           17                       # number of WriteReq MSHR hits
+system.cpu3.dcache.demand_mshr_hits::cpu3.data          296                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.demand_mshr_hits::total          296                       # number of demand (read+write) MSHR hits
+system.cpu3.dcache.overall_mshr_hits::cpu3.data          296                       # number of overall MSHR hits
+system.cpu3.dcache.overall_mshr_hits::total          296                       # number of overall MSHR hits
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          169                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          169                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           56                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          277                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          277                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          277                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          277                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2218000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2218000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1624500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1624500                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data      1182500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total      1182500                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3842500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      3842500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3842500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      3842500                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.004349                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.003904                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.800000                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004164                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004164                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13124.260355                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 15041.666667                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 21116.071429                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 13871.841155                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 13871.841155                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
 system.l2c.tagsinuse                       428.231635                       # Cycle average of tags in use
@@ -1615,142 +1809,231 @@ system.l2c.total_refs                            1446                       # To
 system.l2c.sampled_refs                           527                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.743833                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                   347.174574                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    11.269547                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                    63.254631                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                     1.567259                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                     4.965624                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.005297                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.000172                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.000965                       # Average percentage of cache occupancy
-system.l2c.occ_percent::3                    0.000024                       # Average percentage of cache occupancy
-system.l2c.occ_percent::4                    0.000076                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                        233                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                        424                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                        356                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                        436                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks            4.965624                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           287.776309                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            59.398265                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            10.494682                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             0.774865                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst            57.571117                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             5.683514                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             0.828706                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.738553                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.000076                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.004391                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.000906                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.000160                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.000012                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.000878                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data            0.000087                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.inst            0.000013                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.data            0.000011                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.006534                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                228                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                412                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data                 12                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                349                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data                  7                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst                424                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data                 12                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                   1449                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks               9                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                       3                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data               3                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   3                       # number of UpgradeReq hits
-system.l2c.demand_hits::0                         233                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                         424                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                         356                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                         436                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 228                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 412                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                  12                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 349                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   7                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 424                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                  12                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                    1449                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                        233                       # number of overall hits
-system.l2c.overall_hits::1                        424                       # number of overall hits
-system.l2c.overall_hits::2                        356                       # number of overall hits
-system.l2c.overall_hits::3                        436                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst                228                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                412                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                 12                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                349                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  7                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                424                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                 12                       # number of overall hits
 system.l2c.overall_hits::total                   1449                       # number of overall hits
-system.l2c.ReadReq_misses::0                      429                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       16                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                       85                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                        3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst              354                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data               75                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst               15                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data                1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst               78                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data                7                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                  533                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                    21                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                    22                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                    22                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                    22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data            21                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            22                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            22                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                     94                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                     12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2                     13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data             94                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data             12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data             13                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                131                       # number of ReadExReq misses
-system.l2c.demand_misses::0                       523                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        28                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                        98                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                        15                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst               354                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               169                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                15                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                78                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data                20                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                   664                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                      523                       # number of overall misses
-system.l2c.overall_misses::1                       28                       # number of overall misses
-system.l2c.overall_misses::2                       98                       # number of overall misses
-system.l2c.overall_misses::3                       15                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst              354                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              169                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               15                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               13                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst               78                       # number of overall misses
+system.l2c.overall_misses::cpu2.data               20                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
+system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
 system.l2c.overall_misses::total                  664                       # number of overall misses
-system.l2c.ReadReq_miss_latency              27701000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency             157500                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency             6878000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency               34579000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency              34579000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                    662                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                    440                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                    441                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3                    439                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0.inst     18441500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data      3931500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst       745000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data        52500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst      4016500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data       365500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst        96000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.data        52500                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total       27701000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data        52500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data        52500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data        52500                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       157500                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      4940000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data       627500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       683000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       627500                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      6878000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     18441500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data      8871500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst       745000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data       680000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst      4016500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data      1048500                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst        96000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       680000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        34579000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     18441500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data      8871500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst       745000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data       680000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst      4016500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data      1048500                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst        96000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       680000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       34579000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst            582                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data             80                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst            427                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data             13                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst            427                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data             14                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            426                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data             13                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total               1982                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks            9                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  24                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                  22                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2                  22                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3                  22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           24                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           22                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           22                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              90                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0                   94                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                   12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2                   13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data           94                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data           12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data           13                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              131                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                     756                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                     452                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                     454                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::3                     451                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst             582                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             174                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             427                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             427                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data              27                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             426                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data              25                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total                2113                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                    756                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                    452                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                    454                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::3                    451                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            582                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            174                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            427                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            427                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data             27                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            426                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data             25                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               2113                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.648036                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.036364                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.192744                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.006834                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.883977                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.875000                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       3.875000                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.691799                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.061947                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.215859                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.033259                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           1.002864                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.691799                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.061947                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.215859                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.033259                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          1.002864                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   64571.095571                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   1731312.500000                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   325894.117647                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3   9233666.666667                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 11355444.379885                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0         7500                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1  7159.090909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2  7159.090909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3  7159.090909                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 28977.272727                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 73170.212766                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 573166.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 529076.923077                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 573166.666667                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 1748580.469176                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    66116.634799                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    1234964.285714                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    352846.938776                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3    2305266.666667                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3959194.525956                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   66116.634799                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   1234964.285714                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   352846.938776                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3   2305266.666667                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3959194.525956                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.608247                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.937500                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.035129                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.076923                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.182670                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.500000                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.004695                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data      0.076923                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.875000                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.608247                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.971264                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.035129                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.520000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.182670                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.740741                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.004695                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.520000                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.608247                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.971264                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.035129                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.520000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.182670                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.740741                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.004695                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.520000                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52094.632768                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data        52420                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49666.666667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data        52500                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst 51493.589744                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data 52214.285714                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst        48000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.data        52500                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  2386.363636                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data  2386.363636                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data  2386.363636                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data 52553.191489                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52291.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52538.461538                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data 52291.666667                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52094.632768                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data 52494.082840                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 49666.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 52307.692308                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst 51493.589744                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data        52425                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst        48000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 52307.692308                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52094.632768                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data 52494.082840                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 49666.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 52307.692308                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst 51493.589744                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data        52425                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst        48000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 52307.692308                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -1759,55 +2042,159 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                               0                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                        8                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                         8                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        8                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                    525                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                  87                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses                  131                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                     656                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                    656                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency         20993500                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency       3480000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency        5279000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency          26272500                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency         26272500                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.793051                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         1.193182                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         1.190476                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3         1.195900                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     4.372609                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      3.625000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      3.954545                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2      3.954545                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3      3.954545                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total    15.488636                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       1.393617                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1      10.916667                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2      10.076923                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3      10.916667                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total    33.303873                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.867725                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.451327                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          1.444934                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3          1.454545                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      5.218532                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.867725                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.451327                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         1.444934                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3         1.454545                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     5.218532                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 39987.619048                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40297.709924                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40049.542683                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40049.542683                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.ReadReq_mshr_hits::cpu0.inst             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.inst             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.inst             5                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.inst             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                 8                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              5                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                  8                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             5                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                 8                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst          353                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data           75                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst           14                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst           73                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data            7                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total             525                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data           21                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           22                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           22                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           22                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           87                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data           94                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data           12                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data           13                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data           12                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total           131                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          353                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data          169                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           14                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data           13                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst           73                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data           20                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data           13                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total              656                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          353                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data          169                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           14                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data           13                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst           73                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data           20                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data           13                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total             656                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     14091500                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data      3019000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst       561000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst      2922000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data       280000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     20993500                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data       840000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      3480000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3792000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       481000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       524500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       481500                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      5279000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     14091500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data      6811000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst       561000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data       521000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst      2922000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data       804500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst        40000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       521500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     26272500                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     14091500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data      6811000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst       561000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data       521000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst      2922000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data       804500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst        40000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       521500                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     26272500                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.606529                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.937500                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.032787                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.076923                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.170960                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.500000                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002347                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.076923                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.875000                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.606529                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.032787                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.520000                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.170960                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.740741                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002347                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.520000                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.606529                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.971264                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.032787                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.520000                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.170960                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.740741                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002347                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.520000                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39919.263456                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40253.333333                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40071.428571                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40027.397260                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40340.425532                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40083.333333                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40346.153846                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40125                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39919.263456                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40301.775148                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40071.428571                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40076.923077                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40027.397260                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data        40225                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39919.263456                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40301.775148                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40071.428571                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40027.397260                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data        40225                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40115.384615                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index 65fcae2f7952166824116d9422ac891bae0174cb..90b4c4184b7d01d791693cf10198afd560cfd257 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=atomic
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[2]
 
 [system.cpu0]
 type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu0.interrupts
 itb=system.cpu0.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -61,20 +71,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -97,20 +100,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -118,6 +114,9 @@ write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.port[1]
 
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
 [system.cpu0.itb]
 type=SparcTLB
 size=64
@@ -146,16 +145,18 @@ uid=100
 
 [system.cpu1]
 type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu1.interrupts
 itb=system.cpu1.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -163,6 +164,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -184,20 +186,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -220,20 +215,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -241,6 +229,9 @@ write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.port[3]
 
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
 [system.cpu1.itb]
 type=SparcTLB
 size=64
@@ -250,16 +241,18 @@ type=ExeTracer
 
 [system.cpu2]
 type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 checker=Null
 clock=500
 cpu_id=2
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu2.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu2.interrupts
 itb=system.cpu2.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -267,6 +260,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -288,20 +282,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -324,20 +311,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -345,6 +325,9 @@ write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.port[5]
 
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
 [system.cpu2.itb]
 type=SparcTLB
 size=64
@@ -354,16 +337,18 @@ type=ExeTracer
 
 [system.cpu3]
 type=AtomicSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 checker=Null
 clock=500
 cpu_id=3
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu3.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu3.interrupts
 itb=system.cpu3.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -371,6 +356,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 simulate_data_stalls=false
 simulate_inst_stalls=false
@@ -392,20 +378,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -428,20 +407,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -449,6 +421,9 @@ write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.port[7]
 
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
 [system.cpu3.itb]
 type=SparcTLB
 size=64
@@ -467,20 +442,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
index 8daa6c89421b0d5329c6f4fd049a8590a21a0e9d..4d44fa6f6c8381fc4891fadcecce7696c4e947d2 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:32
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:55:56
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
index 0cc0a830c617a5521fe5a389f0c99d4bc8870178..71dd904a3db770771edfa9a94ceb09938ec9be6b 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87713500                       # Number of ticks simulated
 final_tick                                   87713500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1650324                       # Simulator instruction rate (inst/s)
-host_tick_rate                              213702670                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1140448                       # Number of bytes of host memory used
+host_inst_rate                                1664146                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1664073                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              215483439                       # Simulator tick rate (ticks/s)
+host_mem_usage                                1139232                       # Number of bytes of host memory used
 host_seconds                                     0.41                       # Real time elapsed on the host
 sim_insts                                      677340                       # Number of instructions simulated
+sim_ops                                        677340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       35776                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  22272                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls                  89                       # Nu
 system.cpu0.numCycles                          175428                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.num_insts                          175339                       # Number of instructions executed
+system.cpu0.committedInsts                     175339                       # Number of instructions committed
+system.cpu0.committedOps                       175339                       # Number of ops (including micro ops) committed
 system.cpu0.num_int_alu_accesses               120388                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
@@ -46,24 +49,30 @@ system.cpu0.icache.total_refs                  174934                       # To
 system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                374.591006                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           222.757301                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.435073                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits                174934                       # number of ReadReq hits
-system.cpu0.icache.demand_hits                 174934                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits                174934                       # number of overall hits
-system.cpu0.icache.ReadReq_misses                 467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses                  467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses                 467                       # number of overall misses
-system.cpu0.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses            175401                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses             175401                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses            175401                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate         0.002662                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate          0.002662                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate         0.002662                       # miss rate for overall accesses
-system.cpu0.icache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst   222.757301                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.435073                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.435073                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst       174934                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         174934                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       174934                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          174934                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       174934                       # number of overall hits
+system.cpu0.icache.overall_hits::total         174934                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
+system.cpu0.icache.overall_misses::total          467                       # number of overall misses
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       175401                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       175401                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       175401                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       175401                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       175401                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       175401                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002662                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002662                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002662                       # miss rate for overall accesses
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -72,22 +81,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu0.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     9                       # number of replacements
 system.cpu0.dcache.tagsinuse               145.712770                       # Cycle average of tags in use
@@ -95,32 +88,44 @@ system.cpu0.dcache.total_refs                   61599                       # To
 system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                362.347059                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           145.712770                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.284595                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits                 54431                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits                27578                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits                    15                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits                  82009                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits                 82009                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses                 151                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses                177                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses                  27                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses                  328                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses                 328                       # number of overall misses
-system.cpu0.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses             54582                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses            27755                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses              82337                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses             82337                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate         0.002766                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate        0.006377                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate         0.642857                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate          0.003984                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate         0.003984                       # miss rate for overall accesses
-system.cpu0.dcache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data   145.712770                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.284595                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.284595                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        54431                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          54431                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        27578                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         27578                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           15                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data        82009                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           82009                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        82009                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          82009                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          151                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          151                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          177                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          177                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           27                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           27                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data          328                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total           328                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data          328                       # number of overall misses
+system.cpu0.dcache.overall_misses::total          328                       # number of overall misses
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        54582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        54582                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        27755                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        27755                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data        82337                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        82337                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        82337                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        82337                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.002766                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.006377                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.642857                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.003984                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.003984                       # miss rate for overall accesses
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -129,27 +134,14 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                       6                       # number of writebacks
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu0.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
+system.cpu0.dcache.writebacks::total                6                       # number of writebacks
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                          173308                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.num_insts                          167398                       # Number of instructions executed
+system.cpu1.committedInsts                     167398                       # Number of instructions committed
+system.cpu1.committedOps                       167398                       # Number of ops (including micro ops) committed
 system.cpu1.num_int_alu_accesses               109926                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                        633                       # number of times a function call or return occured
@@ -173,24 +165,30 @@ system.cpu1.icache.total_refs                  167072                       # To
 system.cpu1.icache.sampled_refs                   358                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                466.681564                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0            76.746014                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.149895                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits                167072                       # number of ReadReq hits
-system.cpu1.icache.demand_hits                 167072                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits                167072                       # number of overall hits
-system.cpu1.icache.ReadReq_misses                 358                       # number of ReadReq misses
-system.cpu1.icache.demand_misses                  358                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses                 358                       # number of overall misses
-system.cpu1.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses            167430                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses             167430                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses            167430                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate         0.002138                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate          0.002138                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate         0.002138                       # miss rate for overall accesses
-system.cpu1.icache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.icache.occ_blocks::cpu1.inst    76.746014                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.149895                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.149895                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst       167072                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         167072                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       167072                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          167072                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       167072                       # number of overall hits
+system.cpu1.icache.overall_hits::total         167072                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          358                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          358                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          358                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           358                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          358                       # number of overall misses
+system.cpu1.icache.overall_misses::total          358                       # number of overall misses
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       167430                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       167430                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       167430                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       167430                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       167430                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       167430                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002138                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002138                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002138                       # miss rate for overall accesses
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -199,22 +197,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                       0                       # number of writebacks
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu1.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     2                       # number of replacements
 system.cpu1.dcache.tagsinuse                29.073016                       # Cycle average of tags in use
@@ -222,32 +204,44 @@ system.cpu1.dcache.total_refs                   26889                       # To
 system.cpu1.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                960.321429                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0            29.073016                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.056783                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits                 40468                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits                12563                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits                    14                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits                  53031                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits                 53031                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses                 176                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses                106                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses                  57                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses                  282                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses                 282                       # number of overall misses
-system.cpu1.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses             40644                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses            12669                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses                71                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses              53313                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses             53313                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate         0.004330                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate        0.008367                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate         0.802817                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate          0.005290                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate         0.005290                       # miss rate for overall accesses
-system.cpu1.dcache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::cpu1.data    29.073016                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.056783                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.056783                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data        40468                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          40468                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data        12563                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total         12563                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           14                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             14                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        53031                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           53031                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        53031                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          53031                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          176                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          176                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data          106                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total          106                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           57                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           57                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          282                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           282                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          282                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          282                       # number of overall misses
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        40644                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        40644                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data        12669                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total        12669                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           71                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        53313                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        53313                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        53313                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        53313                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004330                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.008367                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.802817                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005290                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005290                       # miss rate for overall accesses
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -256,27 +250,14 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                       1                       # number of writebacks
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu1.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu1.dcache.writebacks::total                1                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.numCycles                          173308                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.num_insts                          167334                       # Number of instructions executed
+system.cpu2.committedInsts                     167334                       # Number of instructions committed
+system.cpu2.committedOps                       167334                       # Number of ops (including micro ops) committed
 system.cpu2.num_int_alu_accesses               113333                       # Number of integer alu accesses
 system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu2.num_func_calls                        633                       # number of times a function call or return occured
@@ -300,24 +281,30 @@ system.cpu2.icache.total_refs                  167008                       # To
 system.cpu2.icache.sampled_refs                   358                       # Sample count of references to valid blocks.
 system.cpu2.icache.avg_refs                466.502793                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::0            74.775474                       # Average occupied blocks per context
-system.cpu2.icache.occ_percent::0            0.146046                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits                167008                       # number of ReadReq hits
-system.cpu2.icache.demand_hits                 167008                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits                167008                       # number of overall hits
-system.cpu2.icache.ReadReq_misses                 358                       # number of ReadReq misses
-system.cpu2.icache.demand_misses                  358                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses                 358                       # number of overall misses
-system.cpu2.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses            167366                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses             167366                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses            167366                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate         0.002139                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate          0.002139                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate         0.002139                       # miss rate for overall accesses
-system.cpu2.icache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst    74.775474                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.146046                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.146046                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst       167008                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         167008                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       167008                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          167008                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       167008                       # number of overall hits
+system.cpu2.icache.overall_hits::total         167008                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          358                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          358                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          358                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           358                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          358                       # number of overall misses
+system.cpu2.icache.overall_misses::total          358                       # number of overall misses
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       167366                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       167366                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       167366                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       167366                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       167366                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       167366                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002139                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002139                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002139                       # miss rate for overall accesses
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -326,22 +313,6 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.writebacks                       0                       # number of writebacks
-system.cpu2.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu2.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu2.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     2                       # number of replacements
 system.cpu2.dcache.tagsinuse                28.420699                       # Cycle average of tags in use
@@ -349,32 +320,44 @@ system.cpu2.dcache.total_refs                   33771                       # To
 system.cpu2.dcache.sampled_refs                    28                       # Sample count of references to valid blocks.
 system.cpu2.dcache.avg_refs               1206.107143                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::0            28.420699                       # Average occupied blocks per context
-system.cpu2.dcache.occ_percent::0            0.055509                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits                 42192                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits                15998                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits                    11                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits                  58190                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits                 58190                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses                 162                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses                109                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses                  55                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses                  271                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses                 271                       # number of overall misses
-system.cpu2.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses             42354                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses            16107                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses                66                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses              58461                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses             58461                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate         0.003825                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate        0.006767                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate         0.833333                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate          0.004636                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate         0.004636                       # miss rate for overall accesses
-system.cpu2.dcache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu2.dcache.occ_blocks::cpu2.data    28.420699                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.055509                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.055509                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data        42192                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          42192                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        15998                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         15998                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           11                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        58190                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           58190                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        58190                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          58190                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          162                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          109                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           55                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          271                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           271                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          271                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          271                       # number of overall misses
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        42354                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        42354                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        16107                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        16107                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           66                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           66                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        58461                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        58461                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        58461                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        58461                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003825                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006767                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.833333                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004636                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004636                       # miss rate for overall accesses
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -383,27 +366,14 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks                       1                       # number of writebacks
-system.cpu2.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu2.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu2.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu2.dcache.writebacks::total                1                       # number of writebacks
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.numCycles                          173307                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.num_insts                          167269                       # Number of instructions executed
+system.cpu3.committedInsts                     167269                       # Number of instructions committed
+system.cpu3.committedOps                       167269                       # Number of ops (including micro ops) committed
 system.cpu3.num_int_alu_accesses               111554                       # Number of integer alu accesses
 system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu3.num_func_calls                        633                       # number of times a function call or return occured
@@ -427,24 +397,30 @@ system.cpu3.icache.total_refs                  166942                       # To
 system.cpu3.icache.sampled_refs                   359                       # Sample count of references to valid blocks.
 system.cpu3.icache.avg_refs                465.019499                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::0            72.869097                       # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0            0.142322                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits                166942                       # number of ReadReq hits
-system.cpu3.icache.demand_hits                 166942                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits                166942                       # number of overall hits
-system.cpu3.icache.ReadReq_misses                 359                       # number of ReadReq misses
-system.cpu3.icache.demand_misses                  359                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses                 359                       # number of overall misses
-system.cpu3.icache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses            167301                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses             167301                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses            167301                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate         0.002146                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate          0.002146                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate         0.002146                       # miss rate for overall accesses
-system.cpu3.icache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.icache.occ_blocks::cpu3.inst    72.869097                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.142322                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.142322                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst       166942                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         166942                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       166942                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          166942                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       166942                       # number of overall hits
+system.cpu3.icache.overall_hits::total         166942                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          359                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          359                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          359                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           359                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          359                       # number of overall misses
+system.cpu3.icache.overall_misses::total          359                       # number of overall misses
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       167301                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       167301                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       167301                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       167301                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       167301                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       167301                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002146                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002146                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002146                       # miss rate for overall accesses
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -453,22 +429,6 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.writebacks                       0                       # number of writebacks
-system.cpu3.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu3.icache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.icache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.icache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu3.icache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     2                       # number of replacements
 system.cpu3.dcache.tagsinuse                27.588376                       # Cycle average of tags in use
@@ -476,32 +436,44 @@ system.cpu3.dcache.total_refs                   30309                       # To
 system.cpu3.dcache.sampled_refs                    29                       # Sample count of references to valid blocks.
 system.cpu3.dcache.avg_refs               1045.137931                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::0            27.588376                       # Average occupied blocks per context
-system.cpu3.dcache.occ_percent::0            0.053884                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits                 41299                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits                14260                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits                    15                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits                  55559                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits                 55559                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses                 159                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses                102                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses                  55                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses                  261                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses                 261                       # number of overall misses
-system.cpu3.dcache.demand_miss_latency              0                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency             0                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses             41458                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses            14362                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses                70                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses              55820                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses             55820                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate         0.003835                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate        0.007102                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate         0.785714                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate          0.004676                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate         0.004676                       # miss rate for overall accesses
-system.cpu3.dcache.demand_avg_miss_latency            0                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency            0                       # average overall miss latency
+system.cpu3.dcache.occ_blocks::cpu3.data    27.588376                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.053884                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.053884                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data        41299                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          41299                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        14260                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         14260                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           15                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             15                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        55559                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           55559                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        55559                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          55559                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          159                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          159                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          102                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          102                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           55                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           55                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          261                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           261                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          261                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          261                       # number of overall misses
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        41458                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        41458                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        14362                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        14362                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           70                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        55820                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        55820                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        55820                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        55820                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003835                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.007102                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.785714                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004676                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004676                       # miss rate for overall accesses
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -510,22 +482,8 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks                       1                       # number of writebacks
-system.cpu3.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu3.dcache.demand_mshr_misses               0                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses              0                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.dcache.demand_mshr_miss_latency            0                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency            0                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.demand_mshr_miss_rate            0                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate            0                       # mshr miss rate for overall accesses
-system.cpu3.dcache.demand_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu3.dcache.writebacks::total                1                       # number of writebacks
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
 system.l2c.tagsinuse                       371.980910                       # Cycle average of tags in use
@@ -533,124 +491,164 @@ system.l2c.total_refs                            1223                       # To
 system.l2c.sampled_refs                           426                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.870892                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                   294.613840                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    66.228089                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                     2.865859                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                     1.883074                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                     6.390048                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.004495                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.001011                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.000044                       # Average percentage of cache occupancy
-system.l2c.occ_percent::3                    0.000029                       # Average percentage of cache occupancy
-system.l2c.occ_percent::4                    0.000098                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                        190                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                        301                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                        367                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                        368                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks            6.390048                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           239.409595                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            55.204245                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            59.507442                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             6.720647                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             1.930518                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.935341                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             0.977501                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.905573                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.000098                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.003653                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.000842                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.000908                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.000103                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.000029                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data            0.000014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.inst            0.000015                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.data            0.000014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.005676                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                356                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst                357                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                   1226                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks               9                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                       2                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::0                         190                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                         301                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                         367                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                         368                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 356                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                    1226                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                        190                       # number of overall hits
-system.l2c.overall_hits::1                        301                       # number of overall hits
-system.l2c.overall_hits::2                        367                       # number of overall hits
-system.l2c.overall_hits::3                        368                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                356                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
 system.l2c.overall_hits::total                   1226                       # number of overall hits
-system.l2c.ReadReq_misses::0                      348                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       69                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                        3                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                        3                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst              282                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst               62                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst                2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                  423                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                    29                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                    19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                    20                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                    19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data            29                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            20                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            19                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                87                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                     99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                     13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2                     12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3                     12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
-system.l2c.demand_misses::0                       447                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        82                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                        15                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                        15                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                 2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                      447                       # number of overall misses
-system.l2c.overall_misses::1                       82                       # number of overall misses
-system.l2c.overall_misses::2                       15                       # number of overall misses
-system.l2c.overall_misses::3                       15                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst                2                       # number of overall misses
+system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
+system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
 system.l2c.overall_misses::total                  559                       # number of overall misses
-system.l2c.demand_miss_latency                      0                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency                     0                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                    538                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                    370                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                    370                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3                    371                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst            358                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data             12                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst            358                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data             12                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            359                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data             12                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total               1649                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks            9                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  31                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                  19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2                  20                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3                  19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           31                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           20                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           19                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              89                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                   13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2                   12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3                   12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                     637                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                     383                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                     382                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::3                     383                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              25                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data              24                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data              24                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total                1785                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                    637                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                    383                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                    382                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::3                    383                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             25                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data             24                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data             24                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               1785                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.646840                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.186486                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.008108                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.008086                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.849521                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.935484                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       3.935484                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.701727                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.214099                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.039267                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.039164                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.994258                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.701727                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.214099                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.039267                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.039164                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.994258                       # miss rate for overall accesses
-system.l2c.demand_avg_miss_latency::0               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3               0                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total            0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3              0                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total            0                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.603854                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.173184                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.583333                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.005587                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.083333                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.005571                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data      0.083333                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.935484                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.800000                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.005587                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.541667                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.005571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.541667                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.800000                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.005587                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.541667                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.005571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.541667                       # miss rate for overall accesses
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -659,30 +657,6 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                               0                       # number of writebacks
-system.l2c.demand_mshr_hits                         0                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                        0                       # number of overall MSHR hits
-system.l2c.demand_mshr_misses                       0                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                      0                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.demand_mshr_miss_latency                 0                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency                0                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.demand_mshr_miss_rate::0                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3                 0                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total             0                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3                0                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total            0                       # mshr miss rate for overall accesses
-system.l2c.demand_avg_mshr_miss_latency      no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency     no_value                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index ae7e021b510e00db27fa59ae0ac49328f51220e8..c00589f535a454d336fe9294cb5d3fb677e46c53 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -23,16 +30,18 @@ system_port=system.membus.port[1]
 
 [system.cpu0]
 type=TimingSimpleCPU
-children=dcache dtb icache itb tracer workload
+children=dcache dtb icache interrupts itb tracer workload
 checker=Null
 clock=500
 cpu_id=0
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu0.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu0.interrupts
 itb=system.cpu0.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -40,6 +49,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu0.tracer
@@ -58,20 +68,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -94,20 +97,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -115,6 +111,9 @@ write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.port[1]
 
+[system.cpu0.interrupts]
+type=SparcInterrupts
+
 [system.cpu0.itb]
 type=SparcTLB
 size=64
@@ -143,16 +142,18 @@ uid=100
 
 [system.cpu1]
 type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 checker=Null
 clock=500
 cpu_id=1
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu1.interrupts
 itb=system.cpu1.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -160,6 +161,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu1.tracer
@@ -178,20 +180,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -214,20 +209,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -235,6 +223,9 @@ write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.port[3]
 
+[system.cpu1.interrupts]
+type=SparcInterrupts
+
 [system.cpu1.itb]
 type=SparcTLB
 size=64
@@ -244,16 +235,18 @@ type=ExeTracer
 
 [system.cpu2]
 type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 checker=Null
 clock=500
 cpu_id=2
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu2.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu2.interrupts
 itb=system.cpu2.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -261,6 +254,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu2.tracer
@@ -279,20 +273,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -315,20 +302,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -336,6 +316,9 @@ write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.port[5]
 
+[system.cpu2.interrupts]
+type=SparcInterrupts
+
 [system.cpu2.itb]
 type=SparcTLB
 size=64
@@ -345,16 +328,18 @@ type=ExeTracer
 
 [system.cpu3]
 type=TimingSimpleCPU
-children=dcache dtb icache itb tracer
+children=dcache dtb icache interrupts itb tracer
 checker=Null
 clock=500
 cpu_id=3
 defer_registration=false
 do_checkpoint_insts=true
+do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu3.dtb
 function_trace=false
 function_trace_start=0
+interrupts=system.cpu3.interrupts
 itb=system.cpu3.itb
 max_insts_all_threads=0
 max_insts_any_thread=0
@@ -362,6 +347,7 @@ max_loads_all_threads=0
 max_loads_any_thread=0
 numThreads=1
 phase=0
+profile=0
 progress_interval=0
 system=system
 tracer=system.cpu3.tracer
@@ -380,20 +366,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -416,20 +395,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=4
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -437,6 +409,9 @@ write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.port[7]
 
+[system.cpu3.interrupts]
+type=SparcInterrupts
+
 [system.cpu3.itb]
 type=SparcTLB
 size=64
@@ -455,20 +430,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=4
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=4194304
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
index 6f90c0dd12b980288a341a068ec70bc0de1dab9a..bd048d4823bfa8a632475da346cbd422b23e5749 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:02:00
-gem5 started Jan 23 2012 04:24:33
+gem5 compiled Feb 11 2012 13:08:33
+gem5 started Feb 11 2012 13:56:07
 gem5 executing on zizzer
-command line: build/SPARC_SE/gem5.opt -d build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC_SE/tests/opt/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
+command line: build/SPARC/gem5.fast -d build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/fast/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
index 0ce3fe3af773ba49cbc5bf80771f2d456a0149b8..fcff65a90936a373b77dd128bc72a167a7ea07f0 100644 (file)
@@ -4,11 +4,13 @@ sim_seconds                                  0.000262                       # Nu
 sim_ticks                                   262298000                       # Number of ticks simulated
 final_tick                                  262298000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1158712                       # Simulator instruction rate (inst/s)
-host_tick_rate                              458877844                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 222944                       # Number of bytes of host memory used
-host_seconds                                     0.57                       # Real time elapsed on the host
+host_inst_rate                                1330969                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1330920                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              527074583                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 221728                       # Number of bytes of host memory used
+host_seconds                                     0.50                       # Real time elapsed on the host
 sim_insts                                      662307                       # Number of instructions simulated
+sim_ops                                        662307                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read                       36608                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                  22656                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
@@ -22,7 +24,8 @@ system.cpu0.workload.num_syscalls                  89                       # Nu
 system.cpu0.numCycles                          524596                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.num_insts                          158353                       # Number of instructions executed
+system.cpu0.committedInsts                     158353                       # Number of instructions committed
+system.cpu0.committedOps                       158353                       # Number of ops (including micro ops) committed
 system.cpu0.num_int_alu_accesses               109064                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                        390                       # number of times a function call or return occured
@@ -46,26 +49,39 @@ system.cpu0.icache.total_refs                  157949                       # To
 system.cpu0.icache.sampled_refs                   467                       # Sample count of references to valid blocks.
 system.cpu0.icache.avg_refs                338.220557                       # Average number of references to valid blocks.
 system.cpu0.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::0           212.479188                       # Average occupied blocks per context
-system.cpu0.icache.occ_percent::0            0.414998                       # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits                157949                       # number of ReadReq hits
-system.cpu0.icache.demand_hits                 157949                       # number of demand (read+write) hits
-system.cpu0.icache.overall_hits                157949                       # number of overall hits
-system.cpu0.icache.ReadReq_misses                 467                       # number of ReadReq misses
-system.cpu0.icache.demand_misses                  467                       # number of demand (read+write) misses
-system.cpu0.icache.overall_misses                 467                       # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency      18524000                       # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency       18524000                       # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency      18524000                       # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses            158416                       # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses             158416                       # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses            158416                       # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate         0.002948                       # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate          0.002948                       # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate         0.002948                       # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency 39665.952891                       # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency 39665.952891                       # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency 39665.952891                       # average overall miss latency
+system.cpu0.icache.occ_blocks::cpu0.inst   212.479188                       # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst     0.414998                       # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total        0.414998                       # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst       157949                       # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total         157949                       # number of ReadReq hits
+system.cpu0.icache.demand_hits::cpu0.inst       157949                       # number of demand (read+write) hits
+system.cpu0.icache.demand_hits::total          157949                       # number of demand (read+write) hits
+system.cpu0.icache.overall_hits::cpu0.inst       157949                       # number of overall hits
+system.cpu0.icache.overall_hits::total         157949                       # number of overall hits
+system.cpu0.icache.ReadReq_misses::cpu0.inst          467                       # number of ReadReq misses
+system.cpu0.icache.ReadReq_misses::total          467                       # number of ReadReq misses
+system.cpu0.icache.demand_misses::cpu0.inst          467                       # number of demand (read+write) misses
+system.cpu0.icache.demand_misses::total           467                       # number of demand (read+write) misses
+system.cpu0.icache.overall_misses::cpu0.inst          467                       # number of overall misses
+system.cpu0.icache.overall_misses::total          467                       # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst     18524000                       # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total     18524000                       # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst     18524000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total     18524000                       # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst     18524000                       # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total     18524000                       # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst       158416                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.ReadReq_accesses::total       158416                       # number of ReadReq accesses(hits+misses)
+system.cpu0.icache.demand_accesses::cpu0.inst       158416                       # number of demand (read+write) accesses
+system.cpu0.icache.demand_accesses::total       158416                       # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst       158416                       # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total       158416                       # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst     0.002948                       # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst     0.002948                       # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst     0.002948                       # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 39665.952891                       # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 39665.952891                       # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 39665.952891                       # average overall miss latency
 system.cpu0.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -74,26 +90,24 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.icache.writebacks                       0                       # number of writebacks
-system.cpu0.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.icache.ReadReq_mshr_misses            467                       # number of ReadReq MSHR misses
-system.cpu0.icache.demand_mshr_misses             467                       # number of demand (read+write) MSHR misses
-system.cpu0.icache.overall_mshr_misses            467                       # number of overall MSHR misses
-system.cpu0.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.icache.ReadReq_mshr_miss_latency     17123000                       # number of ReadReq MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency     17123000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.overall_mshr_miss_latency     17123000                       # number of overall MSHR miss cycles
-system.cpu0.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.icache.ReadReq_mshr_miss_rate     0.002948                       # mshr miss rate for ReadReq accesses
-system.cpu0.icache.demand_mshr_miss_rate     0.002948                       # mshr miss rate for demand accesses
-system.cpu0.icache.overall_mshr_miss_rate     0.002948                       # mshr miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_mshr_miss_latency 36665.952891                       # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency 36665.952891                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency 36665.952891                       # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst          467                       # number of ReadReq MSHR misses
+system.cpu0.icache.ReadReq_mshr_misses::total          467                       # number of ReadReq MSHR misses
+system.cpu0.icache.demand_mshr_misses::cpu0.inst          467                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.demand_mshr_misses::total          467                       # number of demand (read+write) MSHR misses
+system.cpu0.icache.overall_mshr_misses::cpu0.inst          467                       # number of overall MSHR misses
+system.cpu0.icache.overall_mshr_misses::total          467                       # number of overall MSHR misses
+system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst     17123000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_latency::total     17123000                       # number of ReadReq MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst     17123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.demand_mshr_miss_latency::total     17123000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst     17123000                       # number of overall MSHR miss cycles
+system.cpu0.icache.overall_mshr_miss_latency::total     17123000                       # number of overall MSHR miss cycles
+system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst     0.002948                       # mshr miss rate for ReadReq accesses
+system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst     0.002948                       # mshr miss rate for demand accesses
+system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst     0.002948                       # mshr miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36665.952891                       # average ReadReq mshr miss latency
+system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 36665.952891                       # average overall mshr miss latency
+system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 36665.952891                       # average overall mshr miss latency
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu0.dcache.replacements                     9                       # number of replacements
 system.cpu0.dcache.tagsinuse               141.233342                       # Cycle average of tags in use
@@ -101,38 +115,59 @@ system.cpu0.dcache.total_refs                   56009                       # To
 system.cpu0.dcache.sampled_refs                   170                       # Sample count of references to valid blocks.
 system.cpu0.dcache.avg_refs                329.464706                       # Average number of references to valid blocks.
 system.cpu0.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu0.dcache.occ_blocks::0           141.233342                       # Average occupied blocks per context
-system.cpu0.dcache.occ_percent::0            0.275846                       # Average percentage of cache occupancy
-system.cpu0.dcache.ReadReq_hits                 48758                       # number of ReadReq hits
-system.cpu0.dcache.WriteReq_hits                24741                       # number of WriteReq hits
-system.cpu0.dcache.SwapReq_hits                    16                       # number of SwapReq hits
-system.cpu0.dcache.demand_hits                  73499                       # number of demand (read+write) hits
-system.cpu0.dcache.overall_hits                 73499                       # number of overall hits
-system.cpu0.dcache.ReadReq_misses                 162                       # number of ReadReq misses
-system.cpu0.dcache.WriteReq_misses                183                       # number of WriteReq misses
-system.cpu0.dcache.SwapReq_misses                  26                       # number of SwapReq misses
-system.cpu0.dcache.demand_misses                  345                       # number of demand (read+write) misses
-system.cpu0.dcache.overall_misses                 345                       # number of overall misses
-system.cpu0.dcache.ReadReq_miss_latency       4749000                       # number of ReadReq miss cycles
-system.cpu0.dcache.WriteReq_miss_latency      7175000                       # number of WriteReq miss cycles
-system.cpu0.dcache.SwapReq_miss_latency        387000                       # number of SwapReq miss cycles
-system.cpu0.dcache.demand_miss_latency       11924000                       # number of demand (read+write) miss cycles
-system.cpu0.dcache.overall_miss_latency      11924000                       # number of overall miss cycles
-system.cpu0.dcache.ReadReq_accesses             48920                       # number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_accesses            24924                       # number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.SwapReq_accesses                42                       # number of SwapReq accesses(hits+misses)
-system.cpu0.dcache.demand_accesses              73844                       # number of demand (read+write) accesses
-system.cpu0.dcache.overall_accesses             73844                       # number of overall (read+write) accesses
-system.cpu0.dcache.ReadReq_miss_rate         0.003312                       # miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_miss_rate        0.007342                       # miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_miss_rate         0.619048                       # miss rate for SwapReq accesses
-system.cpu0.dcache.demand_miss_rate          0.004672                       # miss rate for demand accesses
-system.cpu0.dcache.overall_miss_rate         0.004672                       # miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_miss_latency 29314.814815                       # average ReadReq miss latency
-system.cpu0.dcache.WriteReq_avg_miss_latency 39207.650273                       # average WriteReq miss latency
-system.cpu0.dcache.SwapReq_avg_miss_latency 14884.615385                       # average SwapReq miss latency
-system.cpu0.dcache.demand_avg_miss_latency 34562.318841                       # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency 34562.318841                       # average overall miss latency
+system.cpu0.dcache.occ_blocks::cpu0.data   141.233342                       # Average occupied blocks per requestor
+system.cpu0.dcache.occ_percent::cpu0.data     0.275846                       # Average percentage of cache occupancy
+system.cpu0.dcache.occ_percent::total        0.275846                       # Average percentage of cache occupancy
+system.cpu0.dcache.ReadReq_hits::cpu0.data        48758                       # number of ReadReq hits
+system.cpu0.dcache.ReadReq_hits::total          48758                       # number of ReadReq hits
+system.cpu0.dcache.WriteReq_hits::cpu0.data        24741                       # number of WriteReq hits
+system.cpu0.dcache.WriteReq_hits::total         24741                       # number of WriteReq hits
+system.cpu0.dcache.SwapReq_hits::cpu0.data           16                       # number of SwapReq hits
+system.cpu0.dcache.SwapReq_hits::total             16                       # number of SwapReq hits
+system.cpu0.dcache.demand_hits::cpu0.data        73499                       # number of demand (read+write) hits
+system.cpu0.dcache.demand_hits::total           73499                       # number of demand (read+write) hits
+system.cpu0.dcache.overall_hits::cpu0.data        73499                       # number of overall hits
+system.cpu0.dcache.overall_hits::total          73499                       # number of overall hits
+system.cpu0.dcache.ReadReq_misses::cpu0.data          162                       # number of ReadReq misses
+system.cpu0.dcache.ReadReq_misses::total          162                       # number of ReadReq misses
+system.cpu0.dcache.WriteReq_misses::cpu0.data          183                       # number of WriteReq misses
+system.cpu0.dcache.WriteReq_misses::total          183                       # number of WriteReq misses
+system.cpu0.dcache.SwapReq_misses::cpu0.data           26                       # number of SwapReq misses
+system.cpu0.dcache.SwapReq_misses::total           26                       # number of SwapReq misses
+system.cpu0.dcache.demand_misses::cpu0.data          345                       # number of demand (read+write) misses
+system.cpu0.dcache.demand_misses::total           345                       # number of demand (read+write) misses
+system.cpu0.dcache.overall_misses::cpu0.data          345                       # number of overall misses
+system.cpu0.dcache.overall_misses::total          345                       # number of overall misses
+system.cpu0.dcache.ReadReq_miss_latency::cpu0.data      4749000                       # number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_latency::total      4749000                       # number of ReadReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::cpu0.data      7175000                       # number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_latency::total      7175000                       # number of WriteReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::cpu0.data       387000                       # number of SwapReq miss cycles
+system.cpu0.dcache.SwapReq_miss_latency::total       387000                       # number of SwapReq miss cycles
+system.cpu0.dcache.demand_miss_latency::cpu0.data     11924000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_latency::total     11924000                       # number of demand (read+write) miss cycles
+system.cpu0.dcache.overall_miss_latency::cpu0.data     11924000                       # number of overall miss cycles
+system.cpu0.dcache.overall_miss_latency::total     11924000                       # number of overall miss cycles
+system.cpu0.dcache.ReadReq_accesses::cpu0.data        48920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_accesses::total        48920                       # number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::cpu0.data        24924                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_accesses::total        24924                       # number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::cpu0.data           42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.SwapReq_accesses::total           42                       # number of SwapReq accesses(hits+misses)
+system.cpu0.dcache.demand_accesses::cpu0.data        73844                       # number of demand (read+write) accesses
+system.cpu0.dcache.demand_accesses::total        73844                       # number of demand (read+write) accesses
+system.cpu0.dcache.overall_accesses::cpu0.data        73844                       # number of overall (read+write) accesses
+system.cpu0.dcache.overall_accesses::total        73844                       # number of overall (read+write) accesses
+system.cpu0.dcache.ReadReq_miss_rate::cpu0.data     0.003312                       # miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_miss_rate::cpu0.data     0.007342                       # miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_miss_rate::cpu0.data     0.619048                       # miss rate for SwapReq accesses
+system.cpu0.dcache.demand_miss_rate::cpu0.data     0.004672                       # miss rate for demand accesses
+system.cpu0.dcache.overall_miss_rate::cpu0.data     0.004672                       # miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 29314.814815                       # average ReadReq miss latency
+system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 39207.650273                       # average WriteReq miss latency
+system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 14884.615385                       # average SwapReq miss latency
+system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 34562.318841                       # average overall miss latency
+system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 34562.318841                       # average overall miss latency
 system.cpu0.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -141,39 +176,44 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu0.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu0.dcache.writebacks                       6                       # number of writebacks
-system.cpu0.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu0.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu0.dcache.ReadReq_mshr_misses            162                       # number of ReadReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_misses           183                       # number of WriteReq MSHR misses
-system.cpu0.dcache.SwapReq_mshr_misses             26                       # number of SwapReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses             345                       # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses            345                       # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency      4263000                       # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency      6626000                       # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.SwapReq_mshr_miss_latency       309000                       # number of SwapReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency     10889000                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency     10889000                       # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate     0.003312                       # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate     0.007342                       # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.SwapReq_mshr_miss_rate     0.619048                       # mshr miss rate for SwapReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate     0.004672                       # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate     0.004672                       # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 26314.814815                       # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 36207.650273                       # average WriteReq mshr miss latency
-system.cpu0.dcache.SwapReq_avg_mshr_miss_latency 11884.615385                       # average SwapReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 31562.318841                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 31562.318841                       # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu0.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu0.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.dcache.writebacks::writebacks            6                       # number of writebacks
+system.cpu0.dcache.writebacks::total                6                       # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data          162                       # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total          162                       # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data          183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total          183                       # number of WriteReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data           26                       # number of SwapReq MSHR misses
+system.cpu0.dcache.SwapReq_mshr_misses::total           26                       # number of SwapReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data          345                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total          345                       # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data          345                       # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total          345                       # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data      4263000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total      4263000                       # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data      6626000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total      6626000                       # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data       309000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.SwapReq_mshr_miss_latency::total       309000                       # number of SwapReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data     10889000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total     10889000                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data     10889000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total     10889000                       # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data     0.003312                       # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data     0.007342                       # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data     0.619048                       # mshr miss rate for SwapReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data     0.004672                       # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data     0.004672                       # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 26314.814815                       # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 36207.650273                       # average WriteReq mshr miss latency
+system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 11884.615385                       # average SwapReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 31562.318841                       # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 31562.318841                       # average overall mshr miss latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.numCycles                          524596                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.num_insts                          172325                       # Number of instructions executed
+system.cpu1.committedInsts                     172325                       # Number of instructions committed
+system.cpu1.committedOps                       172325                       # Number of ops (including micro ops) committed
 system.cpu1.num_int_alu_accesses               107932                       # Number of integer alu accesses
 system.cpu1.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu1.num_func_calls                        637                       # number of times a function call or return occured
@@ -197,26 +237,39 @@ system.cpu1.icache.total_refs                  171992                       # To
 system.cpu1.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
 system.cpu1.icache.avg_refs                469.923497                       # Average number of references to valid blocks.
 system.cpu1.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::0            70.076133                       # Average occupied blocks per context
-system.cpu1.icache.occ_percent::0            0.136867                       # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits                171992                       # number of ReadReq hits
-system.cpu1.icache.demand_hits                 171992                       # number of demand (read+write) hits
-system.cpu1.icache.overall_hits                171992                       # number of overall hits
-system.cpu1.icache.ReadReq_misses                 366                       # number of ReadReq misses
-system.cpu1.icache.demand_misses                  366                       # number of demand (read+write) misses
-system.cpu1.icache.overall_misses                 366                       # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency       7920500                       # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency        7920500                       # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency       7920500                       # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses            172358                       # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.demand_accesses             172358                       # number of demand (read+write) accesses
-system.cpu1.icache.overall_accesses            172358                       # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate         0.002123                       # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate          0.002123                       # miss rate for demand accesses
-system.cpu1.icache.overall_miss_rate         0.002123                       # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency 21640.710383                       # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency 21640.710383                       # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency 21640.710383                       # average overall miss latency
+system.cpu1.icache.occ_blocks::cpu1.inst    70.076133                       # Average occupied blocks per requestor
+system.cpu1.icache.occ_percent::cpu1.inst     0.136867                       # Average percentage of cache occupancy
+system.cpu1.icache.occ_percent::total        0.136867                       # Average percentage of cache occupancy
+system.cpu1.icache.ReadReq_hits::cpu1.inst       171992                       # number of ReadReq hits
+system.cpu1.icache.ReadReq_hits::total         171992                       # number of ReadReq hits
+system.cpu1.icache.demand_hits::cpu1.inst       171992                       # number of demand (read+write) hits
+system.cpu1.icache.demand_hits::total          171992                       # number of demand (read+write) hits
+system.cpu1.icache.overall_hits::cpu1.inst       171992                       # number of overall hits
+system.cpu1.icache.overall_hits::total         171992                       # number of overall hits
+system.cpu1.icache.ReadReq_misses::cpu1.inst          366                       # number of ReadReq misses
+system.cpu1.icache.ReadReq_misses::total          366                       # number of ReadReq misses
+system.cpu1.icache.demand_misses::cpu1.inst          366                       # number of demand (read+write) misses
+system.cpu1.icache.demand_misses::total           366                       # number of demand (read+write) misses
+system.cpu1.icache.overall_misses::cpu1.inst          366                       # number of overall misses
+system.cpu1.icache.overall_misses::total          366                       # number of overall misses
+system.cpu1.icache.ReadReq_miss_latency::cpu1.inst      7920500                       # number of ReadReq miss cycles
+system.cpu1.icache.ReadReq_miss_latency::total      7920500                       # number of ReadReq miss cycles
+system.cpu1.icache.demand_miss_latency::cpu1.inst      7920500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.demand_miss_latency::total      7920500                       # number of demand (read+write) miss cycles
+system.cpu1.icache.overall_miss_latency::cpu1.inst      7920500                       # number of overall miss cycles
+system.cpu1.icache.overall_miss_latency::total      7920500                       # number of overall miss cycles
+system.cpu1.icache.ReadReq_accesses::cpu1.inst       172358                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.ReadReq_accesses::total       172358                       # number of ReadReq accesses(hits+misses)
+system.cpu1.icache.demand_accesses::cpu1.inst       172358                       # number of demand (read+write) accesses
+system.cpu1.icache.demand_accesses::total       172358                       # number of demand (read+write) accesses
+system.cpu1.icache.overall_accesses::cpu1.inst       172358                       # number of overall (read+write) accesses
+system.cpu1.icache.overall_accesses::total       172358                       # number of overall (read+write) accesses
+system.cpu1.icache.ReadReq_miss_rate::cpu1.inst     0.002123                       # miss rate for ReadReq accesses
+system.cpu1.icache.demand_miss_rate::cpu1.inst     0.002123                       # miss rate for demand accesses
+system.cpu1.icache.overall_miss_rate::cpu1.inst     0.002123                       # miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21640.710383                       # average ReadReq miss latency
+system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21640.710383                       # average overall miss latency
+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21640.710383                       # average overall miss latency
 system.cpu1.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -225,67 +278,84 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.icache.writebacks                       0                       # number of writebacks
-system.cpu1.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.icache.ReadReq_mshr_misses            366                       # number of ReadReq MSHR misses
-system.cpu1.icache.demand_mshr_misses             366                       # number of demand (read+write) MSHR misses
-system.cpu1.icache.overall_mshr_misses            366                       # number of overall MSHR misses
-system.cpu1.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.icache.ReadReq_mshr_miss_latency      6822000                       # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency      6822000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency      6822000                       # number of overall MSHR miss cycles
-system.cpu1.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.icache.ReadReq_mshr_miss_rate     0.002123                       # mshr miss rate for ReadReq accesses
-system.cpu1.icache.demand_mshr_miss_rate     0.002123                       # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate     0.002123                       # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency 18639.344262                       # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency 18639.344262                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency 18639.344262                       # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst          366                       # number of ReadReq MSHR misses
+system.cpu1.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
+system.cpu1.icache.demand_mshr_misses::cpu1.inst          366                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
+system.cpu1.icache.overall_mshr_misses::cpu1.inst          366                       # number of overall MSHR misses
+system.cpu1.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
+system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst      6822000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_latency::total      6822000                       # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst      6822000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total      6822000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst      6822000                       # number of overall MSHR miss cycles
+system.cpu1.icache.overall_mshr_miss_latency::total      6822000                       # number of overall MSHR miss cycles
+system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst     0.002123                       # mshr miss rate for ReadReq accesses
+system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst     0.002123                       # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst     0.002123                       # mshr miss rate for overall accesses
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18639.344262                       # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18639.344262                       # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18639.344262                       # average overall mshr miss latency
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu1.dcache.replacements                     2                       # number of replacements
-system.cpu1.dcache.tagsinuse                22.703917                       # Cycle average of tags in use
+system.cpu1.dcache.tagsinuse                26.693562                       # Cycle average of tags in use
 system.cpu1.dcache.total_refs                   18908                       # Total number of references to valid blocks.
 system.cpu1.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
 system.cpu1.dcache.avg_refs                609.935484                       # Average number of references to valid blocks.
 system.cpu1.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu1.dcache.occ_blocks::0            26.693562                       # Average occupied blocks per context
-system.cpu1.dcache.occ_blocks::1            -3.989645                       # Average occupied blocks per context
-system.cpu1.dcache.occ_percent::0            0.052136                       # Average percentage of cache occupancy
-system.cpu1.dcache.occ_percent::1           -0.007792                       # Average percentage of cache occupancy
-system.cpu1.dcache.ReadReq_hits                 39428                       # number of ReadReq hits
-system.cpu1.dcache.WriteReq_hits                 8099                       # number of WriteReq hits
-system.cpu1.dcache.SwapReq_hits                    18                       # number of SwapReq hits
-system.cpu1.dcache.demand_hits                  47527                       # number of demand (read+write) hits
-system.cpu1.dcache.overall_hits                 47527                       # number of overall hits
-system.cpu1.dcache.ReadReq_misses                 181                       # number of ReadReq misses
-system.cpu1.dcache.WriteReq_misses                 98                       # number of WriteReq misses
-system.cpu1.dcache.SwapReq_misses                  65                       # number of SwapReq misses
-system.cpu1.dcache.demand_misses                  279                       # number of demand (read+write) misses
-system.cpu1.dcache.overall_misses                 279                       # number of overall misses
-system.cpu1.dcache.ReadReq_miss_latency       3713000                       # number of ReadReq miss cycles
-system.cpu1.dcache.WriteReq_miss_latency      1889000                       # number of WriteReq miss cycles
-system.cpu1.dcache.SwapReq_miss_latency        415000                       # number of SwapReq miss cycles
-system.cpu1.dcache.demand_miss_latency        5602000                       # number of demand (read+write) miss cycles
-system.cpu1.dcache.overall_miss_latency       5602000                       # number of overall miss cycles
-system.cpu1.dcache.ReadReq_accesses             39609                       # number of ReadReq accesses(hits+misses)
-system.cpu1.dcache.WriteReq_accesses             8197                       # number of WriteReq accesses(hits+misses)
-system.cpu1.dcache.SwapReq_accesses                83                       # number of SwapReq accesses(hits+misses)
-system.cpu1.dcache.demand_accesses              47806                       # number of demand (read+write) accesses
-system.cpu1.dcache.overall_accesses             47806                       # number of overall (read+write) accesses
-system.cpu1.dcache.ReadReq_miss_rate         0.004570                       # miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_miss_rate        0.011956                       # miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_miss_rate         0.783133                       # miss rate for SwapReq accesses
-system.cpu1.dcache.demand_miss_rate          0.005836                       # miss rate for demand accesses
-system.cpu1.dcache.overall_miss_rate         0.005836                       # miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_miss_latency 20513.812155                       # average ReadReq miss latency
-system.cpu1.dcache.WriteReq_avg_miss_latency 19275.510204                       # average WriteReq miss latency
-system.cpu1.dcache.SwapReq_avg_miss_latency  6384.615385                       # average SwapReq miss latency
-system.cpu1.dcache.demand_avg_miss_latency 20078.853047                       # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency 20078.853047                       # average overall miss latency
+system.cpu1.dcache.occ_blocks::cpu1.data    26.693562                       # Average occupied blocks per requestor
+system.cpu1.dcache.occ_percent::cpu1.data     0.052136                       # Average percentage of cache occupancy
+system.cpu1.dcache.occ_percent::total        0.052136                       # Average percentage of cache occupancy
+system.cpu1.dcache.ReadReq_hits::cpu1.data        39428                       # number of ReadReq hits
+system.cpu1.dcache.ReadReq_hits::total          39428                       # number of ReadReq hits
+system.cpu1.dcache.WriteReq_hits::cpu1.data         8099                       # number of WriteReq hits
+system.cpu1.dcache.WriteReq_hits::total          8099                       # number of WriteReq hits
+system.cpu1.dcache.SwapReq_hits::cpu1.data           18                       # number of SwapReq hits
+system.cpu1.dcache.SwapReq_hits::total             18                       # number of SwapReq hits
+system.cpu1.dcache.demand_hits::cpu1.data        47527                       # number of demand (read+write) hits
+system.cpu1.dcache.demand_hits::total           47527                       # number of demand (read+write) hits
+system.cpu1.dcache.overall_hits::cpu1.data        47527                       # number of overall hits
+system.cpu1.dcache.overall_hits::total          47527                       # number of overall hits
+system.cpu1.dcache.ReadReq_misses::cpu1.data          181                       # number of ReadReq misses
+system.cpu1.dcache.ReadReq_misses::total          181                       # number of ReadReq misses
+system.cpu1.dcache.WriteReq_misses::cpu1.data           98                       # number of WriteReq misses
+system.cpu1.dcache.WriteReq_misses::total           98                       # number of WriteReq misses
+system.cpu1.dcache.SwapReq_misses::cpu1.data           65                       # number of SwapReq misses
+system.cpu1.dcache.SwapReq_misses::total           65                       # number of SwapReq misses
+system.cpu1.dcache.demand_misses::cpu1.data          279                       # number of demand (read+write) misses
+system.cpu1.dcache.demand_misses::total           279                       # number of demand (read+write) misses
+system.cpu1.dcache.overall_misses::cpu1.data          279                       # number of overall misses
+system.cpu1.dcache.overall_misses::total          279                       # number of overall misses
+system.cpu1.dcache.ReadReq_miss_latency::cpu1.data      3713000                       # number of ReadReq miss cycles
+system.cpu1.dcache.ReadReq_miss_latency::total      3713000                       # number of ReadReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::cpu1.data      1889000                       # number of WriteReq miss cycles
+system.cpu1.dcache.WriteReq_miss_latency::total      1889000                       # number of WriteReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::cpu1.data       415000                       # number of SwapReq miss cycles
+system.cpu1.dcache.SwapReq_miss_latency::total       415000                       # number of SwapReq miss cycles
+system.cpu1.dcache.demand_miss_latency::cpu1.data      5602000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.demand_miss_latency::total      5602000                       # number of demand (read+write) miss cycles
+system.cpu1.dcache.overall_miss_latency::cpu1.data      5602000                       # number of overall miss cycles
+system.cpu1.dcache.overall_miss_latency::total      5602000                       # number of overall miss cycles
+system.cpu1.dcache.ReadReq_accesses::cpu1.data        39609                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.ReadReq_accesses::total        39609                       # number of ReadReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::cpu1.data         8197                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.WriteReq_accesses::total         8197                       # number of WriteReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::cpu1.data           83                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.SwapReq_accesses::total           83                       # number of SwapReq accesses(hits+misses)
+system.cpu1.dcache.demand_accesses::cpu1.data        47806                       # number of demand (read+write) accesses
+system.cpu1.dcache.demand_accesses::total        47806                       # number of demand (read+write) accesses
+system.cpu1.dcache.overall_accesses::cpu1.data        47806                       # number of overall (read+write) accesses
+system.cpu1.dcache.overall_accesses::total        47806                       # number of overall (read+write) accesses
+system.cpu1.dcache.ReadReq_miss_rate::cpu1.data     0.004570                       # miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_miss_rate::cpu1.data     0.011956                       # miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_miss_rate::cpu1.data     0.783133                       # miss rate for SwapReq accesses
+system.cpu1.dcache.demand_miss_rate::cpu1.data     0.005836                       # miss rate for demand accesses
+system.cpu1.dcache.overall_miss_rate::cpu1.data     0.005836                       # miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20513.812155                       # average ReadReq miss latency
+system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19275.510204                       # average WriteReq miss latency
+system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data  6384.615385                       # average SwapReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20078.853047                       # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20078.853047                       # average overall miss latency
 system.cpu1.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -294,39 +364,44 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu1.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu1.dcache.writebacks                       1                       # number of writebacks
-system.cpu1.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu1.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu1.dcache.ReadReq_mshr_misses            181                       # number of ReadReq MSHR misses
-system.cpu1.dcache.WriteReq_mshr_misses            98                       # number of WriteReq MSHR misses
-system.cpu1.dcache.SwapReq_mshr_misses             65                       # number of SwapReq MSHR misses
-system.cpu1.dcache.demand_mshr_misses             279                       # number of demand (read+write) MSHR misses
-system.cpu1.dcache.overall_mshr_misses            279                       # number of overall MSHR misses
-system.cpu1.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.dcache.ReadReq_mshr_miss_latency      3170000                       # number of ReadReq MSHR miss cycles
-system.cpu1.dcache.WriteReq_mshr_miss_latency      1595000                       # number of WriteReq MSHR miss cycles
-system.cpu1.dcache.SwapReq_mshr_miss_latency       220000                       # number of SwapReq MSHR miss cycles
-system.cpu1.dcache.demand_mshr_miss_latency      4765000                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.dcache.overall_mshr_miss_latency      4765000                       # number of overall MSHR miss cycles
-system.cpu1.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu1.dcache.ReadReq_mshr_miss_rate     0.004570                       # mshr miss rate for ReadReq accesses
-system.cpu1.dcache.WriteReq_mshr_miss_rate     0.011956                       # mshr miss rate for WriteReq accesses
-system.cpu1.dcache.SwapReq_mshr_miss_rate     0.783133                       # mshr miss rate for SwapReq accesses
-system.cpu1.dcache.demand_mshr_miss_rate     0.005836                       # mshr miss rate for demand accesses
-system.cpu1.dcache.overall_mshr_miss_rate     0.005836                       # mshr miss rate for overall accesses
-system.cpu1.dcache.ReadReq_avg_mshr_miss_latency 17513.812155                       # average ReadReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency 16275.510204                       # average WriteReq mshr miss latency
-system.cpu1.dcache.SwapReq_avg_mshr_miss_latency  3384.615385                       # average SwapReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency 17078.853047                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency 17078.853047                       # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu1.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu1.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu1.dcache.writebacks::total                1                       # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data          181                       # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total          181                       # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data           98                       # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total           98                       # number of WriteReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data           65                       # number of SwapReq MSHR misses
+system.cpu1.dcache.SwapReq_mshr_misses::total           65                       # number of SwapReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data          279                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total          279                       # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data          279                       # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total          279                       # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data      3170000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total      3170000                       # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data      1595000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total      1595000                       # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data       220000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.SwapReq_mshr_miss_latency::total       220000                       # number of SwapReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data      4765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total      4765000                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data      4765000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total      4765000                       # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data     0.004570                       # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data     0.011956                       # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data     0.783133                       # mshr miss rate for SwapReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data     0.005836                       # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data     0.005836                       # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17513.812155                       # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 16275.510204                       # average WriteReq mshr miss latency
+system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data  3384.615385                       # average SwapReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17078.853047                       # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17078.853047                       # average overall mshr miss latency
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.numCycles                          524596                       # number of cpu cycles simulated
 system.cpu2.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu2.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu2.num_insts                          165499                       # Number of instructions executed
+system.cpu2.committedInsts                     165499                       # Number of instructions committed
+system.cpu2.committedOps                       165499                       # Number of ops (including micro ops) committed
 system.cpu2.num_int_alu_accesses               112355                       # Number of integer alu accesses
 system.cpu2.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu2.num_func_calls                        637                       # number of times a function call or return occured
@@ -350,26 +425,39 @@ system.cpu2.icache.total_refs                  165166                       # To
 system.cpu2.icache.sampled_refs                   366                       # Sample count of references to valid blocks.
 system.cpu2.icache.avg_refs                451.273224                       # Average number of references to valid blocks.
 system.cpu2.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.icache.occ_blocks::0            65.601019                       # Average occupied blocks per context
-system.cpu2.icache.occ_percent::0            0.128127                       # Average percentage of cache occupancy
-system.cpu2.icache.ReadReq_hits                165166                       # number of ReadReq hits
-system.cpu2.icache.demand_hits                 165166                       # number of demand (read+write) hits
-system.cpu2.icache.overall_hits                165166                       # number of overall hits
-system.cpu2.icache.ReadReq_misses                 366                       # number of ReadReq misses
-system.cpu2.icache.demand_misses                  366                       # number of demand (read+write) misses
-system.cpu2.icache.overall_misses                 366                       # number of overall misses
-system.cpu2.icache.ReadReq_miss_latency       5648500                       # number of ReadReq miss cycles
-system.cpu2.icache.demand_miss_latency        5648500                       # number of demand (read+write) miss cycles
-system.cpu2.icache.overall_miss_latency       5648500                       # number of overall miss cycles
-system.cpu2.icache.ReadReq_accesses            165532                       # number of ReadReq accesses(hits+misses)
-system.cpu2.icache.demand_accesses             165532                       # number of demand (read+write) accesses
-system.cpu2.icache.overall_accesses            165532                       # number of overall (read+write) accesses
-system.cpu2.icache.ReadReq_miss_rate         0.002211                       # miss rate for ReadReq accesses
-system.cpu2.icache.demand_miss_rate          0.002211                       # miss rate for demand accesses
-system.cpu2.icache.overall_miss_rate         0.002211                       # miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_miss_latency 15433.060109                       # average ReadReq miss latency
-system.cpu2.icache.demand_avg_miss_latency 15433.060109                       # average overall miss latency
-system.cpu2.icache.overall_avg_miss_latency 15433.060109                       # average overall miss latency
+system.cpu2.icache.occ_blocks::cpu2.inst    65.601019                       # Average occupied blocks per requestor
+system.cpu2.icache.occ_percent::cpu2.inst     0.128127                       # Average percentage of cache occupancy
+system.cpu2.icache.occ_percent::total        0.128127                       # Average percentage of cache occupancy
+system.cpu2.icache.ReadReq_hits::cpu2.inst       165166                       # number of ReadReq hits
+system.cpu2.icache.ReadReq_hits::total         165166                       # number of ReadReq hits
+system.cpu2.icache.demand_hits::cpu2.inst       165166                       # number of demand (read+write) hits
+system.cpu2.icache.demand_hits::total          165166                       # number of demand (read+write) hits
+system.cpu2.icache.overall_hits::cpu2.inst       165166                       # number of overall hits
+system.cpu2.icache.overall_hits::total         165166                       # number of overall hits
+system.cpu2.icache.ReadReq_misses::cpu2.inst          366                       # number of ReadReq misses
+system.cpu2.icache.ReadReq_misses::total          366                       # number of ReadReq misses
+system.cpu2.icache.demand_misses::cpu2.inst          366                       # number of demand (read+write) misses
+system.cpu2.icache.demand_misses::total           366                       # number of demand (read+write) misses
+system.cpu2.icache.overall_misses::cpu2.inst          366                       # number of overall misses
+system.cpu2.icache.overall_misses::total          366                       # number of overall misses
+system.cpu2.icache.ReadReq_miss_latency::cpu2.inst      5648500                       # number of ReadReq miss cycles
+system.cpu2.icache.ReadReq_miss_latency::total      5648500                       # number of ReadReq miss cycles
+system.cpu2.icache.demand_miss_latency::cpu2.inst      5648500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.demand_miss_latency::total      5648500                       # number of demand (read+write) miss cycles
+system.cpu2.icache.overall_miss_latency::cpu2.inst      5648500                       # number of overall miss cycles
+system.cpu2.icache.overall_miss_latency::total      5648500                       # number of overall miss cycles
+system.cpu2.icache.ReadReq_accesses::cpu2.inst       165532                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.ReadReq_accesses::total       165532                       # number of ReadReq accesses(hits+misses)
+system.cpu2.icache.demand_accesses::cpu2.inst       165532                       # number of demand (read+write) accesses
+system.cpu2.icache.demand_accesses::total       165532                       # number of demand (read+write) accesses
+system.cpu2.icache.overall_accesses::cpu2.inst       165532                       # number of overall (read+write) accesses
+system.cpu2.icache.overall_accesses::total       165532                       # number of overall (read+write) accesses
+system.cpu2.icache.ReadReq_miss_rate::cpu2.inst     0.002211                       # miss rate for ReadReq accesses
+system.cpu2.icache.demand_miss_rate::cpu2.inst     0.002211                       # miss rate for demand accesses
+system.cpu2.icache.overall_miss_rate::cpu2.inst     0.002211                       # miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15433.060109                       # average ReadReq miss latency
+system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15433.060109                       # average overall miss latency
+system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15433.060109                       # average overall miss latency
 system.cpu2.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -378,67 +466,84 @@ system.cpu2.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu2.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.icache.writebacks                       0                       # number of writebacks
-system.cpu2.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu2.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu2.icache.ReadReq_mshr_misses            366                       # number of ReadReq MSHR misses
-system.cpu2.icache.demand_mshr_misses             366                       # number of demand (read+write) MSHR misses
-system.cpu2.icache.overall_mshr_misses            366                       # number of overall MSHR misses
-system.cpu2.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.icache.ReadReq_mshr_miss_latency      4550500                       # number of ReadReq MSHR miss cycles
-system.cpu2.icache.demand_mshr_miss_latency      4550500                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.icache.overall_mshr_miss_latency      4550500                       # number of overall MSHR miss cycles
-system.cpu2.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.icache.ReadReq_mshr_miss_rate     0.002211                       # mshr miss rate for ReadReq accesses
-system.cpu2.icache.demand_mshr_miss_rate     0.002211                       # mshr miss rate for demand accesses
-system.cpu2.icache.overall_mshr_miss_rate     0.002211                       # mshr miss rate for overall accesses
-system.cpu2.icache.ReadReq_avg_mshr_miss_latency 12433.060109                       # average ReadReq mshr miss latency
-system.cpu2.icache.demand_avg_mshr_miss_latency 12433.060109                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_miss_latency 12433.060109                       # average overall mshr miss latency
-system.cpu2.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu2.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu2.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst          366                       # number of ReadReq MSHR misses
+system.cpu2.icache.ReadReq_mshr_misses::total          366                       # number of ReadReq MSHR misses
+system.cpu2.icache.demand_mshr_misses::cpu2.inst          366                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.demand_mshr_misses::total          366                       # number of demand (read+write) MSHR misses
+system.cpu2.icache.overall_mshr_misses::cpu2.inst          366                       # number of overall MSHR misses
+system.cpu2.icache.overall_mshr_misses::total          366                       # number of overall MSHR misses
+system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst      4550500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_latency::total      4550500                       # number of ReadReq MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst      4550500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.demand_mshr_miss_latency::total      4550500                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst      4550500                       # number of overall MSHR miss cycles
+system.cpu2.icache.overall_mshr_miss_latency::total      4550500                       # number of overall MSHR miss cycles
+system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst     0.002211                       # mshr miss rate for ReadReq accesses
+system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst     0.002211                       # mshr miss rate for demand accesses
+system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst     0.002211                       # mshr miss rate for overall accesses
+system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12433.060109                       # average ReadReq mshr miss latency
+system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12433.060109                       # average overall mshr miss latency
+system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12433.060109                       # average overall mshr miss latency
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu2.dcache.replacements                     2                       # number of replacements
-system.cpu2.dcache.tagsinuse                23.305393                       # Cycle average of tags in use
+system.cpu2.dcache.tagsinuse                24.943438                       # Cycle average of tags in use
 system.cpu2.dcache.total_refs                   34578                       # Total number of references to valid blocks.
 system.cpu2.dcache.sampled_refs                    31                       # Sample count of references to valid blocks.
 system.cpu2.dcache.avg_refs               1115.419355                       # Average number of references to valid blocks.
 system.cpu2.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu2.dcache.occ_blocks::0            24.943438                       # Average occupied blocks per context
-system.cpu2.dcache.occ_blocks::1            -1.638045                       # Average occupied blocks per context
-system.cpu2.dcache.occ_percent::0            0.048718                       # Average percentage of cache occupancy
-system.cpu2.dcache.occ_percent::1           -0.003199                       # Average percentage of cache occupancy
-system.cpu2.dcache.ReadReq_hits                 41688                       # number of ReadReq hits
-system.cpu2.dcache.WriteReq_hits                15916                       # number of WriteReq hits
-system.cpu2.dcache.SwapReq_hits                    11                       # number of SwapReq hits
-system.cpu2.dcache.demand_hits                  57604                       # number of demand (read+write) hits
-system.cpu2.dcache.overall_hits                 57604                       # number of overall hits
-system.cpu2.dcache.ReadReq_misses                 156                       # number of ReadReq misses
-system.cpu2.dcache.WriteReq_misses                109                       # number of WriteReq misses
-system.cpu2.dcache.SwapReq_misses                  51                       # number of SwapReq misses
-system.cpu2.dcache.demand_misses                  265                       # number of demand (read+write) misses
-system.cpu2.dcache.overall_misses                 265                       # number of overall misses
-system.cpu2.dcache.ReadReq_miss_latency       2527000                       # number of ReadReq miss cycles
-system.cpu2.dcache.WriteReq_miss_latency      2084000                       # number of WriteReq miss cycles
-system.cpu2.dcache.SwapReq_miss_latency        305000                       # number of SwapReq miss cycles
-system.cpu2.dcache.demand_miss_latency        4611000                       # number of demand (read+write) miss cycles
-system.cpu2.dcache.overall_miss_latency       4611000                       # number of overall miss cycles
-system.cpu2.dcache.ReadReq_accesses             41844                       # number of ReadReq accesses(hits+misses)
-system.cpu2.dcache.WriteReq_accesses            16025                       # number of WriteReq accesses(hits+misses)
-system.cpu2.dcache.SwapReq_accesses                62                       # number of SwapReq accesses(hits+misses)
-system.cpu2.dcache.demand_accesses              57869                       # number of demand (read+write) accesses
-system.cpu2.dcache.overall_accesses             57869                       # number of overall (read+write) accesses
-system.cpu2.dcache.ReadReq_miss_rate         0.003728                       # miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_miss_rate        0.006802                       # miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_miss_rate         0.822581                       # miss rate for SwapReq accesses
-system.cpu2.dcache.demand_miss_rate          0.004579                       # miss rate for demand accesses
-system.cpu2.dcache.overall_miss_rate         0.004579                       # miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_miss_latency 16198.717949                       # average ReadReq miss latency
-system.cpu2.dcache.WriteReq_avg_miss_latency 19119.266055                       # average WriteReq miss latency
-system.cpu2.dcache.SwapReq_avg_miss_latency  5980.392157                       # average SwapReq miss latency
-system.cpu2.dcache.demand_avg_miss_latency        17400                       # average overall miss latency
-system.cpu2.dcache.overall_avg_miss_latency        17400                       # average overall miss latency
+system.cpu2.dcache.occ_blocks::cpu2.data    24.943438                       # Average occupied blocks per requestor
+system.cpu2.dcache.occ_percent::cpu2.data     0.048718                       # Average percentage of cache occupancy
+system.cpu2.dcache.occ_percent::total        0.048718                       # Average percentage of cache occupancy
+system.cpu2.dcache.ReadReq_hits::cpu2.data        41688                       # number of ReadReq hits
+system.cpu2.dcache.ReadReq_hits::total          41688                       # number of ReadReq hits
+system.cpu2.dcache.WriteReq_hits::cpu2.data        15916                       # number of WriteReq hits
+system.cpu2.dcache.WriteReq_hits::total         15916                       # number of WriteReq hits
+system.cpu2.dcache.SwapReq_hits::cpu2.data           11                       # number of SwapReq hits
+system.cpu2.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
+system.cpu2.dcache.demand_hits::cpu2.data        57604                       # number of demand (read+write) hits
+system.cpu2.dcache.demand_hits::total           57604                       # number of demand (read+write) hits
+system.cpu2.dcache.overall_hits::cpu2.data        57604                       # number of overall hits
+system.cpu2.dcache.overall_hits::total          57604                       # number of overall hits
+system.cpu2.dcache.ReadReq_misses::cpu2.data          156                       # number of ReadReq misses
+system.cpu2.dcache.ReadReq_misses::total          156                       # number of ReadReq misses
+system.cpu2.dcache.WriteReq_misses::cpu2.data          109                       # number of WriteReq misses
+system.cpu2.dcache.WriteReq_misses::total          109                       # number of WriteReq misses
+system.cpu2.dcache.SwapReq_misses::cpu2.data           51                       # number of SwapReq misses
+system.cpu2.dcache.SwapReq_misses::total           51                       # number of SwapReq misses
+system.cpu2.dcache.demand_misses::cpu2.data          265                       # number of demand (read+write) misses
+system.cpu2.dcache.demand_misses::total           265                       # number of demand (read+write) misses
+system.cpu2.dcache.overall_misses::cpu2.data          265                       # number of overall misses
+system.cpu2.dcache.overall_misses::total          265                       # number of overall misses
+system.cpu2.dcache.ReadReq_miss_latency::cpu2.data      2527000                       # number of ReadReq miss cycles
+system.cpu2.dcache.ReadReq_miss_latency::total      2527000                       # number of ReadReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::cpu2.data      2084000                       # number of WriteReq miss cycles
+system.cpu2.dcache.WriteReq_miss_latency::total      2084000                       # number of WriteReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::cpu2.data       305000                       # number of SwapReq miss cycles
+system.cpu2.dcache.SwapReq_miss_latency::total       305000                       # number of SwapReq miss cycles
+system.cpu2.dcache.demand_miss_latency::cpu2.data      4611000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.demand_miss_latency::total      4611000                       # number of demand (read+write) miss cycles
+system.cpu2.dcache.overall_miss_latency::cpu2.data      4611000                       # number of overall miss cycles
+system.cpu2.dcache.overall_miss_latency::total      4611000                       # number of overall miss cycles
+system.cpu2.dcache.ReadReq_accesses::cpu2.data        41844                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.ReadReq_accesses::total        41844                       # number of ReadReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::cpu2.data        16025                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.WriteReq_accesses::total        16025                       # number of WriteReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::cpu2.data           62                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.SwapReq_accesses::total           62                       # number of SwapReq accesses(hits+misses)
+system.cpu2.dcache.demand_accesses::cpu2.data        57869                       # number of demand (read+write) accesses
+system.cpu2.dcache.demand_accesses::total        57869                       # number of demand (read+write) accesses
+system.cpu2.dcache.overall_accesses::cpu2.data        57869                       # number of overall (read+write) accesses
+system.cpu2.dcache.overall_accesses::total        57869                       # number of overall (read+write) accesses
+system.cpu2.dcache.ReadReq_miss_rate::cpu2.data     0.003728                       # miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_miss_rate::cpu2.data     0.006802                       # miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_miss_rate::cpu2.data     0.822581                       # miss rate for SwapReq accesses
+system.cpu2.dcache.demand_miss_rate::cpu2.data     0.004579                       # miss rate for demand accesses
+system.cpu2.dcache.overall_miss_rate::cpu2.data     0.004579                       # miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 16198.717949                       # average ReadReq miss latency
+system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 19119.266055                       # average WriteReq miss latency
+system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data  5980.392157                       # average SwapReq miss latency
+system.cpu2.dcache.demand_avg_miss_latency::cpu2.data        17400                       # average overall miss latency
+system.cpu2.dcache.overall_avg_miss_latency::cpu2.data        17400                       # average overall miss latency
 system.cpu2.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -447,39 +552,44 @@ system.cpu2.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu2.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu2.dcache.writebacks                       1                       # number of writebacks
-system.cpu2.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu2.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu2.dcache.ReadReq_mshr_misses            156                       # number of ReadReq MSHR misses
-system.cpu2.dcache.WriteReq_mshr_misses           109                       # number of WriteReq MSHR misses
-system.cpu2.dcache.SwapReq_mshr_misses             51                       # number of SwapReq MSHR misses
-system.cpu2.dcache.demand_mshr_misses             265                       # number of demand (read+write) MSHR misses
-system.cpu2.dcache.overall_mshr_misses            265                       # number of overall MSHR misses
-system.cpu2.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.dcache.ReadReq_mshr_miss_latency      2059000                       # number of ReadReq MSHR miss cycles
-system.cpu2.dcache.WriteReq_mshr_miss_latency      1757000                       # number of WriteReq MSHR miss cycles
-system.cpu2.dcache.SwapReq_mshr_miss_latency       152000                       # number of SwapReq MSHR miss cycles
-system.cpu2.dcache.demand_mshr_miss_latency      3816000                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.dcache.overall_mshr_miss_latency      3816000                       # number of overall MSHR miss cycles
-system.cpu2.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu2.dcache.ReadReq_mshr_miss_rate     0.003728                       # mshr miss rate for ReadReq accesses
-system.cpu2.dcache.WriteReq_mshr_miss_rate     0.006802                       # mshr miss rate for WriteReq accesses
-system.cpu2.dcache.SwapReq_mshr_miss_rate     0.822581                       # mshr miss rate for SwapReq accesses
-system.cpu2.dcache.demand_mshr_miss_rate     0.004579                       # mshr miss rate for demand accesses
-system.cpu2.dcache.overall_mshr_miss_rate     0.004579                       # mshr miss rate for overall accesses
-system.cpu2.dcache.ReadReq_avg_mshr_miss_latency 13198.717949                       # average ReadReq mshr miss latency
-system.cpu2.dcache.WriteReq_avg_mshr_miss_latency 16119.266055                       # average WriteReq mshr miss latency
-system.cpu2.dcache.SwapReq_avg_mshr_miss_latency  2980.392157                       # average SwapReq mshr miss latency
-system.cpu2.dcache.demand_avg_mshr_miss_latency        14400                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_miss_latency        14400                       # average overall mshr miss latency
-system.cpu2.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu2.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu2.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu2.dcache.writebacks::total                1                       # number of writebacks
+system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data          156                       # number of ReadReq MSHR misses
+system.cpu2.dcache.ReadReq_mshr_misses::total          156                       # number of ReadReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data          109                       # number of WriteReq MSHR misses
+system.cpu2.dcache.WriteReq_mshr_misses::total          109                       # number of WriteReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data           51                       # number of SwapReq MSHR misses
+system.cpu2.dcache.SwapReq_mshr_misses::total           51                       # number of SwapReq MSHR misses
+system.cpu2.dcache.demand_mshr_misses::cpu2.data          265                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
+system.cpu2.dcache.overall_mshr_misses::cpu2.data          265                       # number of overall MSHR misses
+system.cpu2.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
+system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data      2059000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_latency::total      2059000                       # number of ReadReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data      1757000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.WriteReq_mshr_miss_latency::total      1757000                       # number of WriteReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data       152000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.SwapReq_mshr_miss_latency::total       152000                       # number of SwapReq MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data      3816000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.demand_mshr_miss_latency::total      3816000                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data      3816000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.overall_mshr_miss_latency::total      3816000                       # number of overall MSHR miss cycles
+system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data     0.003728                       # mshr miss rate for ReadReq accesses
+system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data     0.006802                       # mshr miss rate for WriteReq accesses
+system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data     0.822581                       # mshr miss rate for SwapReq accesses
+system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data     0.004579                       # mshr miss rate for demand accesses
+system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data     0.004579                       # mshr miss rate for overall accesses
+system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13198.717949                       # average ReadReq mshr miss latency
+system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 16119.266055                       # average WriteReq mshr miss latency
+system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data  2980.392157                       # average SwapReq mshr miss latency
+system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data        14400                       # average overall mshr miss latency
+system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data        14400                       # average overall mshr miss latency
 system.cpu2.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.numCycles                          524596                       # number of cpu cycles simulated
 system.cpu3.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu3.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu3.num_insts                          166130                       # Number of instructions executed
+system.cpu3.committedInsts                     166130                       # Number of instructions committed
+system.cpu3.committedOps                       166130                       # Number of ops (including micro ops) committed
 system.cpu3.num_int_alu_accesses               112098                       # Number of integer alu accesses
 system.cpu3.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu3.num_func_calls                        637                       # number of times a function call or return occured
@@ -503,26 +613,39 @@ system.cpu3.icache.total_refs                  165796                       # To
 system.cpu3.icache.sampled_refs                   367                       # Sample count of references to valid blocks.
 system.cpu3.icache.avg_refs                451.760218                       # Average number of references to valid blocks.
 system.cpu3.icache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.icache.occ_blocks::0            67.737646                       # Average occupied blocks per context
-system.cpu3.icache.occ_percent::0            0.132300                       # Average percentage of cache occupancy
-system.cpu3.icache.ReadReq_hits                165796                       # number of ReadReq hits
-system.cpu3.icache.demand_hits                 165796                       # number of demand (read+write) hits
-system.cpu3.icache.overall_hits                165796                       # number of overall hits
-system.cpu3.icache.ReadReq_misses                 367                       # number of ReadReq misses
-system.cpu3.icache.demand_misses                  367                       # number of demand (read+write) misses
-system.cpu3.icache.overall_misses                 367                       # number of overall misses
-system.cpu3.icache.ReadReq_miss_latency       5531500                       # number of ReadReq miss cycles
-system.cpu3.icache.demand_miss_latency        5531500                       # number of demand (read+write) miss cycles
-system.cpu3.icache.overall_miss_latency       5531500                       # number of overall miss cycles
-system.cpu3.icache.ReadReq_accesses            166163                       # number of ReadReq accesses(hits+misses)
-system.cpu3.icache.demand_accesses             166163                       # number of demand (read+write) accesses
-system.cpu3.icache.overall_accesses            166163                       # number of overall (read+write) accesses
-system.cpu3.icache.ReadReq_miss_rate         0.002209                       # miss rate for ReadReq accesses
-system.cpu3.icache.demand_miss_rate          0.002209                       # miss rate for demand accesses
-system.cpu3.icache.overall_miss_rate         0.002209                       # miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_miss_latency 15072.207084                       # average ReadReq miss latency
-system.cpu3.icache.demand_avg_miss_latency 15072.207084                       # average overall miss latency
-system.cpu3.icache.overall_avg_miss_latency 15072.207084                       # average overall miss latency
+system.cpu3.icache.occ_blocks::cpu3.inst    67.737646                       # Average occupied blocks per requestor
+system.cpu3.icache.occ_percent::cpu3.inst     0.132300                       # Average percentage of cache occupancy
+system.cpu3.icache.occ_percent::total        0.132300                       # Average percentage of cache occupancy
+system.cpu3.icache.ReadReq_hits::cpu3.inst       165796                       # number of ReadReq hits
+system.cpu3.icache.ReadReq_hits::total         165796                       # number of ReadReq hits
+system.cpu3.icache.demand_hits::cpu3.inst       165796                       # number of demand (read+write) hits
+system.cpu3.icache.demand_hits::total          165796                       # number of demand (read+write) hits
+system.cpu3.icache.overall_hits::cpu3.inst       165796                       # number of overall hits
+system.cpu3.icache.overall_hits::total         165796                       # number of overall hits
+system.cpu3.icache.ReadReq_misses::cpu3.inst          367                       # number of ReadReq misses
+system.cpu3.icache.ReadReq_misses::total          367                       # number of ReadReq misses
+system.cpu3.icache.demand_misses::cpu3.inst          367                       # number of demand (read+write) misses
+system.cpu3.icache.demand_misses::total           367                       # number of demand (read+write) misses
+system.cpu3.icache.overall_misses::cpu3.inst          367                       # number of overall misses
+system.cpu3.icache.overall_misses::total          367                       # number of overall misses
+system.cpu3.icache.ReadReq_miss_latency::cpu3.inst      5531500                       # number of ReadReq miss cycles
+system.cpu3.icache.ReadReq_miss_latency::total      5531500                       # number of ReadReq miss cycles
+system.cpu3.icache.demand_miss_latency::cpu3.inst      5531500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.demand_miss_latency::total      5531500                       # number of demand (read+write) miss cycles
+system.cpu3.icache.overall_miss_latency::cpu3.inst      5531500                       # number of overall miss cycles
+system.cpu3.icache.overall_miss_latency::total      5531500                       # number of overall miss cycles
+system.cpu3.icache.ReadReq_accesses::cpu3.inst       166163                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.ReadReq_accesses::total       166163                       # number of ReadReq accesses(hits+misses)
+system.cpu3.icache.demand_accesses::cpu3.inst       166163                       # number of demand (read+write) accesses
+system.cpu3.icache.demand_accesses::total       166163                       # number of demand (read+write) accesses
+system.cpu3.icache.overall_accesses::cpu3.inst       166163                       # number of overall (read+write) accesses
+system.cpu3.icache.overall_accesses::total       166163                       # number of overall (read+write) accesses
+system.cpu3.icache.ReadReq_miss_rate::cpu3.inst     0.002209                       # miss rate for ReadReq accesses
+system.cpu3.icache.demand_miss_rate::cpu3.inst     0.002209                       # miss rate for demand accesses
+system.cpu3.icache.overall_miss_rate::cpu3.inst     0.002209                       # miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15072.207084                       # average ReadReq miss latency
+system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15072.207084                       # average overall miss latency
+system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15072.207084                       # average overall miss latency
 system.cpu3.icache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.icache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -531,67 +654,84 @@ system.cpu3.icache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu3.icache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.icache.writebacks                       0                       # number of writebacks
-system.cpu3.icache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu3.icache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu3.icache.ReadReq_mshr_misses            367                       # number of ReadReq MSHR misses
-system.cpu3.icache.demand_mshr_misses             367                       # number of demand (read+write) MSHR misses
-system.cpu3.icache.overall_mshr_misses            367                       # number of overall MSHR misses
-system.cpu3.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.icache.ReadReq_mshr_miss_latency      4430500                       # number of ReadReq MSHR miss cycles
-system.cpu3.icache.demand_mshr_miss_latency      4430500                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.icache.overall_mshr_miss_latency      4430500                       # number of overall MSHR miss cycles
-system.cpu3.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.icache.ReadReq_mshr_miss_rate     0.002209                       # mshr miss rate for ReadReq accesses
-system.cpu3.icache.demand_mshr_miss_rate     0.002209                       # mshr miss rate for demand accesses
-system.cpu3.icache.overall_mshr_miss_rate     0.002209                       # mshr miss rate for overall accesses
-system.cpu3.icache.ReadReq_avg_mshr_miss_latency 12072.207084                       # average ReadReq mshr miss latency
-system.cpu3.icache.demand_avg_mshr_miss_latency 12072.207084                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_miss_latency 12072.207084                       # average overall mshr miss latency
-system.cpu3.icache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu3.icache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu3.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst          367                       # number of ReadReq MSHR misses
+system.cpu3.icache.ReadReq_mshr_misses::total          367                       # number of ReadReq MSHR misses
+system.cpu3.icache.demand_mshr_misses::cpu3.inst          367                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.demand_mshr_misses::total          367                       # number of demand (read+write) MSHR misses
+system.cpu3.icache.overall_mshr_misses::cpu3.inst          367                       # number of overall MSHR misses
+system.cpu3.icache.overall_mshr_misses::total          367                       # number of overall MSHR misses
+system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst      4430500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_latency::total      4430500                       # number of ReadReq MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst      4430500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.demand_mshr_miss_latency::total      4430500                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst      4430500                       # number of overall MSHR miss cycles
+system.cpu3.icache.overall_mshr_miss_latency::total      4430500                       # number of overall MSHR miss cycles
+system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst     0.002209                       # mshr miss rate for ReadReq accesses
+system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst     0.002209                       # mshr miss rate for demand accesses
+system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst     0.002209                       # mshr miss rate for overall accesses
+system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12072.207084                       # average ReadReq mshr miss latency
+system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12072.207084                       # average overall mshr miss latency
+system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12072.207084                       # average overall mshr miss latency
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu3.dcache.replacements                     2                       # number of replacements
-system.cpu3.dcache.tagsinuse                22.083417                       # Cycle average of tags in use
+system.cpu3.dcache.tagsinuse                25.684916                       # Cycle average of tags in use
 system.cpu3.dcache.total_refs                   33474                       # Total number of references to valid blocks.
 system.cpu3.dcache.sampled_refs                    32                       # Sample count of references to valid blocks.
 system.cpu3.dcache.avg_refs               1046.062500                       # Average number of references to valid blocks.
 system.cpu3.dcache.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
-system.cpu3.dcache.occ_blocks::0            25.684916                       # Average occupied blocks per context
-system.cpu3.dcache.occ_blocks::1            -3.601499                       # Average occupied blocks per context
-system.cpu3.dcache.occ_percent::0            0.050166                       # Average percentage of cache occupancy
-system.cpu3.dcache.occ_percent::1           -0.007034                       # Average percentage of cache occupancy
-system.cpu3.dcache.ReadReq_hits                 41555                       # number of ReadReq hits
-system.cpu3.dcache.WriteReq_hits                15348                       # number of WriteReq hits
-system.cpu3.dcache.SwapReq_hits                    11                       # number of SwapReq hits
-system.cpu3.dcache.demand_hits                  56903                       # number of demand (read+write) hits
-system.cpu3.dcache.overall_hits                 56903                       # number of overall hits
-system.cpu3.dcache.ReadReq_misses                 157                       # number of ReadReq misses
-system.cpu3.dcache.WriteReq_misses                108                       # number of WriteReq misses
-system.cpu3.dcache.SwapReq_misses                  54                       # number of SwapReq misses
-system.cpu3.dcache.demand_misses                  265                       # number of demand (read+write) misses
-system.cpu3.dcache.overall_misses                 265                       # number of overall misses
-system.cpu3.dcache.ReadReq_miss_latency       2569000                       # number of ReadReq miss cycles
-system.cpu3.dcache.WriteReq_miss_latency      2080000                       # number of WriteReq miss cycles
-system.cpu3.dcache.SwapReq_miss_latency        326000                       # number of SwapReq miss cycles
-system.cpu3.dcache.demand_miss_latency        4649000                       # number of demand (read+write) miss cycles
-system.cpu3.dcache.overall_miss_latency       4649000                       # number of overall miss cycles
-system.cpu3.dcache.ReadReq_accesses             41712                       # number of ReadReq accesses(hits+misses)
-system.cpu3.dcache.WriteReq_accesses            15456                       # number of WriteReq accesses(hits+misses)
-system.cpu3.dcache.SwapReq_accesses                65                       # number of SwapReq accesses(hits+misses)
-system.cpu3.dcache.demand_accesses              57168                       # number of demand (read+write) accesses
-system.cpu3.dcache.overall_accesses             57168                       # number of overall (read+write) accesses
-system.cpu3.dcache.ReadReq_miss_rate         0.003764                       # miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_miss_rate        0.006988                       # miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_miss_rate         0.830769                       # miss rate for SwapReq accesses
-system.cpu3.dcache.demand_miss_rate          0.004635                       # miss rate for demand accesses
-system.cpu3.dcache.overall_miss_rate         0.004635                       # miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_miss_latency 16363.057325                       # average ReadReq miss latency
-system.cpu3.dcache.WriteReq_avg_miss_latency 19259.259259                       # average WriteReq miss latency
-system.cpu3.dcache.SwapReq_avg_miss_latency  6037.037037                       # average SwapReq miss latency
-system.cpu3.dcache.demand_avg_miss_latency 17543.396226                       # average overall miss latency
-system.cpu3.dcache.overall_avg_miss_latency 17543.396226                       # average overall miss latency
+system.cpu3.dcache.occ_blocks::cpu3.data    25.684916                       # Average occupied blocks per requestor
+system.cpu3.dcache.occ_percent::cpu3.data     0.050166                       # Average percentage of cache occupancy
+system.cpu3.dcache.occ_percent::total        0.050166                       # Average percentage of cache occupancy
+system.cpu3.dcache.ReadReq_hits::cpu3.data        41555                       # number of ReadReq hits
+system.cpu3.dcache.ReadReq_hits::total          41555                       # number of ReadReq hits
+system.cpu3.dcache.WriteReq_hits::cpu3.data        15348                       # number of WriteReq hits
+system.cpu3.dcache.WriteReq_hits::total         15348                       # number of WriteReq hits
+system.cpu3.dcache.SwapReq_hits::cpu3.data           11                       # number of SwapReq hits
+system.cpu3.dcache.SwapReq_hits::total             11                       # number of SwapReq hits
+system.cpu3.dcache.demand_hits::cpu3.data        56903                       # number of demand (read+write) hits
+system.cpu3.dcache.demand_hits::total           56903                       # number of demand (read+write) hits
+system.cpu3.dcache.overall_hits::cpu3.data        56903                       # number of overall hits
+system.cpu3.dcache.overall_hits::total          56903                       # number of overall hits
+system.cpu3.dcache.ReadReq_misses::cpu3.data          157                       # number of ReadReq misses
+system.cpu3.dcache.ReadReq_misses::total          157                       # number of ReadReq misses
+system.cpu3.dcache.WriteReq_misses::cpu3.data          108                       # number of WriteReq misses
+system.cpu3.dcache.WriteReq_misses::total          108                       # number of WriteReq misses
+system.cpu3.dcache.SwapReq_misses::cpu3.data           54                       # number of SwapReq misses
+system.cpu3.dcache.SwapReq_misses::total           54                       # number of SwapReq misses
+system.cpu3.dcache.demand_misses::cpu3.data          265                       # number of demand (read+write) misses
+system.cpu3.dcache.demand_misses::total           265                       # number of demand (read+write) misses
+system.cpu3.dcache.overall_misses::cpu3.data          265                       # number of overall misses
+system.cpu3.dcache.overall_misses::total          265                       # number of overall misses
+system.cpu3.dcache.ReadReq_miss_latency::cpu3.data      2569000                       # number of ReadReq miss cycles
+system.cpu3.dcache.ReadReq_miss_latency::total      2569000                       # number of ReadReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::cpu3.data      2080000                       # number of WriteReq miss cycles
+system.cpu3.dcache.WriteReq_miss_latency::total      2080000                       # number of WriteReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::cpu3.data       326000                       # number of SwapReq miss cycles
+system.cpu3.dcache.SwapReq_miss_latency::total       326000                       # number of SwapReq miss cycles
+system.cpu3.dcache.demand_miss_latency::cpu3.data      4649000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.demand_miss_latency::total      4649000                       # number of demand (read+write) miss cycles
+system.cpu3.dcache.overall_miss_latency::cpu3.data      4649000                       # number of overall miss cycles
+system.cpu3.dcache.overall_miss_latency::total      4649000                       # number of overall miss cycles
+system.cpu3.dcache.ReadReq_accesses::cpu3.data        41712                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.ReadReq_accesses::total        41712                       # number of ReadReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::cpu3.data        15456                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.WriteReq_accesses::total        15456                       # number of WriteReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::cpu3.data           65                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.SwapReq_accesses::total           65                       # number of SwapReq accesses(hits+misses)
+system.cpu3.dcache.demand_accesses::cpu3.data        57168                       # number of demand (read+write) accesses
+system.cpu3.dcache.demand_accesses::total        57168                       # number of demand (read+write) accesses
+system.cpu3.dcache.overall_accesses::cpu3.data        57168                       # number of overall (read+write) accesses
+system.cpu3.dcache.overall_accesses::total        57168                       # number of overall (read+write) accesses
+system.cpu3.dcache.ReadReq_miss_rate::cpu3.data     0.003764                       # miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_miss_rate::cpu3.data     0.006988                       # miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_miss_rate::cpu3.data     0.830769                       # miss rate for SwapReq accesses
+system.cpu3.dcache.demand_miss_rate::cpu3.data     0.004635                       # miss rate for demand accesses
+system.cpu3.dcache.overall_miss_rate::cpu3.data     0.004635                       # miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 16363.057325                       # average ReadReq miss latency
+system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 19259.259259                       # average WriteReq miss latency
+system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data  6037.037037                       # average SwapReq miss latency
+system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 17543.396226                       # average overall miss latency
+system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 17543.396226                       # average overall miss latency
 system.cpu3.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.dcache.blocked::no_mshrs                0                       # number of cycles access was blocked
@@ -600,34 +740,38 @@ system.cpu3.dcache.avg_blocked_cycles::no_mshrs     no_value
 system.cpu3.dcache.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
-system.cpu3.dcache.writebacks                       1                       # number of writebacks
-system.cpu3.dcache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu3.dcache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu3.dcache.ReadReq_mshr_misses            157                       # number of ReadReq MSHR misses
-system.cpu3.dcache.WriteReq_mshr_misses           108                       # number of WriteReq MSHR misses
-system.cpu3.dcache.SwapReq_mshr_misses             54                       # number of SwapReq MSHR misses
-system.cpu3.dcache.demand_mshr_misses             265                       # number of demand (read+write) MSHR misses
-system.cpu3.dcache.overall_mshr_misses            265                       # number of overall MSHR misses
-system.cpu3.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.dcache.ReadReq_mshr_miss_latency      2098000                       # number of ReadReq MSHR miss cycles
-system.cpu3.dcache.WriteReq_mshr_miss_latency      1756000                       # number of WriteReq MSHR miss cycles
-system.cpu3.dcache.SwapReq_mshr_miss_latency       164000                       # number of SwapReq MSHR miss cycles
-system.cpu3.dcache.demand_mshr_miss_latency      3854000                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.dcache.overall_mshr_miss_latency      3854000                       # number of overall MSHR miss cycles
-system.cpu3.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu3.dcache.ReadReq_mshr_miss_rate     0.003764                       # mshr miss rate for ReadReq accesses
-system.cpu3.dcache.WriteReq_mshr_miss_rate     0.006988                       # mshr miss rate for WriteReq accesses
-system.cpu3.dcache.SwapReq_mshr_miss_rate     0.830769                       # mshr miss rate for SwapReq accesses
-system.cpu3.dcache.demand_mshr_miss_rate     0.004635                       # mshr miss rate for demand accesses
-system.cpu3.dcache.overall_mshr_miss_rate     0.004635                       # mshr miss rate for overall accesses
-system.cpu3.dcache.ReadReq_avg_mshr_miss_latency 13363.057325                       # average ReadReq mshr miss latency
-system.cpu3.dcache.WriteReq_avg_mshr_miss_latency 16259.259259                       # average WriteReq mshr miss latency
-system.cpu3.dcache.SwapReq_avg_mshr_miss_latency  3037.037037                       # average SwapReq mshr miss latency
-system.cpu3.dcache.demand_avg_mshr_miss_latency 14543.396226                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_miss_latency 14543.396226                       # average overall mshr miss latency
-system.cpu3.dcache.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.cpu3.dcache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu3.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.dcache.writebacks::writebacks            1                       # number of writebacks
+system.cpu3.dcache.writebacks::total                1                       # number of writebacks
+system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data          157                       # number of ReadReq MSHR misses
+system.cpu3.dcache.ReadReq_mshr_misses::total          157                       # number of ReadReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data          108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.WriteReq_mshr_misses::total          108                       # number of WriteReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data           54                       # number of SwapReq MSHR misses
+system.cpu3.dcache.SwapReq_mshr_misses::total           54                       # number of SwapReq MSHR misses
+system.cpu3.dcache.demand_mshr_misses::cpu3.data          265                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.demand_mshr_misses::total          265                       # number of demand (read+write) MSHR misses
+system.cpu3.dcache.overall_mshr_misses::cpu3.data          265                       # number of overall MSHR misses
+system.cpu3.dcache.overall_mshr_misses::total          265                       # number of overall MSHR misses
+system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data      2098000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_latency::total      2098000                       # number of ReadReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data      1756000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.WriteReq_mshr_miss_latency::total      1756000                       # number of WriteReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data       164000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.SwapReq_mshr_miss_latency::total       164000                       # number of SwapReq MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data      3854000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.demand_mshr_miss_latency::total      3854000                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data      3854000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.overall_mshr_miss_latency::total      3854000                       # number of overall MSHR miss cycles
+system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data     0.003764                       # mshr miss rate for ReadReq accesses
+system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data     0.006988                       # mshr miss rate for WriteReq accesses
+system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data     0.830769                       # mshr miss rate for SwapReq accesses
+system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data     0.004635                       # mshr miss rate for demand accesses
+system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data     0.004635                       # mshr miss rate for overall accesses
+system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 13363.057325                       # average ReadReq mshr miss latency
+system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 16259.259259                       # average WriteReq mshr miss latency
+system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data  3037.037037                       # average SwapReq mshr miss latency
+system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 14543.396226                       # average overall mshr miss latency
+system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 14543.396226                       # average overall mshr miss latency
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.l2c.replacements                             0                       # number of replacements
 system.l2c.tagsinuse                       353.886259                       # Cycle average of tags in use
@@ -635,142 +779,231 @@ system.l2c.total_refs                            1223                       # To
 system.l2c.sampled_refs                           434                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          2.817972                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                   286.079543                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    57.730360                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                     2.746586                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                     1.731874                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                     5.597896                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.004365                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.000881                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.000042                       # Average percentage of cache occupancy
-system.l2c.occ_percent::3                    0.000026                       # Average percentage of cache occupancy
-system.l2c.occ_percent::4                    0.000085                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                        187                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                        305                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                        365                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                        369                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks            5.597896                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.inst           231.859183                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0.data            54.220360                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.inst            51.601293                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1.data             6.129067                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.inst             1.914986                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2.data             0.831600                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.inst             0.887228                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3.data             0.844646                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.000085                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.inst            0.003538                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0.data            0.000827                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.inst            0.000787                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1.data            0.000094                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.inst            0.000029                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2.data            0.000013                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.inst            0.000014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3.data            0.000013                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.005400                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                182                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                300                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data                  5                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                354                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data                 11                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst                358                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data                 11                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                   1226                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                        9                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks               9                       # number of Writeback hits
 system.l2c.Writeback_hits::total                    9                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                       2                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::0                         187                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                         305                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                         365                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                         369                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.inst                 182                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 300                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 354                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                  11                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 358                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                  11                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                    1226                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                        187                       # number of overall hits
-system.l2c.overall_hits::1                        305                       # number of overall hits
-system.l2c.overall_hits::2                        365                       # number of overall hits
-system.l2c.overall_hits::3                        369                       # number of overall hits
+system.l2c.overall_hits::cpu0.inst                182                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                300                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                354                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                 11                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                358                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                 11                       # number of overall hits
 system.l2c.overall_hits::total                   1226                       # number of overall hits
-system.l2c.ReadReq_misses::0                      351                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                       74                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                       14                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                       11                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.inst              285                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst               66                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data                8                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst               12                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data                2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst                9                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data                2                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                  450                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                    28                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                    12                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                    16                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                    16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0.data            28                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            12                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            16                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            16                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total                72                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                     99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                     15                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2                     14                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3                     14                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data             15                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data             14                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data             14                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total                142                       # number of ReadExReq misses
-system.l2c.demand_misses::0                       450                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                        89                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                        28                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                        25                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.inst               285                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                66                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                23                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                12                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data                16                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 9                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data                16                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                   592                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                      450                       # number of overall misses
-system.l2c.overall_misses::1                       89                       # number of overall misses
-system.l2c.overall_misses::2                       28                       # number of overall misses
-system.l2c.overall_misses::3                       25                       # number of overall misses
+system.l2c.overall_misses::cpu0.inst              285                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               66                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               23                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst               12                       # number of overall misses
+system.l2c.overall_misses::cpu2.data               16                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                9                       # number of overall misses
+system.l2c.overall_misses::cpu3.data               16                       # number of overall misses
 system.l2c.overall_misses::total                  592                       # number of overall misses
-system.l2c.ReadReq_miss_latency              23330000                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency             156000                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency             7385000                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency               30715000                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency              30715000                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                    538                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                    379                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                    379                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3                    380                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0.inst     14822000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu0.data      3432000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.inst      3416000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1.data       413000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.inst       615000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2.data       104000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.inst       429000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3.data        99000                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total       23330000                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1.data        52000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2.data        52000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3.data        52000                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total       156000                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0.data      5148000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1.data       781000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2.data       728000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3.data       728000                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total      7385000                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0.inst     14822000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu0.data      8580000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.inst      3416000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1.data      1194000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.inst       615000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2.data       832000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.inst       429000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3.data       827000                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total        30715000                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0.inst     14822000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu0.data      8580000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.inst      3416000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1.data      1194000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.inst       615000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2.data       832000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.inst       429000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3.data       827000                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total       30715000                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst            366                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data             13                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst            366                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data             13                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            367                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data             13                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total               1676                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0                    9                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks            9                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total                9                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                  30                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                  12                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2                  16                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3                  16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           30                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           12                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           16                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           16                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total              74                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0                   99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                   15                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2                   14                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3                   14                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data           15                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data           14                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data           14                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total              142                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                     637                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                     394                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                     393                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::3                     394                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              28                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             366                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data              27                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             367                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data              27                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total                1818                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                    637                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                    394                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                    393                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::3                    394                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             28                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            366                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data             27                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            367                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data             27                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total               1818                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.652416                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.195251                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.036939                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.028947                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.913554                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.933333                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3                  1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       3.933333                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3                   1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               4                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.706436                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.225888                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.071247                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.063452                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           1.067023                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.706436                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.225888                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.071247                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.063452                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          1.067023                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   66467.236467                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   315270.270270                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   1666428.571429                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3   2120909.090909                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 4169075.169075                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0  5571.428571                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1        13000                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2         9750                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3         9750                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 38071.428571                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 74595.959596                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 492333.333333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2       527500                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3       527500                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 1621929.292929                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    68255.555556                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    345112.359551                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    1096964.285714                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3         1228600                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 2738932.200820                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   68255.555556                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   345112.359551                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   1096964.285714                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3        1228600                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 2738932.200820                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.610278                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.180328                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.615385                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.032787                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.153846                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.024523                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data      0.153846                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.933333                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.610278                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.180328                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.821429                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.032787                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.592593                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.024523                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.592593                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.610278                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.180328                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.821429                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.032787                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.592593                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.024523                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.592593                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0.inst 52007.017544                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu0.data        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51757.575758                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1.data        51625                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.inst        51250                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2.data        52000                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.inst 47666.666667                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3.data        49500                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1.data  4333.333333                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2.data         3250                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3.data         3250                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0.data        52000                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52066.666667                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2.data        52000                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3.data        52000                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0.inst 52007.017544                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu0.data        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.inst 51757.575758                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1.data 51913.043478                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.inst        51250                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2.data        52000                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.inst 47666.666667                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3.data 51687.500000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.inst 52007.017544                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0.data        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.inst 51757.575758                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1.data 51913.043478                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.inst        51250                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2.data        52000                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.inst 47666.666667                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3.data 51687.500000                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
@@ -779,55 +1012,162 @@ system.l2c.avg_blocked_cycles::no_mshrs      no_value                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                               0                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                       20                       # number of ReadReq MSHR hits
-system.l2c.demand_mshr_hits                        20                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                       20                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                    430                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses                  72                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses                  142                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                     572                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                    572                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency         17203000                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency       2880000                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency        5681000                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency          22884000                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency         22884000                       # number of overall MSHR miss cycles
-system.l2c.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         0.799257                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         1.134565                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         1.134565                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3         1.131579                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total     4.199965                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      2.400000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1             6                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2      4.500000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3      4.500000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total    17.400000                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       1.434343                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       9.466667                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2      10.142857                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3      10.142857                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total    31.186724                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          0.897959                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          1.451777                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          1.455471                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3          1.451777                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total      5.256983                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         0.897959                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         1.451777                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         1.455471                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3         1.451777                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total     5.256983                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 40006.976744                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency        40000                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40007.042254                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  40006.993007                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 40006.993007                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_uncacheable_latency     no_value                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.ReadReq_mshr_hits::cpu1.inst             7                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1.data             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2.inst             3                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.inst             8                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3.data             1                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total                20                       # number of ReadReq MSHR hits
+system.l2c.demand_mshr_hits::cpu1.inst              7                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2.inst              3                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.inst              8                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3.data              1                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total                 20                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu1.inst             7                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2.inst             3                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.inst             8                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3.data             1                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total                20                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0.inst          285                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu0.data           66                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.inst           59                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1.data            7                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.inst            9                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2.data            2                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.inst            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3.data            1                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total             430                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0.data           28                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1.data           12                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2.data           16                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3.data           16                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total           72                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0.data           99                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1.data           15                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2.data           14                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3.data           14                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total           142                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0.inst          285                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu0.data          165                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.inst           59                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1.data           22                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.inst            9                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2.data           16                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.inst            1                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3.data           15                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total              572                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0.inst          285                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu0.data          165                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.inst           59                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1.data           22                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.inst            9                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2.data           16                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.inst            1                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3.data           15                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total             572                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0.inst     11402000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu0.data      2640000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.inst      2360000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1.data       280000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.inst       361000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2.data        80000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.inst        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3.data        40000                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total     17203000                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data      1120000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data       480000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data       640000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data       640000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total      2880000                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0.data      3960000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1.data       601000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2.data       560000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3.data       560000                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total      5681000                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.inst     11402000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0.data      6600000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.inst      2360000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1.data       881000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.inst       361000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2.data       640000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.inst        40000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3.data       600000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total     22884000                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.inst     11402000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0.data      6600000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.inst      2360000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1.data       881000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.inst       361000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2.data       640000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.inst        40000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3.data       600000                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total     22884000                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu0.data     0.929577                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1.data     0.538462                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.inst     0.024590                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2.data     0.153846                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3.data     0.076923                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data     0.933333                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3.data            1                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.inst     0.024590                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2.data     0.592593                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3.data     0.555556                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst     0.610278                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data     0.970588                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst     0.161202                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data     0.785714                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.inst     0.024590                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2.data     0.592593                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.inst     0.002725                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3.data     0.555556                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40007.017544                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40111.111111                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst        40000                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data        40000                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data        40000                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.666667                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data        40000                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data        40000                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40007.017544                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40045.454545                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40111.111111                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2.data        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40007.017544                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40045.454545                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40111.111111                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2.data        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.inst        40000                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3.data        40000                       # average overall mshr miss latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index f1d5fb57f7360fbf2ceff4a8ee4c2b5cf1c189ea..dacf2f87f33529482fbe24385cb5f5369a95e368 100644 (file)
@@ -41,6 +41,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[0]
 test=system.l1_cntrl0.sequencer.port[0]
@@ -58,6 +59,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[1]
 test=system.l1_cntrl1.sequencer.port[0]
@@ -75,6 +77,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[2]
 test=system.l1_cntrl2.sequencer.port[0]
@@ -92,6 +95,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[3]
 test=system.l1_cntrl3.sequencer.port[0]
@@ -109,6 +113,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[4]
 test=system.l1_cntrl4.sequencer.port[0]
@@ -126,6 +131,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[5]
 test=system.l1_cntrl5.sequencer.port[0]
@@ -143,6 +149,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[6]
 test=system.l1_cntrl6.sequencer.port[0]
@@ -160,6 +167,7 @@ percent_source_unaligned=50
 percent_uncacheable=0
 progress_interval=10000
 suppress_func_warnings=true
+sys=system
 trace_addr=0
 functional=system.funcmem.port[7]
 test=system.l1_cntrl7.sequencer.port[0]
index 64437a4e39b5628b454e0a2111b6c2f01e31fbe4..e8a51599b6c3855efce927793c205c1228b8a9e8 100644 (file)
@@ -34,27 +34,26 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/12/2012 12:58:05
+Real time: Feb/12/2012 15:36:31
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 110
-Elapsed_time_in_minutes: 1.83333
-Elapsed_time_in_hours: 0.0305556
-Elapsed_time_in_days: 0.00127315
+Elapsed_time_in_seconds: 190
+Elapsed_time_in_minutes: 3.16667
+Elapsed_time_in_hours: 0.0527778
+Elapsed_time_in_days: 0.00219907
 
-Virtual_time_in_seconds: 110.38
-Virtual_time_in_minutes: 1.83967
-Virtual_time_in_hours:   0.0306611
-Virtual_time_in_days:    0.00127755
+Virtual_time_in_seconds: 189.25
+Virtual_time_in_minutes: 3.15417
+Virtual_time_in_hours:   0.0525694
+Virtual_time_in_days:    0.00219039
 
 Ruby_current_time: 22495354
 Ruby_start_time: 0
 Ruby_cycles: 22495354
 
-mbytes_resident: 41.8164
-mbytes_total: 371.512
-resident_ratio: 0.112578
+mbytes_resident: 0
+mbytes_total: 0
 
 ruby_cycles_executed: [ 22495355 22495355 22495355 22495355 22495355 22495355 22495355 22495355 ]
 
@@ -116,13 +115,13 @@ Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 3280807 average: 0.508064 |
 Resource Usage
 --------------
 page_size: 4096
-user_time: 110
+user_time: 188
 system_time: 0
-page_reclaims: 11719
-page_faults: 18
+page_reclaims: 12571
+page_faults: 0
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 1
+block_outputs: 44
 
 Network Stats
 -------------
index 1577dfd4791117944e31dccdc2b6a400ad3b0778..f74c8ffd68eea2da9aa1f79b2c4c438fe441781c 100755 (executable)
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 12:56:01
-gem5 started Feb 12 2012 12:56:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
index 04704faf44b9aedd3f438e379b6b3dc16e30ab03..1bc6a2ebbc56fc8f5e11032940d8dd4f29eab584 100644 (file)
@@ -4,9 +4,9 @@ sim_seconds                                  0.022495                       # Nu
 sim_ticks                                    22495354                       # Number of ticks simulated
 final_tick                                   22495354                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 204320                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 380432                       # Number of bytes of host memory used
-host_seconds                                   110.10                       # Real time elapsed on the host
+host_tick_rate                                 118487                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 398520                       # Number of bytes of host memory used
+host_seconds                                   189.86                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory
index ac8d82ede216c301ab9896e75516b4b97b53b090..1dd8fc1b6d67d682593b971e1bcf0a7ffd522f6c 100644 (file)
@@ -1,6 +1,7 @@
 [root]
 type=Root
 children=system
+full_system=false
 time_sync_enable=false
 time_sync_period=100000000000
 time_sync_spin_threshold=100000000
@@ -8,10 +9,16 @@ time_sync_spin_threshold=100000000
 [system]
 type=System
 children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem l2c membus physmem toL2Bus
+boot_osflags=a
+init_param=0
+kernel=
+load_addr_mask=1099511627775
 mem_mode=timing
 memories=system.physmem system.funcmem
 num_work_ids=16
 physmem=system.physmem
+readfile=
+symbolfile=
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -35,6 +42,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[0]
 test=system.cpu0.l1c.cpu_side
@@ -50,20 +58,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -85,6 +86,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[1]
 test=system.cpu1.l1c.cpu_side
@@ -100,20 +102,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -135,6 +130,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[2]
 test=system.cpu2.l1c.cpu_side
@@ -150,20 +146,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -185,6 +174,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[3]
 test=system.cpu3.l1c.cpu_side
@@ -200,20 +190,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -235,6 +218,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[4]
 test=system.cpu4.l1c.cpu_side
@@ -250,20 +234,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -285,6 +262,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[5]
 test=system.cpu5.l1c.cpu_side
@@ -300,20 +278,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -335,6 +306,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[6]
 test=system.cpu6.l1c.cpu_side
@@ -350,20 +322,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -385,6 +350,7 @@ percent_source_unaligned=50
 percent_uncacheable=10
 progress_interval=10000
 suppress_func_warnings=false
+sys=system
 trace_addr=0
 functional=system.funcmem.port[7]
 test=system.cpu7.l1c.cpu_side
@@ -400,20 +366,13 @@ is_top_level=true
 latency=1000
 max_miss_count=0
 mshrs=12
-num_cpus=1
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=32768
 subblock_size=0
+system=system
 tgts_per_mshr=8
 trace_addr=0
 two_queue=false
@@ -442,20 +401,13 @@ is_top_level=false
 latency=10000
 max_miss_count=0
 mshrs=92
-num_cpus=8
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=100000
 prefetch_on_access=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
+prefetcher=Null
 prioritizeRequests=false
 repl=Null
 size=65536
 subblock_size=0
+system=system
 tgts_per_mshr=16
 trace_addr=0
 two_queue=false
index c76c335768e62ee32eb8de6a7de5b676978a65c6..c89b6224383d0115c1973bca7de04f7bdda58daa 100755 (executable)
@@ -1,10 +1,10 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2012 04:48:33
-gem5 started Jan 23 2012 04:59:28
+gem5 compiled Feb 11 2012 13:05:17
+gem5 started Feb 11 2012 13:09:36
 gem5 executing on zizzer
-command line: build/ALPHA_SE/gem5.opt -d build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/opt/quick/50.memtest/alpha/linux/memtest
+command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/fast/quick/se/50.memtest/alpha/linux/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 263488655 because maximum number of loads reached
index 82bd7a1b0d844daf4b86b06c48ca6dde24fc8dd0..8183eaaf7b6b5c841983cd65bb2674ee631eab62 100644 (file)
@@ -4,9 +4,9 @@ sim_seconds                                  0.000263                       # Nu
 sim_ticks                                   263488655                       # Number of ticks simulated
 final_tick                                  263488655                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_tick_rate                                1768401                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 335780                       # Number of bytes of host memory used
-host_seconds                                   149.00                       # Real time elapsed on the host
+host_tick_rate                                1938715                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 338552                       # Number of bytes of host memory used
+host_seconds                                   135.91                       # Real time elapsed on the host
 system.physmem.bytes_read                     4057580                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                  2644316                       # Number of bytes written to this memory
@@ -28,258 +28,289 @@ system.l2c.total_refs                          139150                       # To
 system.l2c.sampled_refs                         77525                       # Sample count of references to valid blocks.
 system.l2c.avg_refs                          1.794905                       # Average number of references to valid blocks.
 system.l2c.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.occ_blocks::0                    24.077198                       # Average occupied blocks per context
-system.l2c.occ_blocks::1                    23.899612                       # Average occupied blocks per context
-system.l2c.occ_blocks::2                    23.566419                       # Average occupied blocks per context
-system.l2c.occ_blocks::3                    24.461210                       # Average occupied blocks per context
-system.l2c.occ_blocks::4                    24.025606                       # Average occupied blocks per context
-system.l2c.occ_blocks::5                    23.167376                       # Average occupied blocks per context
-system.l2c.occ_blocks::6                    23.494200                       # Average occupied blocks per context
-system.l2c.occ_blocks::7                    23.002994                       # Average occupied blocks per context
-system.l2c.occ_blocks::8                   468.019905                       # Average occupied blocks per context
-system.l2c.occ_percent::0                    0.023513                       # Average percentage of cache occupancy
-system.l2c.occ_percent::1                    0.023339                       # Average percentage of cache occupancy
-system.l2c.occ_percent::2                    0.023014                       # Average percentage of cache occupancy
-system.l2c.occ_percent::3                    0.023888                       # Average percentage of cache occupancy
-system.l2c.occ_percent::4                    0.023463                       # Average percentage of cache occupancy
-system.l2c.occ_percent::5                    0.022624                       # Average percentage of cache occupancy
-system.l2c.occ_percent::6                    0.022944                       # Average percentage of cache occupancy
-system.l2c.occ_percent::7                    0.022464                       # Average percentage of cache occupancy
-system.l2c.occ_percent::8                    0.457051                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::0                      10466                       # number of ReadReq hits
-system.l2c.ReadReq_hits::1                      10370                       # number of ReadReq hits
-system.l2c.ReadReq_hits::2                      10579                       # number of ReadReq hits
-system.l2c.ReadReq_hits::3                      10469                       # number of ReadReq hits
-system.l2c.ReadReq_hits::4                      10390                       # number of ReadReq hits
-system.l2c.ReadReq_hits::5                      10384                       # number of ReadReq hits
-system.l2c.ReadReq_hits::6                      10590                       # number of ReadReq hits
-system.l2c.ReadReq_hits::7                      10463                       # number of ReadReq hits
+system.l2c.occ_blocks::writebacks          468.019905                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu0                 24.077198                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu1                 23.899612                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu2                 23.566419                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu3                 24.461210                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu4                 24.025606                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu5                 23.167376                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu6                 23.494200                       # Average occupied blocks per requestor
+system.l2c.occ_blocks::cpu7                 23.002994                       # Average occupied blocks per requestor
+system.l2c.occ_percent::writebacks           0.457051                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu0                 0.023513                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu1                 0.023339                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu2                 0.023014                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu3                 0.023888                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu4                 0.023463                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu5                 0.022624                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu6                 0.022944                       # Average percentage of cache occupancy
+system.l2c.occ_percent::cpu7                 0.022464                       # Average percentage of cache occupancy
+system.l2c.occ_percent::total                0.642299                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0                   10466                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1                   10370                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2                   10579                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3                   10469                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu4                   10390                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu5                   10384                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu6                   10590                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu7                   10463                       # number of ReadReq hits
 system.l2c.ReadReq_hits::total                  83711                       # number of ReadReq hits
-system.l2c.Writeback_hits::0                    94038                       # number of Writeback hits
+system.l2c.Writeback_hits::writebacks           94038                       # number of Writeback hits
 system.l2c.Writeback_hits::total                94038                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::0                     457                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::1                     419                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::2                     446                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::3                     463                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::4                     430                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::5                     463                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::6                     415                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::7                     411                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu0                  457                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1                  419                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2                  446                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3                  463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4                  430                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5                  463                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6                  415                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7                  411                       # number of UpgradeReq hits
 system.l2c.UpgradeReq_hits::total                3504                       # number of UpgradeReq hits
-system.l2c.ReadExReq_hits::0                     2829                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::1                     2819                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::2                     2901                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::3                     2765                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::4                     2827                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::5                     2929                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::6                     2882                       # number of ReadExReq hits
-system.l2c.ReadExReq_hits::7                     2913                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu0                  2829                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1                  2819                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2                  2901                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3                  2765                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu4                  2827                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu5                  2929                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu6                  2882                       # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu7                  2913                       # number of ReadExReq hits
 system.l2c.ReadExReq_hits::total                22865                       # number of ReadExReq hits
-system.l2c.demand_hits::0                       13295                       # number of demand (read+write) hits
-system.l2c.demand_hits::1                       13189                       # number of demand (read+write) hits
-system.l2c.demand_hits::2                       13480                       # number of demand (read+write) hits
-system.l2c.demand_hits::3                       13234                       # number of demand (read+write) hits
-system.l2c.demand_hits::4                       13217                       # number of demand (read+write) hits
-system.l2c.demand_hits::5                       13313                       # number of demand (read+write) hits
-system.l2c.demand_hits::6                       13472                       # number of demand (read+write) hits
-system.l2c.demand_hits::7                       13376                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0                    13295                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1                    13189                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2                    13480                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3                    13234                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu4                    13217                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu5                    13313                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu6                    13472                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu7                    13376                       # number of demand (read+write) hits
 system.l2c.demand_hits::total                  106576                       # number of demand (read+write) hits
-system.l2c.overall_hits::0                      13295                       # number of overall hits
-system.l2c.overall_hits::1                      13189                       # number of overall hits
-system.l2c.overall_hits::2                      13480                       # number of overall hits
-system.l2c.overall_hits::3                      13234                       # number of overall hits
-system.l2c.overall_hits::4                      13217                       # number of overall hits
-system.l2c.overall_hits::5                      13313                       # number of overall hits
-system.l2c.overall_hits::6                      13472                       # number of overall hits
-system.l2c.overall_hits::7                      13376                       # number of overall hits
+system.l2c.overall_hits::cpu0                   13295                       # number of overall hits
+system.l2c.overall_hits::cpu1                   13189                       # number of overall hits
+system.l2c.overall_hits::cpu2                   13480                       # number of overall hits
+system.l2c.overall_hits::cpu3                   13234                       # number of overall hits
+system.l2c.overall_hits::cpu4                   13217                       # number of overall hits
+system.l2c.overall_hits::cpu5                   13313                       # number of overall hits
+system.l2c.overall_hits::cpu6                   13472                       # number of overall hits
+system.l2c.overall_hits::cpu7                   13376                       # number of overall hits
 system.l2c.overall_hits::total                 106576                       # number of overall hits
-system.l2c.ReadReq_misses::0                     5163                       # number of ReadReq misses
-system.l2c.ReadReq_misses::1                     5186                       # number of ReadReq misses
-system.l2c.ReadReq_misses::2                     5173                       # number of ReadReq misses
-system.l2c.ReadReq_misses::3                     5223                       # number of ReadReq misses
-system.l2c.ReadReq_misses::4                     5193                       # number of ReadReq misses
-system.l2c.ReadReq_misses::5                     5114                       # number of ReadReq misses
-system.l2c.ReadReq_misses::6                     5145                       # number of ReadReq misses
-system.l2c.ReadReq_misses::7                     4996                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0                  5163                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1                  5186                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2                  5173                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3                  5223                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu4                  5193                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu5                  5114                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu6                  5145                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu7                  4996                       # number of ReadReq misses
 system.l2c.ReadReq_misses::total                41193                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::0                  1644                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::1                  1598                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::2                  1617                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::3                  1610                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::4                  1586                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::5                  1626                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::6                  1624                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::7                  1582                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu0               1644                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1               1598                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2               1617                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3               1610                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4               1586                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5               1626                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6               1624                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu7               1582                       # number of UpgradeReq misses
 system.l2c.UpgradeReq_misses::total             12887                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::0                   5539                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::1                   5808                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::2                   5466                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::3                   5538                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::4                   5599                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::5                   5507                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::6                   5800                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::7                   5643                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu0                5539                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1                5808                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2                5466                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3                5538                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu4                5599                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu5                5507                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu6                5800                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu7                5643                       # number of ReadExReq misses
 system.l2c.ReadExReq_misses::total              44900                       # number of ReadExReq misses
-system.l2c.demand_misses::0                     10702                       # number of demand (read+write) misses
-system.l2c.demand_misses::1                     10994                       # number of demand (read+write) misses
-system.l2c.demand_misses::2                     10639                       # number of demand (read+write) misses
-system.l2c.demand_misses::3                     10761                       # number of demand (read+write) misses
-system.l2c.demand_misses::4                     10792                       # number of demand (read+write) misses
-system.l2c.demand_misses::5                     10621                       # number of demand (read+write) misses
-system.l2c.demand_misses::6                     10945                       # number of demand (read+write) misses
-system.l2c.demand_misses::7                     10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0                  10702                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1                  10994                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2                  10639                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3                  10761                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu4                  10792                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu5                  10621                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu6                  10945                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu7                  10639                       # number of demand (read+write) misses
 system.l2c.demand_misses::total                 86093                       # number of demand (read+write) misses
-system.l2c.overall_misses::0                    10702                       # number of overall misses
-system.l2c.overall_misses::1                    10994                       # number of overall misses
-system.l2c.overall_misses::2                    10639                       # number of overall misses
-system.l2c.overall_misses::3                    10761                       # number of overall misses
-system.l2c.overall_misses::4                    10792                       # number of overall misses
-system.l2c.overall_misses::5                    10621                       # number of overall misses
-system.l2c.overall_misses::6                    10945                       # number of overall misses
-system.l2c.overall_misses::7                    10639                       # number of overall misses
+system.l2c.overall_misses::cpu0                 10702                       # number of overall misses
+system.l2c.overall_misses::cpu1                 10994                       # number of overall misses
+system.l2c.overall_misses::cpu2                 10639                       # number of overall misses
+system.l2c.overall_misses::cpu3                 10761                       # number of overall misses
+system.l2c.overall_misses::cpu4                 10792                       # number of overall misses
+system.l2c.overall_misses::cpu5                 10621                       # number of overall misses
+system.l2c.overall_misses::cpu6                 10945                       # number of overall misses
+system.l2c.overall_misses::cpu7                 10639                       # number of overall misses
 system.l2c.overall_misses::total                86093                       # number of overall misses
-system.l2c.ReadReq_miss_latency            2043791615                       # number of ReadReq miss cycles
-system.l2c.UpgradeReq_miss_latency          261408598                       # number of UpgradeReq miss cycles
-system.l2c.ReadExReq_miss_latency          2236788368                       # number of ReadExReq miss cycles
-system.l2c.demand_miss_latency             4280579983                       # number of demand (read+write) miss cycles
-system.l2c.overall_miss_latency            4280579983                       # number of overall miss cycles
-system.l2c.ReadReq_accesses::0                  15629                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::1                  15556                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::2                  15752                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::3                  15692                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::4                  15583                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::5                  15498                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::6                  15735                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::7                  15459                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_miss_latency::cpu0       256196985                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu1       257287128                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu2       256567876                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu3       259144977                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu4       257572428                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu5       253877351                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu6       255352806                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::cpu7       247792064                       # number of ReadReq miss cycles
+system.l2c.ReadReq_miss_latency::total     2043791615                       # number of ReadReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu0     32636387                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu1     33737386                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu2     32855972                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu3     32255171                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu4     31405634                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu5     33663875                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu6     32311068                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::cpu7     32543105                       # number of UpgradeReq miss cycles
+system.l2c.UpgradeReq_miss_latency::total    261408598                       # number of UpgradeReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu0     275716926                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu1     289198618                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu2     271873258                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu3     276122659                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu4     279168031                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu5     274243794                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu6     289241297                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::cpu7     281223785                       # number of ReadExReq miss cycles
+system.l2c.ReadExReq_miss_latency::total   2236788368                       # number of ReadExReq miss cycles
+system.l2c.demand_miss_latency::cpu0        531913911                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu1        546485746                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu2        528441134                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu3        535267636                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu4        536740459                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu5        528121145                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu6        544594103                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::cpu7        529015849                       # number of demand (read+write) miss cycles
+system.l2c.demand_miss_latency::total      4280579983                       # number of demand (read+write) miss cycles
+system.l2c.overall_miss_latency::cpu0       531913911                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu1       546485746                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu2       528441134                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu3       535267636                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu4       536740459                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu5       528121145                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu6       544594103                       # number of overall miss cycles
+system.l2c.overall_miss_latency::cpu7       529015849                       # number of overall miss cycles
+system.l2c.overall_miss_latency::total     4280579983                       # number of overall miss cycles
+system.l2c.ReadReq_accesses::cpu0               15629                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1               15556                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2               15752                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3               15692                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu4               15583                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu5               15498                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu6               15735                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu7               15459                       # number of ReadReq accesses(hits+misses)
 system.l2c.ReadReq_accesses::total             124904                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::0                94038                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks        94038                       # number of Writeback accesses(hits+misses)
 system.l2c.Writeback_accesses::total            94038                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::0                2101                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::1                2017                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::2                2063                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::3                2073                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::4                2016                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::5                2089                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::6                2039                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::7                1993                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0             2101                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1             2017                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2             2063                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3             2073                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu4             2016                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu5             2089                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu6             2039                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu7             1993                       # number of UpgradeReq accesses(hits+misses)
 system.l2c.UpgradeReq_accesses::total           16391                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::0                 8368                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::1                 8627                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::2                 8367                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::3                 8303                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::4                 8426                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::5                 8436                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::6                 8682                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::7                 8556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0              8368                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1              8627                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2              8367                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3              8303                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu4              8426                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu5              8436                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu6              8682                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu7              8556                       # number of ReadExReq accesses(hits+misses)
 system.l2c.ReadExReq_accesses::total            67765                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::0                   23997                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::1                   24183                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::2                   24119                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::3                   23995                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::4                   24009                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::5                   23934                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::6                   24417                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::7                   24015                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0                23997                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1                24183                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2                24119                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3                23995                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu4                24009                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu5                23934                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu6                24417                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu7                24015                       # number of demand (read+write) accesses
 system.l2c.demand_accesses::total              192669                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::0                  23997                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::1                  24183                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::2                  24119                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::3                  23995                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::4                  24009                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::5                  23934                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::6                  24417                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::7                  24015                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0               23997                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1               24183                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2               24119                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3               23995                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu4               24009                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu5               23934                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu6               24417                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu7               24015                       # number of overall (read+write) accesses
 system.l2c.overall_accesses::total             192669                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::0              0.330347                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::1              0.333376                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::2              0.328403                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::3              0.332845                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::4              0.333248                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::5              0.329978                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::6              0.326978                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::7              0.323177                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          2.638352                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::0           0.782485                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::1           0.792266                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::2           0.783810                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::3           0.776652                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::4           0.786706                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::5           0.778363                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::6           0.796469                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::7           0.793778                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       6.290529                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::0            0.661926                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::1            0.673235                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::2            0.653281                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::3            0.666988                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::4            0.664491                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::5            0.652798                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::6            0.668049                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::7            0.659537                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total        5.300305                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::0               0.445972                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::1               0.454617                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::2               0.441105                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::3               0.448468                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::4               0.449498                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::5               0.443762                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::6               0.448253                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::7               0.443015                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           3.574690                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::0              0.445972                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::1              0.454617                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::2              0.441105                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::3              0.448468                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::4              0.449498                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::5              0.443762                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::6              0.448253                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::7              0.443015                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          3.574690                       # miss rate for overall accesses
-system.l2c.ReadReq_avg_miss_latency::0   395853.498935                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::1   394097.881797                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::2   395088.268896                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::3   391306.072181                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::4   393566.650298                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::5   399646.385413                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::6   397238.409135                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::7   409085.591473                       # average ReadReq miss latency
-system.l2c.ReadReq_avg_miss_latency::total 3175882.758128                       # average ReadReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::0 159007.663017                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::1 163584.854819                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::2 161662.707483                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::3 162365.588820                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::4 164822.571248                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::5 160767.895449                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::6 160965.885468                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::7 165239.316056                       # average UpgradeReq miss latency
-system.l2c.UpgradeReq_avg_miss_latency::total 1298416.482359                       # average UpgradeReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::0 403825.305651                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::1 385121.964187                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::2 409218.508599                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::3 403898.224630                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::4 399497.833184                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::5 406171.848193                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::6 385653.166897                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::7 396382.840333                       # average ReadExReq miss latency
-system.l2c.ReadExReq_avg_miss_latency::total 3189769.691674                       # average ReadExReq miss latency
-system.l2c.demand_avg_miss_latency::0    399979.441506                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::1    389356.010824                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::2    402347.963436                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::3    397786.449494                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::4    396643.808655                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::5    403029.844930                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::6    391099.130471                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::7    402347.963436                       # average overall miss latency
-system.l2c.demand_avg_miss_latency::total 3182590.612752                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::0   399979.441506                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::1   389356.010824                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::2   402347.963436                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::3   397786.449494                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::4   396643.808655                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::5   403029.844930                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::6   391099.130471                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::7   402347.963436                       # average overall miss latency
-system.l2c.overall_avg_miss_latency::total 3182590.612752                       # average overall miss latency
+system.l2c.ReadReq_miss_rate::cpu0           0.330347                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1           0.333376                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2           0.328403                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3           0.332845                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu4           0.333248                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu5           0.329978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu6           0.326978                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu7           0.323177                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0        0.782485                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1        0.792266                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2        0.783810                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3        0.776652                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu4        0.786706                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu5        0.778363                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu6        0.796469                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu7        0.793778                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0         0.661926                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1         0.673235                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2         0.653281                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3         0.666988                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu4         0.664491                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu5         0.652798                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu6         0.668049                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu7         0.659537                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0            0.445972                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1            0.454617                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2            0.441105                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3            0.448468                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu4            0.449498                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu5            0.443762                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu6            0.448253                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu7            0.443015                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0           0.445972                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1           0.454617                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2           0.441105                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3           0.448468                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu4           0.449498                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu5           0.443762                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu6           0.448253                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu7           0.443015                       # miss rate for overall accesses
+system.l2c.ReadReq_avg_miss_latency::cpu0 49621.728646                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu1 49611.864250                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu2 49597.501643                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu3 49616.116600                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu4 49599.928365                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu5 49643.596206                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu6 49631.254810                       # average ReadReq miss latency
+system.l2c.ReadReq_avg_miss_latency::cpu7 49598.091273                       # average ReadReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu0 19851.816910                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu1 21112.256571                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu2 20319.092146                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu3 20034.267702                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu4 19801.786885                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu5 20703.490160                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu6 19895.977833                       # average UpgradeReq miss latency
+system.l2c.UpgradeReq_avg_miss_latency::cpu7 20570.862832                       # average UpgradeReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu0 49777.383282                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu1 49793.150482                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu2 49738.978778                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu3 49859.635067                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu4 49860.337739                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu5 49799.127293                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu6 49869.189138                       # average ReadExReq miss latency
+system.l2c.ReadExReq_avg_miss_latency::cpu7 49835.864788                       # average ReadExReq miss latency
+system.l2c.demand_avg_miss_latency::cpu0 49702.290320                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu1 49707.635619                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu2 49670.188364                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu3 49741.440015                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu4 49735.031412                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu5 49724.239243                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu6 49757.341526                       # average overall miss latency
+system.l2c.demand_avg_miss_latency::cpu7 49724.208008                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu0 49702.290320                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu1 49707.635619                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu2 49670.188364                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu3 49741.440015                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu4 49735.031412                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu5 49724.239243                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu6 49757.341526                       # average overall miss latency
+system.l2c.overall_avg_miss_latency::cpu7 49724.208008                       # average overall miss latency
 system.l2c.blocked_cycles::no_mshrs             97509                       # number of cycles access was blocked
 system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
 system.l2c.blocked::no_mshrs                       14                       # number of cycles access was blocked
@@ -288,119 +319,327 @@ system.l2c.avg_blocked_cycles::no_mshrs   6964.928571                       # av
 system.l2c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.l2c.fast_writes                              0                       # number of fast writes performed
 system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.writebacks                           40644                       # number of writebacks
-system.l2c.ReadReq_mshr_hits                      961                       # number of ReadReq MSHR hits
-system.l2c.UpgradeReq_mshr_hits                    49                       # number of UpgradeReq MSHR hits
-system.l2c.ReadExReq_mshr_hits                    507                       # number of ReadExReq MSHR hits
-system.l2c.demand_mshr_hits                      1468                       # number of demand (read+write) MSHR hits
-system.l2c.overall_mshr_hits                     1468                       # number of overall MSHR hits
-system.l2c.ReadReq_mshr_misses                  40232                       # number of ReadReq MSHR misses
-system.l2c.UpgradeReq_mshr_misses               12838                       # number of UpgradeReq MSHR misses
-system.l2c.ReadExReq_mshr_misses                44393                       # number of ReadExReq MSHR misses
-system.l2c.demand_mshr_misses                   84625                       # number of demand (read+write) MSHR misses
-system.l2c.overall_mshr_misses                  84625                       # number of overall MSHR misses
-system.l2c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.l2c.ReadReq_mshr_miss_latency       1609227416                       # number of ReadReq MSHR miss cycles
-system.l2c.UpgradeReq_mshr_miss_latency     513507057                       # number of UpgradeReq MSHR miss cycles
-system.l2c.ReadExReq_mshr_miss_latency     1775748338                       # number of ReadExReq MSHR miss cycles
-system.l2c.demand_mshr_miss_latency        3384975754                       # number of demand (read+write) MSHR miss cycles
-system.l2c.overall_mshr_miss_latency       3384975754                       # number of overall MSHR miss cycles
-system.l2c.ReadReq_mshr_uncacheable_latency   3189139994                       # number of ReadReq MSHR uncacheable cycles
-system.l2c.WriteReq_mshr_uncacheable_latency   1723903484                       # number of WriteReq MSHR uncacheable cycles
-system.l2c.overall_mshr_uncacheable_latency   4913043478                       # number of overall MSHR uncacheable cycles
-system.l2c.ReadReq_mshr_miss_rate::0         2.574189                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::1         2.586269                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::2         2.554088                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::3         2.563854                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::4         2.581788                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::5         2.595948                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::6         2.556848                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::7         2.602497                       # mshr miss rate for ReadReq accesses
-system.l2c.ReadReq_mshr_miss_rate::total    20.615481                       # mshr miss rate for ReadReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::0      6.110424                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::1      6.364898                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::2      6.222976                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::3      6.192957                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::4      6.368056                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::5      6.145524                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::6      6.296224                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::7      6.441545                       # mshr miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_mshr_miss_rate::total    50.142604                       # mshr miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::0       5.305091                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::1       5.145821                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::2       5.305725                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::3       5.346622                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::4       5.268573                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::5       5.262328                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::6       5.113223                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::7       5.188523                       # mshr miss rate for ReadExReq accesses
-system.l2c.ReadExReq_mshr_miss_rate::total    41.935906                       # mshr miss rate for ReadExReq accesses
-system.l2c.demand_mshr_miss_rate::0          3.526482                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::1          3.499359                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::2          3.508645                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::3          3.526776                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::4          3.524720                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::5          3.535765                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::6          3.465823                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::7          3.523839                       # mshr miss rate for demand accesses
-system.l2c.demand_mshr_miss_rate::total     28.111410                       # mshr miss rate for demand accesses
-system.l2c.overall_mshr_miss_rate::0         3.526482                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::1         3.499359                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::2         3.508645                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::3         3.526776                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::4         3.524720                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::5         3.535765                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::6         3.465823                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::7         3.523839                       # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total    28.111410                       # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency 39998.692981                       # average ReadReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency 39998.991821                       # average UpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency 40000.638344                       # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency  39999.713489                       # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency 39999.713489                       # average overall mshr miss latency
-system.l2c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.l2c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.l2c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.l2c.mshr_cap_events                          0                       # number of times MSHR cap was activated
-system.l2c.soft_prefetch_mshr_full                  0                       # number of mshr full events for SW prefetching instrutions
+system.l2c.writebacks::writebacks               40644                       # number of writebacks
+system.l2c.writebacks::total                    40644                       # number of writebacks
+system.l2c.ReadReq_mshr_hits::cpu0                118                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu1                121                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu2                142                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu3                119                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu4                123                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu5                114                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu6                110                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::cpu7                114                       # number of ReadReq MSHR hits
+system.l2c.ReadReq_mshr_hits::total               961                       # number of ReadReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu0               7                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu1               8                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu2               5                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu3               7                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu4               6                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu5               5                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu6               5                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::cpu7               6                       # number of UpgradeReq MSHR hits
+system.l2c.UpgradeReq_mshr_hits::total             49                       # number of UpgradeReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu0               68                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu1               72                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu2               73                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu3               47                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu4               55                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu5               72                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu6               58                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::cpu7               62                       # number of ReadExReq MSHR hits
+system.l2c.ReadExReq_mshr_hits::total             507                       # number of ReadExReq MSHR hits
+system.l2c.demand_mshr_hits::cpu0                 186                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu1                 193                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu2                 215                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu3                 166                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu4                 178                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu5                 186                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu6                 168                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::cpu7                 176                       # number of demand (read+write) MSHR hits
+system.l2c.demand_mshr_hits::total               1468                       # number of demand (read+write) MSHR hits
+system.l2c.overall_mshr_hits::cpu0                186                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu1                193                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu2                215                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu3                166                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu4                178                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu5                186                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu6                168                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::cpu7                176                       # number of overall MSHR hits
+system.l2c.overall_mshr_hits::total              1468                       # number of overall MSHR hits
+system.l2c.ReadReq_mshr_misses::cpu0             5045                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu1             5065                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu2             5031                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu3             5104                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu4             5070                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu5             5000                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu6             5035                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::cpu7             4882                       # number of ReadReq MSHR misses
+system.l2c.ReadReq_mshr_misses::total           40232                       # number of ReadReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu0          1637                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu1          1590                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu2          1612                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu3          1603                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu4          1580                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu5          1621                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu6          1619                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::cpu7          1576                       # number of UpgradeReq MSHR misses
+system.l2c.UpgradeReq_mshr_misses::total        12838                       # number of UpgradeReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu0           5471                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu1           5736                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu2           5393                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu3           5491                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu4           5544                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu5           5435                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu6           5742                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::cpu7           5581                       # number of ReadExReq MSHR misses
+system.l2c.ReadExReq_mshr_misses::total         44393                       # number of ReadExReq MSHR misses
+system.l2c.demand_mshr_misses::cpu0             10516                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu1             10801                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu2             10424                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu3             10595                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu4             10614                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu5             10435                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu6             10777                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::cpu7             10463                       # number of demand (read+write) MSHR misses
+system.l2c.demand_mshr_misses::total            84625                       # number of demand (read+write) MSHR misses
+system.l2c.overall_mshr_misses::cpu0            10516                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu1            10801                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu2            10424                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu3            10595                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu4            10614                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu5            10435                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu6            10777                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::cpu7            10463                       # number of overall MSHR misses
+system.l2c.overall_mshr_misses::total           84625                       # number of overall MSHR misses
+system.l2c.ReadReq_mshr_miss_latency::cpu0    201814482                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu1    202614244                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu2    201254484                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu3    204173248                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu4    202773617                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu5    200011523                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu6    201333402                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::cpu7    195252416                       # number of ReadReq MSHR miss cycles
+system.l2c.ReadReq_mshr_miss_latency::total   1609227416                       # number of ReadReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu0     65483665                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu1     63563227                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu2     64483276                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu3     64122909                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu4     63203179                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu5     64843827                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu6     64763487                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::cpu7     63043487                       # number of UpgradeReq MSHR miss cycles
+system.l2c.UpgradeReq_mshr_miss_latency::total    513507057                       # number of UpgradeReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu0    218853383                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu1    229413457                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu2    215692606                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu3    219654421                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu4    221773547                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu5    217413717                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu6    229694076                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::cpu7    223253131                       # number of ReadExReq MSHR miss cycles
+system.l2c.ReadExReq_mshr_miss_latency::total   1775748338                       # number of ReadExReq MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu0    420667865                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu1    432027701                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu2    416947090                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu3    423827669                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu4    424547164                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu5    417425240                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu6    431027478                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::cpu7    418505547                       # number of demand (read+write) MSHR miss cycles
+system.l2c.demand_mshr_miss_latency::total   3384975754                       # number of demand (read+write) MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu0    420667865                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu1    432027701                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu2    416947090                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu3    423827669                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu4    424547164                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu5    417425240                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu6    431027478                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::cpu7    418505547                       # number of overall MSHR miss cycles
+system.l2c.overall_mshr_miss_latency::total   3384975754                       # number of overall MSHR miss cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu0    400422345                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu1    391061487                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu2    401502890                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu3    396621827                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu4    400743471                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu5    404102628                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu6    391101960                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::cpu7    403583386                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_uncacheable_latency::total   3189139994                       # number of ReadReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu0    215688086                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu1    217048117                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu2    213007261                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu3    216128145                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu4    218848364                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu5    214487951                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu6    216767566                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::cpu7    211927994                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.WriteReq_mshr_uncacheable_latency::total   1723903484                       # number of WriteReq MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu0    616110431                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu1    608109604                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu2    614510151                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu3    612749972                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu4    619591835                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu5    618590579                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu6    607869526                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::cpu7    615511380                       # number of overall MSHR uncacheable cycles
+system.l2c.overall_mshr_uncacheable_latency::total   4913043478                       # number of overall MSHR uncacheable cycles
+system.l2c.ReadReq_mshr_miss_rate::cpu0      0.322797                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu1      0.325598                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu2      0.319388                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu3      0.325261                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu4      0.325355                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu5      0.322622                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu6      0.319987                       # mshr miss rate for ReadReq accesses
+system.l2c.ReadReq_mshr_miss_rate::cpu7      0.315803                       # mshr miss rate for ReadReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu0     0.779153                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1     0.788299                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2     0.781386                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3     0.773275                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4     0.783730                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5     0.775969                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6     0.794017                       # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7     0.790768                       # mshr miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu0     0.653800                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu1     0.664889                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu2     0.644556                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu3     0.661327                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu4     0.657963                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu5     0.644263                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu6     0.661368                       # mshr miss rate for ReadExReq accesses
+system.l2c.ReadExReq_mshr_miss_rate::cpu7     0.652291                       # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0       0.438221                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1       0.446636                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu2       0.432190                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu3       0.441550                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu4       0.442084                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu5       0.435991                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu6       0.441373                       # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu7       0.435686                       # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0      0.438221                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1      0.446636                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu2      0.432190                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu3      0.441550                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu4      0.442084                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu5      0.435991                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu6      0.441373                       # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu7      0.435686                       # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 40002.870565                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 40002.812241                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 40002.878951                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 40002.595611                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 39994.796252                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 40002.304600                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 39986.772989                       # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 39994.349857                       # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40002.238852                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 39976.872327                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40002.032258                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40001.814722                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40002.012025                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40002.360888                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40002.153799                       # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40002.212563                       # average UpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 40002.446171                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 39995.372559                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 39994.920452                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 40002.626298                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 40002.443543                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 40002.523827                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 40002.451411                       # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 40002.352804                       # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0 40002.649772                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1 39998.861309                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu2 39998.761512                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu3 40002.611515                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu4 39998.790654                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu5 40002.418783                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu6 39995.126473                       # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu7 39998.618656                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0 40002.649772                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1 39998.861309                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu2 39998.761512                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu3 40002.611515                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu4 39998.790654                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu5 40002.418783                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu6 39995.126473                       # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu7 39998.618656                       # average overall mshr miss latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.cpu0.num_reads                           99815                       # number of read accesses completed
 system.cpu0.num_writes                          53929                       # number of write accesses completed
 system.cpu0.num_copies                              0                       # number of copy accesses completed
 system.cpu0.l1c.replacements                    27826                       # number of replacements
-system.cpu0.l1c.tagsinuse                  102.742005                       # Cycle average of tags in use
+system.cpu0.l1c.tagsinuse                  347.331950                       # Cycle average of tags in use
 system.cpu0.l1c.total_refs                      11604                       # Total number of references to valid blocks.
 system.cpu0.l1c.sampled_refs                    28187                       # Sample count of references to valid blocks.
 system.cpu0.l1c.avg_refs                     0.411679                       # Average number of references to valid blocks.
 system.cpu0.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu0.l1c.occ_blocks::0              347.331950                       # Average occupied blocks per context
-system.cpu0.l1c.occ_blocks::1             -244.589945                       # Average occupied blocks per context
-system.cpu0.l1c.occ_percent::0               0.678383                       # Average percentage of cache occupancy
-system.cpu0.l1c.occ_percent::1              -0.477715                       # Average percentage of cache occupancy
-system.cpu0.l1c.ReadReq_hits                     7530                       # number of ReadReq hits
-system.cpu0.l1c.WriteReq_hits                    1059                       # number of WriteReq hits
-system.cpu0.l1c.demand_hits                      8589                       # number of demand (read+write) hits
-system.cpu0.l1c.overall_hits                     8589                       # number of overall hits
-system.cpu0.l1c.ReadReq_misses                  37279                       # number of ReadReq misses
-system.cpu0.l1c.WriteReq_misses                 23202                       # number of WriteReq misses
-system.cpu0.l1c.demand_misses                   60481                       # number of demand (read+write) misses
-system.cpu0.l1c.overall_misses                  60481                       # number of overall misses
-system.cpu0.l1c.ReadReq_miss_latency       1299667421                       # number of ReadReq miss cycles
-system.cpu0.l1c.WriteReq_miss_latency      1001508092                       # number of WriteReq miss cycles
-system.cpu0.l1c.demand_miss_latency        2301175513                       # number of demand (read+write) miss cycles
-system.cpu0.l1c.overall_miss_latency       2301175513                       # number of overall miss cycles
-system.cpu0.l1c.ReadReq_accesses                44809                       # number of ReadReq accesses(hits+misses)
-system.cpu0.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
-system.cpu0.l1c.demand_accesses                 69070                       # number of demand (read+write) accesses
-system.cpu0.l1c.overall_accesses                69070                       # number of overall (read+write) accesses
-system.cpu0.l1c.ReadReq_miss_rate            0.831953                       # miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_miss_rate           0.956350                       # miss rate for WriteReq accesses
-system.cpu0.l1c.demand_miss_rate             0.875648                       # miss rate for demand accesses
-system.cpu0.l1c.overall_miss_rate            0.875648                       # miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_miss_latency 34863.258698                       # average ReadReq miss latency
-system.cpu0.l1c.WriteReq_avg_miss_latency 43164.731144                       # average WriteReq miss latency
-system.cpu0.l1c.demand_avg_miss_latency  38047.907822                       # average overall miss latency
-system.cpu0.l1c.overall_avg_miss_latency 38047.907822                       # average overall miss latency
+system.cpu0.l1c.occ_blocks::cpu0           347.331950                       # Average occupied blocks per requestor
+system.cpu0.l1c.occ_percent::cpu0            0.678383                       # Average percentage of cache occupancy
+system.cpu0.l1c.occ_percent::total           0.678383                       # Average percentage of cache occupancy
+system.cpu0.l1c.ReadReq_hits::cpu0               7530                       # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total              7530                       # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0              1059                       # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total             1059                       # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0                8589                       # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total               8589                       # number of demand (read+write) hits
+system.cpu0.l1c.overall_hits::cpu0               8589                       # number of overall hits
+system.cpu0.l1c.overall_hits::total              8589                       # number of overall hits
+system.cpu0.l1c.ReadReq_misses::cpu0            37279                       # number of ReadReq misses
+system.cpu0.l1c.ReadReq_misses::total           37279                       # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0           23202                       # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total          23202                       # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0             60481                       # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total            60481                       # number of demand (read+write) misses
+system.cpu0.l1c.overall_misses::cpu0            60481                       # number of overall misses
+system.cpu0.l1c.overall_misses::total           60481                       # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0   1299667421                       # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total   1299667421                       # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0   1001508092                       # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total   1001508092                       # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0   2301175513                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total   2301175513                       # number of demand (read+write) miss cycles
+system.cpu0.l1c.overall_miss_latency::cpu0   2301175513                       # number of overall miss cycles
+system.cpu0.l1c.overall_miss_latency::total   2301175513                       # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0          44809                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total         44809                       # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0         24261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total        24261                       # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0           69070                       # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total          69070                       # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0          69070                       # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total         69070                       # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0      0.831953                       # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0     0.956350                       # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0       0.875648                       # miss rate for demand accesses
+system.cpu0.l1c.overall_miss_rate::cpu0      0.875648                       # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 34863.258698                       # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 43164.731144                       # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 38047.907822                       # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 38047.907822                       # average overall miss latency
 system.cpu0.l1c.blocked_cycles::no_mshrs    253845135                       # number of cycles access was blocked
 system.cpu0.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu0.l1c.blocked::no_mshrs               69110                       # number of cycles access was blocked
@@ -409,72 +648,94 @@ system.cpu0.l1c.avg_blocked_cycles::no_mshrs  3673.059398
 system.cpu0.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu0.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu0.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu0.l1c.writebacks                      11972                       # number of writebacks
-system.cpu0.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu0.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu0.l1c.ReadReq_mshr_misses             37279                       # number of ReadReq MSHR misses
-system.cpu0.l1c.WriteReq_mshr_misses            23202                       # number of WriteReq MSHR misses
-system.cpu0.l1c.demand_mshr_misses              60481                       # number of demand (read+write) MSHR misses
-system.cpu0.l1c.overall_mshr_misses             60481                       # number of overall MSHR misses
-system.cpu0.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu0.l1c.ReadReq_mshr_miss_latency   1262244251                       # number of ReadReq MSHR miss cycles
-system.cpu0.l1c.WriteReq_mshr_miss_latency    978215253                       # number of WriteReq MSHR miss cycles
-system.cpu0.l1c.demand_mshr_miss_latency   2240459504                       # number of demand (read+write) MSHR miss cycles
-system.cpu0.l1c.overall_mshr_miss_latency   2240459504                       # number of overall MSHR miss cycles
-system.cpu0.l1c.ReadReq_mshr_uncacheable_latency    894578632                       # number of ReadReq MSHR uncacheable cycles
-system.cpu0.l1c.WriteReq_mshr_uncacheable_latency    569723237                       # number of WriteReq MSHR uncacheable cycles
-system.cpu0.l1c.overall_mshr_uncacheable_latency   1464301869                       # number of overall MSHR uncacheable cycles
-system.cpu0.l1c.ReadReq_mshr_miss_rate       0.831953                       # mshr miss rate for ReadReq accesses
-system.cpu0.l1c.WriteReq_mshr_miss_rate      0.956350                       # mshr miss rate for WriteReq accesses
-system.cpu0.l1c.demand_mshr_miss_rate        0.875648                       # mshr miss rate for demand accesses
-system.cpu0.l1c.overall_mshr_miss_rate       0.875648                       # mshr miss rate for overall accesses
-system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33859.391373                       # average ReadReq mshr miss latency
-system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 42160.816007                       # average WriteReq mshr miss latency
-system.cpu0.l1c.demand_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
-system.cpu0.l1c.overall_avg_mshr_miss_latency 37044.022156                       # average overall mshr miss latency
-system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu0.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu0.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu0.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu0.l1c.writebacks::writebacks          11972                       # number of writebacks
+system.cpu0.l1c.writebacks::total               11972                       # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0        37279                       # number of ReadReq MSHR misses
+system.cpu0.l1c.ReadReq_mshr_misses::total        37279                       # number of ReadReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::cpu0        23202                       # number of WriteReq MSHR misses
+system.cpu0.l1c.WriteReq_mshr_misses::total        23202                       # number of WriteReq MSHR misses
+system.cpu0.l1c.demand_mshr_misses::cpu0        60481                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.demand_mshr_misses::total        60481                       # number of demand (read+write) MSHR misses
+system.cpu0.l1c.overall_mshr_misses::cpu0        60481                       # number of overall MSHR misses
+system.cpu0.l1c.overall_mshr_misses::total        60481                       # number of overall MSHR misses
+system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0   1262244251                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_miss_latency::total   1262244251                       # number of ReadReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0    978215253                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.WriteReq_mshr_miss_latency::total    978215253                       # number of WriteReq MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::cpu0   2240459504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.demand_mshr_miss_latency::total   2240459504                       # number of demand (read+write) MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::cpu0   2240459504                       # number of overall MSHR miss cycles
+system.cpu0.l1c.overall_mshr_miss_latency::total   2240459504                       # number of overall MSHR miss cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0    894578632                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total    894578632                       # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0    569723237                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total    569723237                       # number of WriteReq MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0   1464301869                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total   1464301869                       # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0     0.831953                       # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0     0.956350                       # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.demand_mshr_miss_rate::cpu0     0.875648                       # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0     0.875648                       # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 33859.391373                       # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 42160.816007                       # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 37044.022156                       # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0          inf                       # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0          inf                       # average overall mshr uncacheable latency
 system.cpu0.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu1.num_reads                           98493                       # number of read accesses completed
 system.cpu1.num_writes                          53671                       # number of write accesses completed
 system.cpu1.num_copies                              0                       # number of copy accesses completed
 system.cpu1.l1c.replacements                    27684                       # number of replacements
-system.cpu1.l1c.tagsinuse                   93.018974                       # Cycle average of tags in use
+system.cpu1.l1c.tagsinuse                  345.656340                       # Cycle average of tags in use
 system.cpu1.l1c.total_refs                      11419                       # Total number of references to valid blocks.
 system.cpu1.l1c.sampled_refs                    28039                       # Sample count of references to valid blocks.
 system.cpu1.l1c.avg_refs                     0.407254                       # Average number of references to valid blocks.
 system.cpu1.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu1.l1c.occ_blocks::0              345.656340                       # Average occupied blocks per context
-system.cpu1.l1c.occ_blocks::1             -252.637366                       # Average occupied blocks per context
-system.cpu1.l1c.occ_percent::0               0.675110                       # Average percentage of cache occupancy
-system.cpu1.l1c.occ_percent::1              -0.493432                       # Average percentage of cache occupancy
-system.cpu1.l1c.ReadReq_hits                     7429                       # number of ReadReq hits
-system.cpu1.l1c.WriteReq_hits                    1066                       # number of WriteReq hits
-system.cpu1.l1c.demand_hits                      8495                       # number of demand (read+write) hits
-system.cpu1.l1c.overall_hits                     8495                       # number of overall hits
-system.cpu1.l1c.ReadReq_misses                  37110                       # number of ReadReq misses
-system.cpu1.l1c.WriteReq_misses                 23275                       # number of WriteReq misses
-system.cpu1.l1c.demand_misses                   60385                       # number of demand (read+write) misses
-system.cpu1.l1c.overall_misses                  60385                       # number of overall misses
-system.cpu1.l1c.ReadReq_miss_latency       1301760811                       # number of ReadReq miss cycles
-system.cpu1.l1c.WriteReq_miss_latency      1014297005                       # number of WriteReq miss cycles
-system.cpu1.l1c.demand_miss_latency        2316057816                       # number of demand (read+write) miss cycles
-system.cpu1.l1c.overall_miss_latency       2316057816                       # number of overall miss cycles
-system.cpu1.l1c.ReadReq_accesses                44539                       # number of ReadReq accesses(hits+misses)
-system.cpu1.l1c.WriteReq_accesses               24341                       # number of WriteReq accesses(hits+misses)
-system.cpu1.l1c.demand_accesses                 68880                       # number of demand (read+write) accesses
-system.cpu1.l1c.overall_accesses                68880                       # number of overall (read+write) accesses
-system.cpu1.l1c.ReadReq_miss_rate            0.833202                       # miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_miss_rate           0.956206                       # miss rate for WriteReq accesses
-system.cpu1.l1c.demand_miss_rate             0.876670                       # miss rate for demand accesses
-system.cpu1.l1c.overall_miss_rate            0.876670                       # miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_miss_latency 35078.437375                       # average ReadReq miss latency
-system.cpu1.l1c.WriteReq_avg_miss_latency 43578.818690                       # average WriteReq miss latency
-system.cpu1.l1c.demand_avg_miss_latency  38354.853291                       # average overall miss latency
-system.cpu1.l1c.overall_avg_miss_latency 38354.853291                       # average overall miss latency
+system.cpu1.l1c.occ_blocks::cpu1           345.656340                       # Average occupied blocks per requestor
+system.cpu1.l1c.occ_percent::cpu1            0.675110                       # Average percentage of cache occupancy
+system.cpu1.l1c.occ_percent::total           0.675110                       # Average percentage of cache occupancy
+system.cpu1.l1c.ReadReq_hits::cpu1               7429                       # number of ReadReq hits
+system.cpu1.l1c.ReadReq_hits::total              7429                       # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1              1066                       # number of WriteReq hits
+system.cpu1.l1c.WriteReq_hits::total             1066                       # number of WriteReq hits
+system.cpu1.l1c.demand_hits::cpu1                8495                       # number of demand (read+write) hits
+system.cpu1.l1c.demand_hits::total               8495                       # number of demand (read+write) hits
+system.cpu1.l1c.overall_hits::cpu1               8495                       # number of overall hits
+system.cpu1.l1c.overall_hits::total              8495                       # number of overall hits
+system.cpu1.l1c.ReadReq_misses::cpu1            37110                       # number of ReadReq misses
+system.cpu1.l1c.ReadReq_misses::total           37110                       # number of ReadReq misses
+system.cpu1.l1c.WriteReq_misses::cpu1           23275                       # number of WriteReq misses
+system.cpu1.l1c.WriteReq_misses::total          23275                       # number of WriteReq misses
+system.cpu1.l1c.demand_misses::cpu1             60385                       # number of demand (read+write) misses
+system.cpu1.l1c.demand_misses::total            60385                       # number of demand (read+write) misses
+system.cpu1.l1c.overall_misses::cpu1            60385                       # number of overall misses
+system.cpu1.l1c.overall_misses::total           60385                       # number of overall misses
+system.cpu1.l1c.ReadReq_miss_latency::cpu1   1301760811                       # number of ReadReq miss cycles
+system.cpu1.l1c.ReadReq_miss_latency::total   1301760811                       # number of ReadReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::cpu1   1014297005                       # number of WriteReq miss cycles
+system.cpu1.l1c.WriteReq_miss_latency::total   1014297005                       # number of WriteReq miss cycles
+system.cpu1.l1c.demand_miss_latency::cpu1   2316057816                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.demand_miss_latency::total   2316057816                       # number of demand (read+write) miss cycles
+system.cpu1.l1c.overall_miss_latency::cpu1   2316057816                       # number of overall miss cycles
+system.cpu1.l1c.overall_miss_latency::total   2316057816                       # number of overall miss cycles
+system.cpu1.l1c.ReadReq_accesses::cpu1          44539                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.ReadReq_accesses::total         44539                       # number of ReadReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::cpu1         24341                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.WriteReq_accesses::total        24341                       # number of WriteReq accesses(hits+misses)
+system.cpu1.l1c.demand_accesses::cpu1           68880                       # number of demand (read+write) accesses
+system.cpu1.l1c.demand_accesses::total          68880                       # number of demand (read+write) accesses
+system.cpu1.l1c.overall_accesses::cpu1          68880                       # number of overall (read+write) accesses
+system.cpu1.l1c.overall_accesses::total         68880                       # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1      0.833202                       # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1     0.956206                       # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1       0.876670                       # miss rate for demand accesses
+system.cpu1.l1c.overall_miss_rate::cpu1      0.876670                       # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 35078.437375                       # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 43578.818690                       # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 38354.853291                       # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 38354.853291                       # average overall miss latency
 system.cpu1.l1c.blocked_cycles::no_mshrs    253325402                       # number of cycles access was blocked
 system.cpu1.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu1.l1c.blocked::no_mshrs               68822                       # number of cycles access was blocked
@@ -483,72 +744,94 @@ system.cpu1.l1c.avg_blocked_cycles::no_mshrs  3680.878237
 system.cpu1.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu1.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu1.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu1.l1c.writebacks                      11809                       # number of writebacks
-system.cpu1.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu1.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu1.l1c.ReadReq_mshr_misses             37110                       # number of ReadReq MSHR misses
-system.cpu1.l1c.WriteReq_mshr_misses            23275                       # number of WriteReq MSHR misses
-system.cpu1.l1c.demand_mshr_misses              60385                       # number of demand (read+write) MSHR misses
-system.cpu1.l1c.overall_mshr_misses             60385                       # number of overall MSHR misses
-system.cpu1.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu1.l1c.ReadReq_mshr_miss_latency   1264508347                       # number of ReadReq MSHR miss cycles
-system.cpu1.l1c.WriteReq_mshr_miss_latency    990933889                       # number of WriteReq MSHR miss cycles
-system.cpu1.l1c.demand_mshr_miss_latency   2255442236                       # number of demand (read+write) MSHR miss cycles
-system.cpu1.l1c.overall_mshr_miss_latency   2255442236                       # number of overall MSHR miss cycles
-system.cpu1.l1c.ReadReq_mshr_uncacheable_latency    877119159                       # number of ReadReq MSHR uncacheable cycles
-system.cpu1.l1c.WriteReq_mshr_uncacheable_latency    578327433                       # number of WriteReq MSHR uncacheable cycles
-system.cpu1.l1c.overall_mshr_uncacheable_latency   1455446592                       # number of overall MSHR uncacheable cycles
-system.cpu1.l1c.ReadReq_mshr_miss_rate       0.833202                       # mshr miss rate for ReadReq accesses
-system.cpu1.l1c.WriteReq_mshr_miss_rate      0.956206                       # mshr miss rate for WriteReq accesses
-system.cpu1.l1c.demand_mshr_miss_rate        0.876670                       # mshr miss rate for demand accesses
-system.cpu1.l1c.overall_mshr_miss_rate       0.876670                       # mshr miss rate for overall accesses
-system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34074.598410                       # average ReadReq mshr miss latency
-system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 42575.032825                       # average WriteReq mshr miss latency
-system.cpu1.l1c.demand_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
-system.cpu1.l1c.overall_avg_mshr_miss_latency 37351.034793                       # average overall mshr miss latency
-system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu1.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu1.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu1.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu1.l1c.writebacks::writebacks          11809                       # number of writebacks
+system.cpu1.l1c.writebacks::total               11809                       # number of writebacks
+system.cpu1.l1c.ReadReq_mshr_misses::cpu1        37110                       # number of ReadReq MSHR misses
+system.cpu1.l1c.ReadReq_mshr_misses::total        37110                       # number of ReadReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::cpu1        23275                       # number of WriteReq MSHR misses
+system.cpu1.l1c.WriteReq_mshr_misses::total        23275                       # number of WriteReq MSHR misses
+system.cpu1.l1c.demand_mshr_misses::cpu1        60385                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.demand_mshr_misses::total        60385                       # number of demand (read+write) MSHR misses
+system.cpu1.l1c.overall_mshr_misses::cpu1        60385                       # number of overall MSHR misses
+system.cpu1.l1c.overall_mshr_misses::total        60385                       # number of overall MSHR misses
+system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1   1264508347                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_miss_latency::total   1264508347                       # number of ReadReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1    990933889                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.WriteReq_mshr_miss_latency::total    990933889                       # number of WriteReq MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::cpu1   2255442236                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.demand_mshr_miss_latency::total   2255442236                       # number of demand (read+write) MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::cpu1   2255442236                       # number of overall MSHR miss cycles
+system.cpu1.l1c.overall_mshr_miss_latency::total   2255442236                       # number of overall MSHR miss cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1    877119159                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total    877119159                       # number of ReadReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1    578327433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total    578327433                       # number of WriteReq MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1   1455446592                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.overall_mshr_uncacheable_latency::total   1455446592                       # number of overall MSHR uncacheable cycles
+system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1     0.833202                       # mshr miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1     0.956206                       # mshr miss rate for WriteReq accesses
+system.cpu1.l1c.demand_mshr_miss_rate::cpu1     0.876670                       # mshr miss rate for demand accesses
+system.cpu1.l1c.overall_mshr_miss_rate::cpu1     0.876670                       # mshr miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 34074.598410                       # average ReadReq mshr miss latency
+system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 42575.032825                       # average WriteReq mshr miss latency
+system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 37351.034793                       # average overall mshr miss latency
+system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average ReadReq mshr uncacheable latency
+system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1          inf                       # average WriteReq mshr uncacheable latency
+system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1          inf                       # average overall mshr uncacheable latency
 system.cpu1.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu2.num_reads                           99149                       # number of read accesses completed
 system.cpu2.num_writes                          53185                       # number of write accesses completed
 system.cpu2.num_copies                              0                       # number of copy accesses completed
 system.cpu2.l1c.replacements                    27627                       # number of replacements
-system.cpu2.l1c.tagsinuse                   84.373112                       # Cycle average of tags in use
+system.cpu2.l1c.tagsinuse                  345.430231                       # Cycle average of tags in use
 system.cpu2.l1c.total_refs                      11519                       # Total number of references to valid blocks.
 system.cpu2.l1c.sampled_refs                    27982                       # Sample count of references to valid blocks.
 system.cpu2.l1c.avg_refs                     0.411657                       # Average number of references to valid blocks.
 system.cpu2.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu2.l1c.occ_blocks::0              345.430231                       # Average occupied blocks per context
-system.cpu2.l1c.occ_blocks::1             -261.057119                       # Average occupied blocks per context
-system.cpu2.l1c.occ_percent::0               0.674668                       # Average percentage of cache occupancy
-system.cpu2.l1c.occ_percent::1              -0.509877                       # Average percentage of cache occupancy
-system.cpu2.l1c.ReadReq_hits                     7576                       # number of ReadReq hits
-system.cpu2.l1c.WriteReq_hits                    1069                       # number of WriteReq hits
-system.cpu2.l1c.demand_hits                      8645                       # number of demand (read+write) hits
-system.cpu2.l1c.overall_hits                     8645                       # number of overall hits
-system.cpu2.l1c.ReadReq_misses                  37144                       # number of ReadReq misses
-system.cpu2.l1c.WriteReq_misses                 22885                       # number of WriteReq misses
-system.cpu2.l1c.demand_misses                   60029                       # number of demand (read+write) misses
-system.cpu2.l1c.overall_misses                  60029                       # number of overall misses
-system.cpu2.l1c.ReadReq_miss_latency       1302790562                       # number of ReadReq miss cycles
-system.cpu2.l1c.WriteReq_miss_latency       991654869                       # number of WriteReq miss cycles
-system.cpu2.l1c.demand_miss_latency        2294445431                       # number of demand (read+write) miss cycles
-system.cpu2.l1c.overall_miss_latency       2294445431                       # number of overall miss cycles
-system.cpu2.l1c.ReadReq_accesses                44720                       # number of ReadReq accesses(hits+misses)
-system.cpu2.l1c.WriteReq_accesses               23954                       # number of WriteReq accesses(hits+misses)
-system.cpu2.l1c.demand_accesses                 68674                       # number of demand (read+write) accesses
-system.cpu2.l1c.overall_accesses                68674                       # number of overall (read+write) accesses
-system.cpu2.l1c.ReadReq_miss_rate            0.830590                       # miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_miss_rate           0.955373                       # miss rate for WriteReq accesses
-system.cpu2.l1c.demand_miss_rate             0.874115                       # miss rate for demand accesses
-system.cpu2.l1c.overall_miss_rate            0.874115                       # miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_miss_latency 35074.051314                       # average ReadReq miss latency
-system.cpu2.l1c.WriteReq_avg_miss_latency 43332.089535                       # average WriteReq miss latency
-system.cpu2.l1c.demand_avg_miss_latency  38222.283080                       # average overall miss latency
-system.cpu2.l1c.overall_avg_miss_latency 38222.283080                       # average overall miss latency
+system.cpu2.l1c.occ_blocks::cpu2           345.430231                       # Average occupied blocks per requestor
+system.cpu2.l1c.occ_percent::cpu2            0.674668                       # Average percentage of cache occupancy
+system.cpu2.l1c.occ_percent::total           0.674668                       # Average percentage of cache occupancy
+system.cpu2.l1c.ReadReq_hits::cpu2               7576                       # number of ReadReq hits
+system.cpu2.l1c.ReadReq_hits::total              7576                       # number of ReadReq hits
+system.cpu2.l1c.WriteReq_hits::cpu2              1069                       # number of WriteReq hits
+system.cpu2.l1c.WriteReq_hits::total             1069                       # number of WriteReq hits
+system.cpu2.l1c.demand_hits::cpu2                8645                       # number of demand (read+write) hits
+system.cpu2.l1c.demand_hits::total               8645                       # number of demand (read+write) hits
+system.cpu2.l1c.overall_hits::cpu2               8645                       # number of overall hits
+system.cpu2.l1c.overall_hits::total              8645                       # number of overall hits
+system.cpu2.l1c.ReadReq_misses::cpu2            37144                       # number of ReadReq misses
+system.cpu2.l1c.ReadReq_misses::total           37144                       # number of ReadReq misses
+system.cpu2.l1c.WriteReq_misses::cpu2           22885                       # number of WriteReq misses
+system.cpu2.l1c.WriteReq_misses::total          22885                       # number of WriteReq misses
+system.cpu2.l1c.demand_misses::cpu2             60029                       # number of demand (read+write) misses
+system.cpu2.l1c.demand_misses::total            60029                       # number of demand (read+write) misses
+system.cpu2.l1c.overall_misses::cpu2            60029                       # number of overall misses
+system.cpu2.l1c.overall_misses::total           60029                       # number of overall misses
+system.cpu2.l1c.ReadReq_miss_latency::cpu2   1302790562                       # number of ReadReq miss cycles
+system.cpu2.l1c.ReadReq_miss_latency::total   1302790562                       # number of ReadReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::cpu2    991654869                       # number of WriteReq miss cycles
+system.cpu2.l1c.WriteReq_miss_latency::total    991654869                       # number of WriteReq miss cycles
+system.cpu2.l1c.demand_miss_latency::cpu2   2294445431                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.demand_miss_latency::total   2294445431                       # number of demand (read+write) miss cycles
+system.cpu2.l1c.overall_miss_latency::cpu2   2294445431                       # number of overall miss cycles
+system.cpu2.l1c.overall_miss_latency::total   2294445431                       # number of overall miss cycles
+system.cpu2.l1c.ReadReq_accesses::cpu2          44720                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.ReadReq_accesses::total         44720                       # number of ReadReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::cpu2         23954                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.WriteReq_accesses::total        23954                       # number of WriteReq accesses(hits+misses)
+system.cpu2.l1c.demand_accesses::cpu2           68674                       # number of demand (read+write) accesses
+system.cpu2.l1c.demand_accesses::total          68674                       # number of demand (read+write) accesses
+system.cpu2.l1c.overall_accesses::cpu2          68674                       # number of overall (read+write) accesses
+system.cpu2.l1c.overall_accesses::total         68674                       # number of overall (read+write) accesses
+system.cpu2.l1c.ReadReq_miss_rate::cpu2      0.830590                       # miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_miss_rate::cpu2     0.955373                       # miss rate for WriteReq accesses
+system.cpu2.l1c.demand_miss_rate::cpu2       0.874115                       # miss rate for demand accesses
+system.cpu2.l1c.overall_miss_rate::cpu2      0.874115                       # miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 35074.051314                       # average ReadReq miss latency
+system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 43332.089535                       # average WriteReq miss latency
+system.cpu2.l1c.demand_avg_miss_latency::cpu2 38222.283080                       # average overall miss latency
+system.cpu2.l1c.overall_avg_miss_latency::cpu2 38222.283080                       # average overall miss latency
 system.cpu2.l1c.blocked_cycles::no_mshrs    254303447                       # number of cycles access was blocked
 system.cpu2.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu2.l1c.blocked::no_mshrs               68698                       # number of cycles access was blocked
@@ -557,72 +840,94 @@ system.cpu2.l1c.avg_blocked_cycles::no_mshrs  3701.759105
 system.cpu2.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu2.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu2.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu2.l1c.writebacks                      11784                       # number of writebacks
-system.cpu2.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu2.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu2.l1c.ReadReq_mshr_misses             37144                       # number of ReadReq MSHR misses
-system.cpu2.l1c.WriteReq_mshr_misses            22885                       # number of WriteReq MSHR misses
-system.cpu2.l1c.demand_mshr_misses              60029                       # number of demand (read+write) MSHR misses
-system.cpu2.l1c.overall_mshr_misses             60029                       # number of overall MSHR misses
-system.cpu2.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu2.l1c.ReadReq_mshr_miss_latency   1265501937                       # number of ReadReq MSHR miss cycles
-system.cpu2.l1c.WriteReq_mshr_miss_latency    968684322                       # number of WriteReq MSHR miss cycles
-system.cpu2.l1c.demand_mshr_miss_latency   2234186259                       # number of demand (read+write) MSHR miss cycles
-system.cpu2.l1c.overall_mshr_miss_latency   2234186259                       # number of overall MSHR miss cycles
-system.cpu2.l1c.ReadReq_mshr_uncacheable_latency    900513056                       # number of ReadReq MSHR uncacheable cycles
-system.cpu2.l1c.WriteReq_mshr_uncacheable_latency    566349170                       # number of WriteReq MSHR uncacheable cycles
-system.cpu2.l1c.overall_mshr_uncacheable_latency   1466862226                       # number of overall MSHR uncacheable cycles
-system.cpu2.l1c.ReadReq_mshr_miss_rate       0.830590                       # mshr miss rate for ReadReq accesses
-system.cpu2.l1c.WriteReq_mshr_miss_rate      0.955373                       # mshr miss rate for WriteReq accesses
-system.cpu2.l1c.demand_mshr_miss_rate        0.874115                       # mshr miss rate for demand accesses
-system.cpu2.l1c.overall_mshr_miss_rate       0.874115                       # mshr miss rate for overall accesses
-system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34070.157684                       # average ReadReq mshr miss latency
-system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 42328.351409                       # average WriteReq mshr miss latency
-system.cpu2.l1c.demand_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
-system.cpu2.l1c.overall_avg_mshr_miss_latency 37218.448733                       # average overall mshr miss latency
-system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu2.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu2.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu2.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu2.l1c.writebacks::writebacks          11784                       # number of writebacks
+system.cpu2.l1c.writebacks::total               11784                       # number of writebacks
+system.cpu2.l1c.ReadReq_mshr_misses::cpu2        37144                       # number of ReadReq MSHR misses
+system.cpu2.l1c.ReadReq_mshr_misses::total        37144                       # number of ReadReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::cpu2        22885                       # number of WriteReq MSHR misses
+system.cpu2.l1c.WriteReq_mshr_misses::total        22885                       # number of WriteReq MSHR misses
+system.cpu2.l1c.demand_mshr_misses::cpu2        60029                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.demand_mshr_misses::total        60029                       # number of demand (read+write) MSHR misses
+system.cpu2.l1c.overall_mshr_misses::cpu2        60029                       # number of overall MSHR misses
+system.cpu2.l1c.overall_mshr_misses::total        60029                       # number of overall MSHR misses
+system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2   1265501937                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_miss_latency::total   1265501937                       # number of ReadReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2    968684322                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.WriteReq_mshr_miss_latency::total    968684322                       # number of WriteReq MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::cpu2   2234186259                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.demand_mshr_miss_latency::total   2234186259                       # number of demand (read+write) MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::cpu2   2234186259                       # number of overall MSHR miss cycles
+system.cpu2.l1c.overall_mshr_miss_latency::total   2234186259                       # number of overall MSHR miss cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2    900513056                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total    900513056                       # number of ReadReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2    566349170                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total    566349170                       # number of WriteReq MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2   1466862226                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.overall_mshr_uncacheable_latency::total   1466862226                       # number of overall MSHR uncacheable cycles
+system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2     0.830590                       # mshr miss rate for ReadReq accesses
+system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2     0.955373                       # mshr miss rate for WriteReq accesses
+system.cpu2.l1c.demand_mshr_miss_rate::cpu2     0.874115                       # mshr miss rate for demand accesses
+system.cpu2.l1c.overall_mshr_miss_rate::cpu2     0.874115                       # mshr miss rate for overall accesses
+system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 34070.157684                       # average ReadReq mshr miss latency
+system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 42328.351409                       # average WriteReq mshr miss latency
+system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 37218.448733                       # average overall mshr miss latency
+system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average ReadReq mshr uncacheable latency
+system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2          inf                       # average WriteReq mshr uncacheable latency
+system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2          inf                       # average overall mshr uncacheable latency
 system.cpu2.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu3.num_reads                           99588                       # number of read accesses completed
 system.cpu3.num_writes                          53645                       # number of write accesses completed
 system.cpu3.num_copies                              0                       # number of copy accesses completed
 system.cpu3.l1c.replacements                    27837                       # number of replacements
-system.cpu3.l1c.tagsinuse                  104.177298                       # Cycle average of tags in use
+system.cpu3.l1c.tagsinuse                  347.574885                       # Cycle average of tags in use
 system.cpu3.l1c.total_refs                      11563                       # Total number of references to valid blocks.
 system.cpu3.l1c.sampled_refs                    28190                       # Sample count of references to valid blocks.
 system.cpu3.l1c.avg_refs                     0.410181                       # Average number of references to valid blocks.
 system.cpu3.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu3.l1c.occ_blocks::0              347.574885                       # Average occupied blocks per context
-system.cpu3.l1c.occ_blocks::1             -243.397586                       # Average occupied blocks per context
-system.cpu3.l1c.occ_percent::0               0.678857                       # Average percentage of cache occupancy
-system.cpu3.l1c.occ_percent::1              -0.475386                       # Average percentage of cache occupancy
-system.cpu3.l1c.ReadReq_hits                     7552                       # number of ReadReq hits
-system.cpu3.l1c.WriteReq_hits                    1078                       # number of WriteReq hits
-system.cpu3.l1c.demand_hits                      8630                       # number of demand (read+write) hits
-system.cpu3.l1c.overall_hits                     8630                       # number of overall hits
-system.cpu3.l1c.ReadReq_misses                  37191                       # number of ReadReq misses
-system.cpu3.l1c.WriteReq_misses                 23219                       # number of WriteReq misses
-system.cpu3.l1c.demand_misses                   60410                       # number of demand (read+write) misses
-system.cpu3.l1c.overall_misses                  60410                       # number of overall misses
-system.cpu3.l1c.ReadReq_miss_latency       1312024933                       # number of ReadReq miss cycles
-system.cpu3.l1c.WriteReq_miss_latency       995527685                       # number of WriteReq miss cycles
-system.cpu3.l1c.demand_miss_latency        2307552618                       # number of demand (read+write) miss cycles
-system.cpu3.l1c.overall_miss_latency       2307552618                       # number of overall miss cycles
-system.cpu3.l1c.ReadReq_accesses                44743                       # number of ReadReq accesses(hits+misses)
-system.cpu3.l1c.WriteReq_accesses               24297                       # number of WriteReq accesses(hits+misses)
-system.cpu3.l1c.demand_accesses                 69040                       # number of demand (read+write) accesses
-system.cpu3.l1c.overall_accesses                69040                       # number of overall (read+write) accesses
-system.cpu3.l1c.ReadReq_miss_rate            0.831214                       # miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_miss_rate           0.955632                       # miss rate for WriteReq accesses
-system.cpu3.l1c.demand_miss_rate             0.875000                       # miss rate for demand accesses
-system.cpu3.l1c.overall_miss_rate            0.875000                       # miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_miss_latency 35278.022452                       # average ReadReq miss latency
-system.cpu3.l1c.WriteReq_avg_miss_latency 42875.562470                       # average WriteReq miss latency
-system.cpu3.l1c.demand_avg_miss_latency  38198.189340                       # average overall miss latency
-system.cpu3.l1c.overall_avg_miss_latency 38198.189340                       # average overall miss latency
+system.cpu3.l1c.occ_blocks::cpu3           347.574885                       # Average occupied blocks per requestor
+system.cpu3.l1c.occ_percent::cpu3            0.678857                       # Average percentage of cache occupancy
+system.cpu3.l1c.occ_percent::total           0.678857                       # Average percentage of cache occupancy
+system.cpu3.l1c.ReadReq_hits::cpu3               7552                       # number of ReadReq hits
+system.cpu3.l1c.ReadReq_hits::total              7552                       # number of ReadReq hits
+system.cpu3.l1c.WriteReq_hits::cpu3              1078                       # number of WriteReq hits
+system.cpu3.l1c.WriteReq_hits::total             1078                       # number of WriteReq hits
+system.cpu3.l1c.demand_hits::cpu3                8630                       # number of demand (read+write) hits
+system.cpu3.l1c.demand_hits::total               8630                       # number of demand (read+write) hits
+system.cpu3.l1c.overall_hits::cpu3               8630                       # number of overall hits
+system.cpu3.l1c.overall_hits::total              8630                       # number of overall hits
+system.cpu3.l1c.ReadReq_misses::cpu3            37191                       # number of ReadReq misses
+system.cpu3.l1c.ReadReq_misses::total           37191                       # number of ReadReq misses
+system.cpu3.l1c.WriteReq_misses::cpu3           23219                       # number of WriteReq misses
+system.cpu3.l1c.WriteReq_misses::total          23219                       # number of WriteReq misses
+system.cpu3.l1c.demand_misses::cpu3             60410                       # number of demand (read+write) misses
+system.cpu3.l1c.demand_misses::total            60410                       # number of demand (read+write) misses
+system.cpu3.l1c.overall_misses::cpu3            60410                       # number of overall misses
+system.cpu3.l1c.overall_misses::total           60410                       # number of overall misses
+system.cpu3.l1c.ReadReq_miss_latency::cpu3   1312024933                       # number of ReadReq miss cycles
+system.cpu3.l1c.ReadReq_miss_latency::total   1312024933                       # number of ReadReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::cpu3    995527685                       # number of WriteReq miss cycles
+system.cpu3.l1c.WriteReq_miss_latency::total    995527685                       # number of WriteReq miss cycles
+system.cpu3.l1c.demand_miss_latency::cpu3   2307552618                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.demand_miss_latency::total   2307552618                       # number of demand (read+write) miss cycles
+system.cpu3.l1c.overall_miss_latency::cpu3   2307552618                       # number of overall miss cycles
+system.cpu3.l1c.overall_miss_latency::total   2307552618                       # number of overall miss cycles
+system.cpu3.l1c.ReadReq_accesses::cpu3          44743                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.ReadReq_accesses::total         44743                       # number of ReadReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::cpu3         24297                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.WriteReq_accesses::total        24297                       # number of WriteReq accesses(hits+misses)
+system.cpu3.l1c.demand_accesses::cpu3           69040                       # number of demand (read+write) accesses
+system.cpu3.l1c.demand_accesses::total          69040                       # number of demand (read+write) accesses
+system.cpu3.l1c.overall_accesses::cpu3          69040                       # number of overall (read+write) accesses
+system.cpu3.l1c.overall_accesses::total         69040                       # number of overall (read+write) accesses
+system.cpu3.l1c.ReadReq_miss_rate::cpu3      0.831214                       # miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_miss_rate::cpu3     0.955632                       # miss rate for WriteReq accesses
+system.cpu3.l1c.demand_miss_rate::cpu3       0.875000                       # miss rate for demand accesses
+system.cpu3.l1c.overall_miss_rate::cpu3      0.875000                       # miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 35278.022452                       # average ReadReq miss latency
+system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 42875.562470                       # average WriteReq miss latency
+system.cpu3.l1c.demand_avg_miss_latency::cpu3 38198.189340                       # average overall miss latency
+system.cpu3.l1c.overall_avg_miss_latency::cpu3 38198.189340                       # average overall miss latency
 system.cpu3.l1c.blocked_cycles::no_mshrs    254462667                       # number of cycles access was blocked
 system.cpu3.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu3.l1c.blocked::no_mshrs               68939                       # number of cycles access was blocked
@@ -631,72 +936,94 @@ system.cpu3.l1c.avg_blocked_cycles::no_mshrs  3691.127910
 system.cpu3.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu3.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu3.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu3.l1c.writebacks                      11956                       # number of writebacks
-system.cpu3.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu3.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu3.l1c.ReadReq_mshr_misses             37191                       # number of ReadReq MSHR misses
-system.cpu3.l1c.WriteReq_mshr_misses            23219                       # number of WriteReq MSHR misses
-system.cpu3.l1c.demand_mshr_misses              60410                       # number of demand (read+write) MSHR misses
-system.cpu3.l1c.overall_mshr_misses             60410                       # number of overall MSHR misses
-system.cpu3.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu3.l1c.ReadReq_mshr_miss_latency   1274692143                       # number of ReadReq MSHR miss cycles
-system.cpu3.l1c.WriteReq_mshr_miss_latency    972218785                       # number of WriteReq MSHR miss cycles
-system.cpu3.l1c.demand_mshr_miss_latency   2246910928                       # number of demand (read+write) MSHR miss cycles
-system.cpu3.l1c.overall_mshr_miss_latency   2246910928                       # number of overall MSHR miss cycles
-system.cpu3.l1c.ReadReq_mshr_uncacheable_latency    889431937                       # number of ReadReq MSHR uncacheable cycles
-system.cpu3.l1c.WriteReq_mshr_uncacheable_latency    569772276                       # number of WriteReq MSHR uncacheable cycles
-system.cpu3.l1c.overall_mshr_uncacheable_latency   1459204213                       # number of overall MSHR uncacheable cycles
-system.cpu3.l1c.ReadReq_mshr_miss_rate       0.831214                       # mshr miss rate for ReadReq accesses
-system.cpu3.l1c.WriteReq_mshr_miss_rate      0.955632                       # mshr miss rate for WriteReq accesses
-system.cpu3.l1c.demand_mshr_miss_rate        0.875000                       # mshr miss rate for demand accesses
-system.cpu3.l1c.overall_mshr_miss_rate       0.875000                       # mshr miss rate for overall accesses
-system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34274.209970                       # average ReadReq mshr miss latency
-system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 41871.690641                       # average WriteReq mshr miss latency
-system.cpu3.l1c.demand_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
-system.cpu3.l1c.overall_avg_mshr_miss_latency 37194.354047                       # average overall mshr miss latency
-system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu3.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu3.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu3.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu3.l1c.writebacks::writebacks          11956                       # number of writebacks
+system.cpu3.l1c.writebacks::total               11956                       # number of writebacks
+system.cpu3.l1c.ReadReq_mshr_misses::cpu3        37191                       # number of ReadReq MSHR misses
+system.cpu3.l1c.ReadReq_mshr_misses::total        37191                       # number of ReadReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::cpu3        23219                       # number of WriteReq MSHR misses
+system.cpu3.l1c.WriteReq_mshr_misses::total        23219                       # number of WriteReq MSHR misses
+system.cpu3.l1c.demand_mshr_misses::cpu3        60410                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.demand_mshr_misses::total        60410                       # number of demand (read+write) MSHR misses
+system.cpu3.l1c.overall_mshr_misses::cpu3        60410                       # number of overall MSHR misses
+system.cpu3.l1c.overall_mshr_misses::total        60410                       # number of overall MSHR misses
+system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3   1274692143                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_miss_latency::total   1274692143                       # number of ReadReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3    972218785                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.WriteReq_mshr_miss_latency::total    972218785                       # number of WriteReq MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::cpu3   2246910928                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.demand_mshr_miss_latency::total   2246910928                       # number of demand (read+write) MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::cpu3   2246910928                       # number of overall MSHR miss cycles
+system.cpu3.l1c.overall_mshr_miss_latency::total   2246910928                       # number of overall MSHR miss cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3    889431937                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total    889431937                       # number of ReadReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3    569772276                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total    569772276                       # number of WriteReq MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3   1459204213                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.overall_mshr_uncacheable_latency::total   1459204213                       # number of overall MSHR uncacheable cycles
+system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3     0.831214                       # mshr miss rate for ReadReq accesses
+system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3     0.955632                       # mshr miss rate for WriteReq accesses
+system.cpu3.l1c.demand_mshr_miss_rate::cpu3     0.875000                       # mshr miss rate for demand accesses
+system.cpu3.l1c.overall_mshr_miss_rate::cpu3     0.875000                       # mshr miss rate for overall accesses
+system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34274.209970                       # average ReadReq mshr miss latency
+system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 41871.690641                       # average WriteReq mshr miss latency
+system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 37194.354047                       # average overall mshr miss latency
+system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average ReadReq mshr uncacheable latency
+system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3          inf                       # average WriteReq mshr uncacheable latency
+system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3          inf                       # average overall mshr uncacheable latency
 system.cpu3.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu4.num_reads                           99725                       # number of read accesses completed
 system.cpu4.num_writes                          53533                       # number of write accesses completed
 system.cpu4.num_copies                              0                       # number of copy accesses completed
 system.cpu4.l1c.replacements                    27683                       # number of replacements
-system.cpu4.l1c.tagsinuse                   94.681644                       # Cycle average of tags in use
+system.cpu4.l1c.tagsinuse                  347.631602                       # Cycle average of tags in use
 system.cpu4.l1c.total_refs                      11724                       # Total number of references to valid blocks.
 system.cpu4.l1c.sampled_refs                    28041                       # Sample count of references to valid blocks.
 system.cpu4.l1c.avg_refs                     0.418102                       # Average number of references to valid blocks.
 system.cpu4.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu4.l1c.occ_blocks::0              347.631602                       # Average occupied blocks per context
-system.cpu4.l1c.occ_blocks::1             -252.949959                       # Average occupied blocks per context
-system.cpu4.l1c.occ_percent::0               0.678968                       # Average percentage of cache occupancy
-system.cpu4.l1c.occ_percent::1              -0.494043                       # Average percentage of cache occupancy
-system.cpu4.l1c.ReadReq_hits                     7686                       # number of ReadReq hits
-system.cpu4.l1c.WriteReq_hits                    1123                       # number of WriteReq hits
-system.cpu4.l1c.demand_hits                      8809                       # number of demand (read+write) hits
-system.cpu4.l1c.overall_hits                     8809                       # number of overall hits
-system.cpu4.l1c.ReadReq_misses                  37251                       # number of ReadReq misses
-system.cpu4.l1c.WriteReq_misses                 22937                       # number of WriteReq misses
-system.cpu4.l1c.demand_misses                   60188                       # number of demand (read+write) misses
-system.cpu4.l1c.overall_misses                  60188                       # number of overall misses
-system.cpu4.l1c.ReadReq_miss_latency       1303112178                       # number of ReadReq miss cycles
-system.cpu4.l1c.WriteReq_miss_latency       994450363                       # number of WriteReq miss cycles
-system.cpu4.l1c.demand_miss_latency        2297562541                       # number of demand (read+write) miss cycles
-system.cpu4.l1c.overall_miss_latency       2297562541                       # number of overall miss cycles
-system.cpu4.l1c.ReadReq_accesses                44937                       # number of ReadReq accesses(hits+misses)
-system.cpu4.l1c.WriteReq_accesses               24060                       # number of WriteReq accesses(hits+misses)
-system.cpu4.l1c.demand_accesses                 68997                       # number of demand (read+write) accesses
-system.cpu4.l1c.overall_accesses                68997                       # number of overall (read+write) accesses
-system.cpu4.l1c.ReadReq_miss_rate            0.828961                       # miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_miss_rate           0.953325                       # miss rate for WriteReq accesses
-system.cpu4.l1c.demand_miss_rate             0.872328                       # miss rate for demand accesses
-system.cpu4.l1c.overall_miss_rate            0.872328                       # miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_miss_latency 34981.938149                       # average ReadReq miss latency
-system.cpu4.l1c.WriteReq_avg_miss_latency 43355.729302                       # average WriteReq miss latency
-system.cpu4.l1c.demand_avg_miss_latency  38173.099970                       # average overall miss latency
-system.cpu4.l1c.overall_avg_miss_latency 38173.099970                       # average overall miss latency
+system.cpu4.l1c.occ_blocks::cpu4           347.631602                       # Average occupied blocks per requestor
+system.cpu4.l1c.occ_percent::cpu4            0.678968                       # Average percentage of cache occupancy
+system.cpu4.l1c.occ_percent::total           0.678968                       # Average percentage of cache occupancy
+system.cpu4.l1c.ReadReq_hits::cpu4               7686                       # number of ReadReq hits
+system.cpu4.l1c.ReadReq_hits::total              7686                       # number of ReadReq hits
+system.cpu4.l1c.WriteReq_hits::cpu4              1123                       # number of WriteReq hits
+system.cpu4.l1c.WriteReq_hits::total             1123                       # number of WriteReq hits
+system.cpu4.l1c.demand_hits::cpu4                8809                       # number of demand (read+write) hits
+system.cpu4.l1c.demand_hits::total               8809                       # number of demand (read+write) hits
+system.cpu4.l1c.overall_hits::cpu4               8809                       # number of overall hits
+system.cpu4.l1c.overall_hits::total              8809                       # number of overall hits
+system.cpu4.l1c.ReadReq_misses::cpu4            37251                       # number of ReadReq misses
+system.cpu4.l1c.ReadReq_misses::total           37251                       # number of ReadReq misses
+system.cpu4.l1c.WriteReq_misses::cpu4           22937                       # number of WriteReq misses
+system.cpu4.l1c.WriteReq_misses::total          22937                       # number of WriteReq misses
+system.cpu4.l1c.demand_misses::cpu4             60188                       # number of demand (read+write) misses
+system.cpu4.l1c.demand_misses::total            60188                       # number of demand (read+write) misses
+system.cpu4.l1c.overall_misses::cpu4            60188                       # number of overall misses
+system.cpu4.l1c.overall_misses::total           60188                       # number of overall misses
+system.cpu4.l1c.ReadReq_miss_latency::cpu4   1303112178                       # number of ReadReq miss cycles
+system.cpu4.l1c.ReadReq_miss_latency::total   1303112178                       # number of ReadReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::cpu4    994450363                       # number of WriteReq miss cycles
+system.cpu4.l1c.WriteReq_miss_latency::total    994450363                       # number of WriteReq miss cycles
+system.cpu4.l1c.demand_miss_latency::cpu4   2297562541                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.demand_miss_latency::total   2297562541                       # number of demand (read+write) miss cycles
+system.cpu4.l1c.overall_miss_latency::cpu4   2297562541                       # number of overall miss cycles
+system.cpu4.l1c.overall_miss_latency::total   2297562541                       # number of overall miss cycles
+system.cpu4.l1c.ReadReq_accesses::cpu4          44937                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.ReadReq_accesses::total         44937                       # number of ReadReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::cpu4         24060                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.WriteReq_accesses::total        24060                       # number of WriteReq accesses(hits+misses)
+system.cpu4.l1c.demand_accesses::cpu4           68997                       # number of demand (read+write) accesses
+system.cpu4.l1c.demand_accesses::total          68997                       # number of demand (read+write) accesses
+system.cpu4.l1c.overall_accesses::cpu4          68997                       # number of overall (read+write) accesses
+system.cpu4.l1c.overall_accesses::total         68997                       # number of overall (read+write) accesses
+system.cpu4.l1c.ReadReq_miss_rate::cpu4      0.828961                       # miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_miss_rate::cpu4     0.953325                       # miss rate for WriteReq accesses
+system.cpu4.l1c.demand_miss_rate::cpu4       0.872328                       # miss rate for demand accesses
+system.cpu4.l1c.overall_miss_rate::cpu4      0.872328                       # miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 34981.938149                       # average ReadReq miss latency
+system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 43355.729302                       # average WriteReq miss latency
+system.cpu4.l1c.demand_avg_miss_latency::cpu4 38173.099970                       # average overall miss latency
+system.cpu4.l1c.overall_avg_miss_latency::cpu4 38173.099970                       # average overall miss latency
 system.cpu4.l1c.blocked_cycles::no_mshrs    254136532                       # number of cycles access was blocked
 system.cpu4.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu4.l1c.blocked::no_mshrs               68868                       # number of cycles access was blocked
@@ -705,72 +1032,94 @@ system.cpu4.l1c.avg_blocked_cycles::no_mshrs  3690.197653
 system.cpu4.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu4.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu4.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu4.l1c.writebacks                      11763                       # number of writebacks
-system.cpu4.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu4.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu4.l1c.ReadReq_mshr_misses             37251                       # number of ReadReq MSHR misses
-system.cpu4.l1c.WriteReq_mshr_misses            22937                       # number of WriteReq MSHR misses
-system.cpu4.l1c.demand_mshr_misses              60188                       # number of demand (read+write) MSHR misses
-system.cpu4.l1c.overall_mshr_misses             60188                       # number of overall MSHR misses
-system.cpu4.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu4.l1c.ReadReq_mshr_miss_latency   1265717116                       # number of ReadReq MSHR miss cycles
-system.cpu4.l1c.WriteReq_mshr_miss_latency    971425596                       # number of WriteReq MSHR miss cycles
-system.cpu4.l1c.demand_mshr_miss_latency   2237142712                       # number of demand (read+write) MSHR miss cycles
-system.cpu4.l1c.overall_mshr_miss_latency   2237142712                       # number of overall MSHR miss cycles
-system.cpu4.l1c.ReadReq_mshr_uncacheable_latency    898461911                       # number of ReadReq MSHR uncacheable cycles
-system.cpu4.l1c.WriteReq_mshr_uncacheable_latency    576408625                       # number of WriteReq MSHR uncacheable cycles
-system.cpu4.l1c.overall_mshr_uncacheable_latency   1474870536                       # number of overall MSHR uncacheable cycles
-system.cpu4.l1c.ReadReq_mshr_miss_rate       0.828961                       # mshr miss rate for ReadReq accesses
-system.cpu4.l1c.WriteReq_mshr_miss_rate      0.953325                       # mshr miss rate for WriteReq accesses
-system.cpu4.l1c.demand_mshr_miss_rate        0.872328                       # mshr miss rate for demand accesses
-system.cpu4.l1c.overall_mshr_miss_rate       0.872328                       # mshr miss rate for overall accesses
-system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 33978.070817                       # average ReadReq mshr miss latency
-system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 42351.902864                       # average WriteReq mshr miss latency
-system.cpu4.l1c.demand_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
-system.cpu4.l1c.overall_avg_mshr_miss_latency 37169.248222                       # average overall mshr miss latency
-system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu4.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu4.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu4.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu4.l1c.writebacks::writebacks          11763                       # number of writebacks
+system.cpu4.l1c.writebacks::total               11763                       # number of writebacks
+system.cpu4.l1c.ReadReq_mshr_misses::cpu4        37251                       # number of ReadReq MSHR misses
+system.cpu4.l1c.ReadReq_mshr_misses::total        37251                       # number of ReadReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::cpu4        22937                       # number of WriteReq MSHR misses
+system.cpu4.l1c.WriteReq_mshr_misses::total        22937                       # number of WriteReq MSHR misses
+system.cpu4.l1c.demand_mshr_misses::cpu4        60188                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.demand_mshr_misses::total        60188                       # number of demand (read+write) MSHR misses
+system.cpu4.l1c.overall_mshr_misses::cpu4        60188                       # number of overall MSHR misses
+system.cpu4.l1c.overall_mshr_misses::total        60188                       # number of overall MSHR misses
+system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4   1265717116                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_miss_latency::total   1265717116                       # number of ReadReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4    971425596                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.WriteReq_mshr_miss_latency::total    971425596                       # number of WriteReq MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::cpu4   2237142712                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.demand_mshr_miss_latency::total   2237142712                       # number of demand (read+write) MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::cpu4   2237142712                       # number of overall MSHR miss cycles
+system.cpu4.l1c.overall_mshr_miss_latency::total   2237142712                       # number of overall MSHR miss cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4    898461911                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total    898461911                       # number of ReadReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4    576408625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total    576408625                       # number of WriteReq MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4   1474870536                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.overall_mshr_uncacheable_latency::total   1474870536                       # number of overall MSHR uncacheable cycles
+system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4     0.828961                       # mshr miss rate for ReadReq accesses
+system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4     0.953325                       # mshr miss rate for WriteReq accesses
+system.cpu4.l1c.demand_mshr_miss_rate::cpu4     0.872328                       # mshr miss rate for demand accesses
+system.cpu4.l1c.overall_mshr_miss_rate::cpu4     0.872328                       # mshr miss rate for overall accesses
+system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 33978.070817                       # average ReadReq mshr miss latency
+system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 42351.902864                       # average WriteReq mshr miss latency
+system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 37169.248222                       # average overall mshr miss latency
+system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average ReadReq mshr uncacheable latency
+system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4          inf                       # average WriteReq mshr uncacheable latency
+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4          inf                       # average overall mshr uncacheable latency
 system.cpu4.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu5.num_reads                          100000                       # number of read accesses completed
 system.cpu5.num_writes                          53710                       # number of write accesses completed
 system.cpu5.num_copies                              0                       # number of copy accesses completed
 system.cpu5.l1c.replacements                    27832                       # number of replacements
-system.cpu5.l1c.tagsinuse                   93.507234                       # Cycle average of tags in use
+system.cpu5.l1c.tagsinuse                  346.806811                       # Cycle average of tags in use
 system.cpu5.l1c.total_refs                      11748                       # Total number of references to valid blocks.
 system.cpu5.l1c.sampled_refs                    28191                       # Sample count of references to valid blocks.
 system.cpu5.l1c.avg_refs                     0.416729                       # Average number of references to valid blocks.
 system.cpu5.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu5.l1c.occ_blocks::0              346.806811                       # Average occupied blocks per context
-system.cpu5.l1c.occ_blocks::1             -253.299577                       # Average occupied blocks per context
-system.cpu5.l1c.occ_percent::0               0.677357                       # Average percentage of cache occupancy
-system.cpu5.l1c.occ_percent::1              -0.494726                       # Average percentage of cache occupancy
-system.cpu5.l1c.ReadReq_hits                     7592                       # number of ReadReq hits
-system.cpu5.l1c.WriteReq_hits                    1126                       # number of WriteReq hits
-system.cpu5.l1c.demand_hits                      8718                       # number of demand (read+write) hits
-system.cpu5.l1c.overall_hits                     8718                       # number of overall hits
-system.cpu5.l1c.ReadReq_misses                  37349                       # number of ReadReq misses
-system.cpu5.l1c.WriteReq_misses                 23013                       # number of WriteReq misses
-system.cpu5.l1c.demand_misses                   60362                       # number of demand (read+write) misses
-system.cpu5.l1c.overall_misses                  60362                       # number of overall misses
-system.cpu5.l1c.ReadReq_miss_latency       1291933371                       # number of ReadReq miss cycles
-system.cpu5.l1c.WriteReq_miss_latency       998304045                       # number of WriteReq miss cycles
-system.cpu5.l1c.demand_miss_latency        2290237416                       # number of demand (read+write) miss cycles
-system.cpu5.l1c.overall_miss_latency       2290237416                       # number of overall miss cycles
-system.cpu5.l1c.ReadReq_accesses                44941                       # number of ReadReq accesses(hits+misses)
-system.cpu5.l1c.WriteReq_accesses               24139                       # number of WriteReq accesses(hits+misses)
-system.cpu5.l1c.demand_accesses                 69080                       # number of demand (read+write) accesses
-system.cpu5.l1c.overall_accesses                69080                       # number of overall (read+write) accesses
-system.cpu5.l1c.ReadReq_miss_rate            0.831067                       # miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_miss_rate           0.953353                       # miss rate for WriteReq accesses
-system.cpu5.l1c.demand_miss_rate             0.873798                       # miss rate for demand accesses
-system.cpu5.l1c.overall_miss_rate            0.873798                       # miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_miss_latency 34590.842352                       # average ReadReq miss latency
-system.cpu5.l1c.WriteReq_avg_miss_latency 43380.004563                       # average WriteReq miss latency
-system.cpu5.l1c.demand_avg_miss_latency  37941.708625                       # average overall miss latency
-system.cpu5.l1c.overall_avg_miss_latency 37941.708625                       # average overall miss latency
+system.cpu5.l1c.occ_blocks::cpu5           346.806811                       # Average occupied blocks per requestor
+system.cpu5.l1c.occ_percent::cpu5            0.677357                       # Average percentage of cache occupancy
+system.cpu5.l1c.occ_percent::total           0.677357                       # Average percentage of cache occupancy
+system.cpu5.l1c.ReadReq_hits::cpu5               7592                       # number of ReadReq hits
+system.cpu5.l1c.ReadReq_hits::total              7592                       # number of ReadReq hits
+system.cpu5.l1c.WriteReq_hits::cpu5              1126                       # number of WriteReq hits
+system.cpu5.l1c.WriteReq_hits::total             1126                       # number of WriteReq hits
+system.cpu5.l1c.demand_hits::cpu5                8718                       # number of demand (read+write) hits
+system.cpu5.l1c.demand_hits::total               8718                       # number of demand (read+write) hits
+system.cpu5.l1c.overall_hits::cpu5               8718                       # number of overall hits
+system.cpu5.l1c.overall_hits::total              8718                       # number of overall hits
+system.cpu5.l1c.ReadReq_misses::cpu5            37349                       # number of ReadReq misses
+system.cpu5.l1c.ReadReq_misses::total           37349                       # number of ReadReq misses
+system.cpu5.l1c.WriteReq_misses::cpu5           23013                       # number of WriteReq misses
+system.cpu5.l1c.WriteReq_misses::total          23013                       # number of WriteReq misses
+system.cpu5.l1c.demand_misses::cpu5             60362                       # number of demand (read+write) misses
+system.cpu5.l1c.demand_misses::total            60362                       # number of demand (read+write) misses
+system.cpu5.l1c.overall_misses::cpu5            60362                       # number of overall misses
+system.cpu5.l1c.overall_misses::total           60362                       # number of overall misses
+system.cpu5.l1c.ReadReq_miss_latency::cpu5   1291933371                       # number of ReadReq miss cycles
+system.cpu5.l1c.ReadReq_miss_latency::total   1291933371                       # number of ReadReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::cpu5    998304045                       # number of WriteReq miss cycles
+system.cpu5.l1c.WriteReq_miss_latency::total    998304045                       # number of WriteReq miss cycles
+system.cpu5.l1c.demand_miss_latency::cpu5   2290237416                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.demand_miss_latency::total   2290237416                       # number of demand (read+write) miss cycles
+system.cpu5.l1c.overall_miss_latency::cpu5   2290237416                       # number of overall miss cycles
+system.cpu5.l1c.overall_miss_latency::total   2290237416                       # number of overall miss cycles
+system.cpu5.l1c.ReadReq_accesses::cpu5          44941                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.ReadReq_accesses::total         44941                       # number of ReadReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::cpu5         24139                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.WriteReq_accesses::total        24139                       # number of WriteReq accesses(hits+misses)
+system.cpu5.l1c.demand_accesses::cpu5           69080                       # number of demand (read+write) accesses
+system.cpu5.l1c.demand_accesses::total          69080                       # number of demand (read+write) accesses
+system.cpu5.l1c.overall_accesses::cpu5          69080                       # number of overall (read+write) accesses
+system.cpu5.l1c.overall_accesses::total         69080                       # number of overall (read+write) accesses
+system.cpu5.l1c.ReadReq_miss_rate::cpu5      0.831067                       # miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_miss_rate::cpu5     0.953353                       # miss rate for WriteReq accesses
+system.cpu5.l1c.demand_miss_rate::cpu5       0.873798                       # miss rate for demand accesses
+system.cpu5.l1c.overall_miss_rate::cpu5      0.873798                       # miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 34590.842352                       # average ReadReq miss latency
+system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 43380.004563                       # average WriteReq miss latency
+system.cpu5.l1c.demand_avg_miss_latency::cpu5 37941.708625                       # average overall miss latency
+system.cpu5.l1c.overall_avg_miss_latency::cpu5 37941.708625                       # average overall miss latency
 system.cpu5.l1c.blocked_cycles::no_mshrs    253381114                       # number of cycles access was blocked
 system.cpu5.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu5.l1c.blocked::no_mshrs               68969                       # number of cycles access was blocked
@@ -779,72 +1128,94 @@ system.cpu5.l1c.avg_blocked_cycles::no_mshrs  3673.840624
 system.cpu5.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu5.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu5.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu5.l1c.writebacks                      11908                       # number of writebacks
-system.cpu5.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu5.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu5.l1c.ReadReq_mshr_misses             37349                       # number of ReadReq MSHR misses
-system.cpu5.l1c.WriteReq_mshr_misses            23013                       # number of WriteReq MSHR misses
-system.cpu5.l1c.demand_mshr_misses              60362                       # number of demand (read+write) MSHR misses
-system.cpu5.l1c.overall_mshr_misses             60362                       # number of overall MSHR misses
-system.cpu5.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu5.l1c.ReadReq_mshr_miss_latency   1254436910                       # number of ReadReq MSHR miss cycles
-system.cpu5.l1c.WriteReq_mshr_miss_latency    975203983                       # number of WriteReq MSHR miss cycles
-system.cpu5.l1c.demand_mshr_miss_latency   2229640893                       # number of demand (read+write) MSHR miss cycles
-system.cpu5.l1c.overall_mshr_miss_latency   2229640893                       # number of overall MSHR miss cycles
-system.cpu5.l1c.ReadReq_mshr_uncacheable_latency    902856034                       # number of ReadReq MSHR uncacheable cycles
-system.cpu5.l1c.WriteReq_mshr_uncacheable_latency    567587171                       # number of WriteReq MSHR uncacheable cycles
-system.cpu5.l1c.overall_mshr_uncacheable_latency   1470443205                       # number of overall MSHR uncacheable cycles
-system.cpu5.l1c.ReadReq_mshr_miss_rate       0.831067                       # mshr miss rate for ReadReq accesses
-system.cpu5.l1c.WriteReq_mshr_miss_rate      0.953353                       # mshr miss rate for WriteReq accesses
-system.cpu5.l1c.demand_mshr_miss_rate        0.873798                       # mshr miss rate for demand accesses
-system.cpu5.l1c.overall_mshr_miss_rate       0.873798                       # mshr miss rate for overall accesses
-system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33586.894160                       # average ReadReq mshr miss latency
-system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 42376.221397                       # average WriteReq mshr miss latency
-system.cpu5.l1c.demand_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
-system.cpu5.l1c.overall_avg_mshr_miss_latency 36937.823349                       # average overall mshr miss latency
-system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu5.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu5.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu5.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu5.l1c.writebacks::writebacks          11908                       # number of writebacks
+system.cpu5.l1c.writebacks::total               11908                       # number of writebacks
+system.cpu5.l1c.ReadReq_mshr_misses::cpu5        37349                       # number of ReadReq MSHR misses
+system.cpu5.l1c.ReadReq_mshr_misses::total        37349                       # number of ReadReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::cpu5        23013                       # number of WriteReq MSHR misses
+system.cpu5.l1c.WriteReq_mshr_misses::total        23013                       # number of WriteReq MSHR misses
+system.cpu5.l1c.demand_mshr_misses::cpu5        60362                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.demand_mshr_misses::total        60362                       # number of demand (read+write) MSHR misses
+system.cpu5.l1c.overall_mshr_misses::cpu5        60362                       # number of overall MSHR misses
+system.cpu5.l1c.overall_mshr_misses::total        60362                       # number of overall MSHR misses
+system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5   1254436910                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_miss_latency::total   1254436910                       # number of ReadReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5    975203983                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.WriteReq_mshr_miss_latency::total    975203983                       # number of WriteReq MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::cpu5   2229640893                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.demand_mshr_miss_latency::total   2229640893                       # number of demand (read+write) MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::cpu5   2229640893                       # number of overall MSHR miss cycles
+system.cpu5.l1c.overall_mshr_miss_latency::total   2229640893                       # number of overall MSHR miss cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5    902856034                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total    902856034                       # number of ReadReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5    567587171                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total    567587171                       # number of WriteReq MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5   1470443205                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.overall_mshr_uncacheable_latency::total   1470443205                       # number of overall MSHR uncacheable cycles
+system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5     0.831067                       # mshr miss rate for ReadReq accesses
+system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5     0.953353                       # mshr miss rate for WriteReq accesses
+system.cpu5.l1c.demand_mshr_miss_rate::cpu5     0.873798                       # mshr miss rate for demand accesses
+system.cpu5.l1c.overall_mshr_miss_rate::cpu5     0.873798                       # mshr miss rate for overall accesses
+system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 33586.894160                       # average ReadReq mshr miss latency
+system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 42376.221397                       # average WriteReq mshr miss latency
+system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 36937.823349                       # average overall mshr miss latency
+system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average ReadReq mshr uncacheable latency
+system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5          inf                       # average WriteReq mshr uncacheable latency
+system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5          inf                       # average overall mshr uncacheable latency
 system.cpu5.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu6.num_reads                           99389                       # number of read accesses completed
 system.cpu6.num_writes                          53686                       # number of write accesses completed
 system.cpu6.num_copies                              0                       # number of copy accesses completed
 system.cpu6.l1c.replacements                    27861                       # number of replacements
-system.cpu6.l1c.tagsinuse                   89.788098                       # Cycle average of tags in use
+system.cpu6.l1c.tagsinuse                  347.289326                       # Cycle average of tags in use
 system.cpu6.l1c.total_refs                      11520                       # Total number of references to valid blocks.
 system.cpu6.l1c.sampled_refs                    28198                       # Sample count of references to valid blocks.
 system.cpu6.l1c.avg_refs                     0.408540                       # Average number of references to valid blocks.
 system.cpu6.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu6.l1c.occ_blocks::0              347.289326                       # Average occupied blocks per context
-system.cpu6.l1c.occ_blocks::1             -257.501227                       # Average occupied blocks per context
-system.cpu6.l1c.occ_percent::0               0.678299                       # Average percentage of cache occupancy
-system.cpu6.l1c.occ_percent::1              -0.502932                       # Average percentage of cache occupancy
-system.cpu6.l1c.ReadReq_hits                     7543                       # number of ReadReq hits
-system.cpu6.l1c.WriteReq_hits                    1119                       # number of WriteReq hits
-system.cpu6.l1c.demand_hits                      8662                       # number of demand (read+write) hits
-system.cpu6.l1c.overall_hits                     8662                       # number of overall hits
-system.cpu6.l1c.ReadReq_misses                  37109                       # number of ReadReq misses
-system.cpu6.l1c.WriteReq_misses                 23142                       # number of WriteReq misses
-system.cpu6.l1c.demand_misses                   60251                       # number of demand (read+write) misses
-system.cpu6.l1c.overall_misses                  60251                       # number of overall misses
-system.cpu6.l1c.ReadReq_miss_latency       1299799162                       # number of ReadReq miss cycles
-system.cpu6.l1c.WriteReq_miss_latency      1015775810                       # number of WriteReq miss cycles
-system.cpu6.l1c.demand_miss_latency        2315574972                       # number of demand (read+write) miss cycles
-system.cpu6.l1c.overall_miss_latency       2315574972                       # number of overall miss cycles
-system.cpu6.l1c.ReadReq_accesses                44652                       # number of ReadReq accesses(hits+misses)
-system.cpu6.l1c.WriteReq_accesses               24261                       # number of WriteReq accesses(hits+misses)
-system.cpu6.l1c.demand_accesses                 68913                       # number of demand (read+write) accesses
-system.cpu6.l1c.overall_accesses                68913                       # number of overall (read+write) accesses
-system.cpu6.l1c.ReadReq_miss_rate            0.831071                       # miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_miss_rate           0.953877                       # miss rate for WriteReq accesses
-system.cpu6.l1c.demand_miss_rate             0.874305                       # miss rate for demand accesses
-system.cpu6.l1c.overall_miss_rate            0.874305                       # miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_miss_latency 35026.520844                       # average ReadReq miss latency
-system.cpu6.l1c.WriteReq_avg_miss_latency 43893.173019                       # average WriteReq miss latency
-system.cpu6.l1c.demand_avg_miss_latency  38432.141740                       # average overall miss latency
-system.cpu6.l1c.overall_avg_miss_latency 38432.141740                       # average overall miss latency
+system.cpu6.l1c.occ_blocks::cpu6           347.289326                       # Average occupied blocks per requestor
+system.cpu6.l1c.occ_percent::cpu6            0.678299                       # Average percentage of cache occupancy
+system.cpu6.l1c.occ_percent::total           0.678299                       # Average percentage of cache occupancy
+system.cpu6.l1c.ReadReq_hits::cpu6               7543                       # number of ReadReq hits
+system.cpu6.l1c.ReadReq_hits::total              7543                       # number of ReadReq hits
+system.cpu6.l1c.WriteReq_hits::cpu6              1119                       # number of WriteReq hits
+system.cpu6.l1c.WriteReq_hits::total             1119                       # number of WriteReq hits
+system.cpu6.l1c.demand_hits::cpu6                8662                       # number of demand (read+write) hits
+system.cpu6.l1c.demand_hits::total               8662                       # number of demand (read+write) hits
+system.cpu6.l1c.overall_hits::cpu6               8662                       # number of overall hits
+system.cpu6.l1c.overall_hits::total              8662                       # number of overall hits
+system.cpu6.l1c.ReadReq_misses::cpu6            37109                       # number of ReadReq misses
+system.cpu6.l1c.ReadReq_misses::total           37109                       # number of ReadReq misses
+system.cpu6.l1c.WriteReq_misses::cpu6           23142                       # number of WriteReq misses
+system.cpu6.l1c.WriteReq_misses::total          23142                       # number of WriteReq misses
+system.cpu6.l1c.demand_misses::cpu6             60251                       # number of demand (read+write) misses
+system.cpu6.l1c.demand_misses::total            60251                       # number of demand (read+write) misses
+system.cpu6.l1c.overall_misses::cpu6            60251                       # number of overall misses
+system.cpu6.l1c.overall_misses::total           60251                       # number of overall misses
+system.cpu6.l1c.ReadReq_miss_latency::cpu6   1299799162                       # number of ReadReq miss cycles
+system.cpu6.l1c.ReadReq_miss_latency::total   1299799162                       # number of ReadReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::cpu6   1015775810                       # number of WriteReq miss cycles
+system.cpu6.l1c.WriteReq_miss_latency::total   1015775810                       # number of WriteReq miss cycles
+system.cpu6.l1c.demand_miss_latency::cpu6   2315574972                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.demand_miss_latency::total   2315574972                       # number of demand (read+write) miss cycles
+system.cpu6.l1c.overall_miss_latency::cpu6   2315574972                       # number of overall miss cycles
+system.cpu6.l1c.overall_miss_latency::total   2315574972                       # number of overall miss cycles
+system.cpu6.l1c.ReadReq_accesses::cpu6          44652                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.ReadReq_accesses::total         44652                       # number of ReadReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::cpu6         24261                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.WriteReq_accesses::total        24261                       # number of WriteReq accesses(hits+misses)
+system.cpu6.l1c.demand_accesses::cpu6           68913                       # number of demand (read+write) accesses
+system.cpu6.l1c.demand_accesses::total          68913                       # number of demand (read+write) accesses
+system.cpu6.l1c.overall_accesses::cpu6          68913                       # number of overall (read+write) accesses
+system.cpu6.l1c.overall_accesses::total         68913                       # number of overall (read+write) accesses
+system.cpu6.l1c.ReadReq_miss_rate::cpu6      0.831071                       # miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_miss_rate::cpu6     0.953877                       # miss rate for WriteReq accesses
+system.cpu6.l1c.demand_miss_rate::cpu6       0.874305                       # miss rate for demand accesses
+system.cpu6.l1c.overall_miss_rate::cpu6      0.874305                       # miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 35026.520844                       # average ReadReq miss latency
+system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 43893.173019                       # average WriteReq miss latency
+system.cpu6.l1c.demand_avg_miss_latency::cpu6 38432.141740                       # average overall miss latency
+system.cpu6.l1c.overall_avg_miss_latency::cpu6 38432.141740                       # average overall miss latency
 system.cpu6.l1c.blocked_cycles::no_mshrs    253794713                       # number of cycles access was blocked
 system.cpu6.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu6.l1c.blocked::no_mshrs               68612                       # number of cycles access was blocked
@@ -853,72 +1224,94 @@ system.cpu6.l1c.avg_blocked_cycles::no_mshrs  3698.984332
 system.cpu6.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu6.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu6.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu6.l1c.writebacks                      11849                       # number of writebacks
-system.cpu6.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu6.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu6.l1c.ReadReq_mshr_misses             37109                       # number of ReadReq MSHR misses
-system.cpu6.l1c.WriteReq_mshr_misses            23142                       # number of WriteReq MSHR misses
-system.cpu6.l1c.demand_mshr_misses              60251                       # number of demand (read+write) MSHR misses
-system.cpu6.l1c.overall_mshr_misses             60251                       # number of overall MSHR misses
-system.cpu6.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu6.l1c.ReadReq_mshr_miss_latency   1262548698                       # number of ReadReq MSHR miss cycles
-system.cpu6.l1c.WriteReq_mshr_miss_latency    992541214                       # number of WriteReq MSHR miss cycles
-system.cpu6.l1c.demand_mshr_miss_latency   2255089912                       # number of demand (read+write) MSHR miss cycles
-system.cpu6.l1c.overall_mshr_miss_latency   2255089912                       # number of overall MSHR miss cycles
-system.cpu6.l1c.ReadReq_mshr_uncacheable_latency    877981455                       # number of ReadReq MSHR uncacheable cycles
-system.cpu6.l1c.WriteReq_mshr_uncacheable_latency    574689009                       # number of WriteReq MSHR uncacheable cycles
-system.cpu6.l1c.overall_mshr_uncacheable_latency   1452670464                       # number of overall MSHR uncacheable cycles
-system.cpu6.l1c.ReadReq_mshr_miss_rate       0.831071                       # mshr miss rate for ReadReq accesses
-system.cpu6.l1c.WriteReq_mshr_miss_rate      0.953877                       # mshr miss rate for WriteReq accesses
-system.cpu6.l1c.demand_mshr_miss_rate        0.874305                       # mshr miss rate for demand accesses
-system.cpu6.l1c.overall_mshr_miss_rate       0.874305                       # mshr miss rate for overall accesses
-system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34022.708723                       # average ReadReq mshr miss latency
-system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 42889.171809                       # average WriteReq mshr miss latency
-system.cpu6.l1c.demand_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
-system.cpu6.l1c.overall_avg_mshr_miss_latency 37428.256992                       # average overall mshr miss latency
-system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu6.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu6.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu6.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu6.l1c.writebacks::writebacks          11849                       # number of writebacks
+system.cpu6.l1c.writebacks::total               11849                       # number of writebacks
+system.cpu6.l1c.ReadReq_mshr_misses::cpu6        37109                       # number of ReadReq MSHR misses
+system.cpu6.l1c.ReadReq_mshr_misses::total        37109                       # number of ReadReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::cpu6        23142                       # number of WriteReq MSHR misses
+system.cpu6.l1c.WriteReq_mshr_misses::total        23142                       # number of WriteReq MSHR misses
+system.cpu6.l1c.demand_mshr_misses::cpu6        60251                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.demand_mshr_misses::total        60251                       # number of demand (read+write) MSHR misses
+system.cpu6.l1c.overall_mshr_misses::cpu6        60251                       # number of overall MSHR misses
+system.cpu6.l1c.overall_mshr_misses::total        60251                       # number of overall MSHR misses
+system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6   1262548698                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_miss_latency::total   1262548698                       # number of ReadReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6    992541214                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.WriteReq_mshr_miss_latency::total    992541214                       # number of WriteReq MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::cpu6   2255089912                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.demand_mshr_miss_latency::total   2255089912                       # number of demand (read+write) MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::cpu6   2255089912                       # number of overall MSHR miss cycles
+system.cpu6.l1c.overall_mshr_miss_latency::total   2255089912                       # number of overall MSHR miss cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6    877981455                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total    877981455                       # number of ReadReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6    574689009                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total    574689009                       # number of WriteReq MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6   1452670464                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.overall_mshr_uncacheable_latency::total   1452670464                       # number of overall MSHR uncacheable cycles
+system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6     0.831071                       # mshr miss rate for ReadReq accesses
+system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6     0.953877                       # mshr miss rate for WriteReq accesses
+system.cpu6.l1c.demand_mshr_miss_rate::cpu6     0.874305                       # mshr miss rate for demand accesses
+system.cpu6.l1c.overall_mshr_miss_rate::cpu6     0.874305                       # mshr miss rate for overall accesses
+system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 34022.708723                       # average ReadReq mshr miss latency
+system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 42889.171809                       # average WriteReq mshr miss latency
+system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 37428.256992                       # average overall mshr miss latency
+system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average ReadReq mshr uncacheable latency
+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6          inf                       # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6          inf                       # average overall mshr uncacheable latency
 system.cpu6.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 system.cpu7.num_reads                           99694                       # number of read accesses completed
 system.cpu7.num_writes                          53501                       # number of write accesses completed
 system.cpu7.num_copies                              0                       # number of copy accesses completed
 system.cpu7.l1c.replacements                    27727                       # number of replacements
-system.cpu7.l1c.tagsinuse                   84.250612                       # Cycle average of tags in use
+system.cpu7.l1c.tagsinuse                  346.094259                       # Cycle average of tags in use
 system.cpu7.l1c.total_refs                      11534                       # Total number of references to valid blocks.
 system.cpu7.l1c.sampled_refs                    28062                       # Sample count of references to valid blocks.
 system.cpu7.l1c.avg_refs                     0.411018                       # Average number of references to valid blocks.
 system.cpu7.l1c.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
-system.cpu7.l1c.occ_blocks::0              346.094259                       # Average occupied blocks per context
-system.cpu7.l1c.occ_blocks::1             -261.843648                       # Average occupied blocks per context
-system.cpu7.l1c.occ_percent::0               0.675965                       # Average percentage of cache occupancy
-system.cpu7.l1c.occ_percent::1              -0.511413                       # Average percentage of cache occupancy
-system.cpu7.l1c.ReadReq_hits                     7593                       # number of ReadReq hits
-system.cpu7.l1c.WriteReq_hits                    1111                       # number of WriteReq hits
-system.cpu7.l1c.demand_hits                      8704                       # number of demand (read+write) hits
-system.cpu7.l1c.overall_hits                     8704                       # number of overall hits
-system.cpu7.l1c.ReadReq_misses                  37155                       # number of ReadReq misses
-system.cpu7.l1c.WriteReq_misses                 23121                       # number of WriteReq misses
-system.cpu7.l1c.demand_misses                   60276                       # number of demand (read+write) misses
-system.cpu7.l1c.overall_misses                  60276                       # number of overall misses
-system.cpu7.l1c.ReadReq_miss_latency       1287127315                       # number of ReadReq miss cycles
-system.cpu7.l1c.WriteReq_miss_latency      1006139538                       # number of WriteReq miss cycles
-system.cpu7.l1c.demand_miss_latency        2293266853                       # number of demand (read+write) miss cycles
-system.cpu7.l1c.overall_miss_latency       2293266853                       # number of overall miss cycles
-system.cpu7.l1c.ReadReq_accesses                44748                       # number of ReadReq accesses(hits+misses)
-system.cpu7.l1c.WriteReq_accesses               24232                       # number of WriteReq accesses(hits+misses)
-system.cpu7.l1c.demand_accesses                 68980                       # number of demand (read+write) accesses
-system.cpu7.l1c.overall_accesses                68980                       # number of overall (read+write) accesses
-system.cpu7.l1c.ReadReq_miss_rate            0.830316                       # miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_miss_rate           0.954152                       # miss rate for WriteReq accesses
-system.cpu7.l1c.demand_miss_rate             0.873818                       # miss rate for demand accesses
-system.cpu7.l1c.overall_miss_rate            0.873818                       # miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_miss_latency 34642.102409                       # average ReadReq miss latency
-system.cpu7.l1c.WriteReq_avg_miss_latency 43516.263916                       # average WriteReq miss latency
-system.cpu7.l1c.demand_avg_miss_latency  38046.102147                       # average overall miss latency
-system.cpu7.l1c.overall_avg_miss_latency 38046.102147                       # average overall miss latency
+system.cpu7.l1c.occ_blocks::cpu7           346.094259                       # Average occupied blocks per requestor
+system.cpu7.l1c.occ_percent::cpu7            0.675965                       # Average percentage of cache occupancy
+system.cpu7.l1c.occ_percent::total           0.675965                       # Average percentage of cache occupancy
+system.cpu7.l1c.ReadReq_hits::cpu7               7593                       # number of ReadReq hits
+system.cpu7.l1c.ReadReq_hits::total              7593                       # number of ReadReq hits
+system.cpu7.l1c.WriteReq_hits::cpu7              1111                       # number of WriteReq hits
+system.cpu7.l1c.WriteReq_hits::total             1111                       # number of WriteReq hits
+system.cpu7.l1c.demand_hits::cpu7                8704                       # number of demand (read+write) hits
+system.cpu7.l1c.demand_hits::total               8704                       # number of demand (read+write) hits
+system.cpu7.l1c.overall_hits::cpu7               8704                       # number of overall hits
+system.cpu7.l1c.overall_hits::total              8704                       # number of overall hits
+system.cpu7.l1c.ReadReq_misses::cpu7            37155                       # number of ReadReq misses
+system.cpu7.l1c.ReadReq_misses::total           37155                       # number of ReadReq misses
+system.cpu7.l1c.WriteReq_misses::cpu7           23121                       # number of WriteReq misses
+system.cpu7.l1c.WriteReq_misses::total          23121                       # number of WriteReq misses
+system.cpu7.l1c.demand_misses::cpu7             60276                       # number of demand (read+write) misses
+system.cpu7.l1c.demand_misses::total            60276                       # number of demand (read+write) misses
+system.cpu7.l1c.overall_misses::cpu7            60276                       # number of overall misses
+system.cpu7.l1c.overall_misses::total           60276                       # number of overall misses
+system.cpu7.l1c.ReadReq_miss_latency::cpu7   1287127315                       # number of ReadReq miss cycles
+system.cpu7.l1c.ReadReq_miss_latency::total   1287127315                       # number of ReadReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::cpu7   1006139538                       # number of WriteReq miss cycles
+system.cpu7.l1c.WriteReq_miss_latency::total   1006139538                       # number of WriteReq miss cycles
+system.cpu7.l1c.demand_miss_latency::cpu7   2293266853                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.demand_miss_latency::total   2293266853                       # number of demand (read+write) miss cycles
+system.cpu7.l1c.overall_miss_latency::cpu7   2293266853                       # number of overall miss cycles
+system.cpu7.l1c.overall_miss_latency::total   2293266853                       # number of overall miss cycles
+system.cpu7.l1c.ReadReq_accesses::cpu7          44748                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.ReadReq_accesses::total         44748                       # number of ReadReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::cpu7         24232                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.WriteReq_accesses::total        24232                       # number of WriteReq accesses(hits+misses)
+system.cpu7.l1c.demand_accesses::cpu7           68980                       # number of demand (read+write) accesses
+system.cpu7.l1c.demand_accesses::total          68980                       # number of demand (read+write) accesses
+system.cpu7.l1c.overall_accesses::cpu7          68980                       # number of overall (read+write) accesses
+system.cpu7.l1c.overall_accesses::total         68980                       # number of overall (read+write) accesses
+system.cpu7.l1c.ReadReq_miss_rate::cpu7      0.830316                       # miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_miss_rate::cpu7     0.954152                       # miss rate for WriteReq accesses
+system.cpu7.l1c.demand_miss_rate::cpu7       0.873818                       # miss rate for demand accesses
+system.cpu7.l1c.overall_miss_rate::cpu7      0.873818                       # miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 34642.102409                       # average ReadReq miss latency
+system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 43516.263916                       # average WriteReq miss latency
+system.cpu7.l1c.demand_avg_miss_latency::cpu7 38046.102147                       # average overall miss latency
+system.cpu7.l1c.overall_avg_miss_latency::cpu7 38046.102147                       # average overall miss latency
 system.cpu7.l1c.blocked_cycles::no_mshrs    254008986                       # number of cycles access was blocked
 system.cpu7.l1c.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.cpu7.l1c.blocked::no_mshrs               69036                       # number of cycles access was blocked
@@ -927,34 +1320,41 @@ system.cpu7.l1c.avg_blocked_cycles::no_mshrs  3679.369981
 system.cpu7.l1c.avg_blocked_cycles::no_targets     no_value                       # average number of cycles each access was blocked
 system.cpu7.l1c.fast_writes                         0                       # number of fast writes performed
 system.cpu7.l1c.cache_copies                        0                       # number of cache copies performed
-system.cpu7.l1c.writebacks                      11797                       # number of writebacks
-system.cpu7.l1c.demand_mshr_hits                    0                       # number of demand (read+write) MSHR hits
-system.cpu7.l1c.overall_mshr_hits                   0                       # number of overall MSHR hits
-system.cpu7.l1c.ReadReq_mshr_misses             37155                       # number of ReadReq MSHR misses
-system.cpu7.l1c.WriteReq_mshr_misses            23121                       # number of WriteReq MSHR misses
-system.cpu7.l1c.demand_mshr_misses              60276                       # number of demand (read+write) MSHR misses
-system.cpu7.l1c.overall_mshr_misses             60276                       # number of overall MSHR misses
-system.cpu7.l1c.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu7.l1c.ReadReq_mshr_miss_latency   1249829653                       # number of ReadReq MSHR miss cycles
-system.cpu7.l1c.WriteReq_mshr_miss_latency    982928032                       # number of WriteReq MSHR miss cycles
-system.cpu7.l1c.demand_mshr_miss_latency   2232757685                       # number of demand (read+write) MSHR miss cycles
-system.cpu7.l1c.overall_mshr_miss_latency   2232757685                       # number of overall MSHR miss cycles
-system.cpu7.l1c.ReadReq_mshr_uncacheable_latency    901961636                       # number of ReadReq MSHR uncacheable cycles
-system.cpu7.l1c.WriteReq_mshr_uncacheable_latency    558194703                       # number of WriteReq MSHR uncacheable cycles
-system.cpu7.l1c.overall_mshr_uncacheable_latency   1460156339                       # number of overall MSHR uncacheable cycles
-system.cpu7.l1c.ReadReq_mshr_miss_rate       0.830316                       # mshr miss rate for ReadReq accesses
-system.cpu7.l1c.WriteReq_mshr_miss_rate      0.954152                       # mshr miss rate for WriteReq accesses
-system.cpu7.l1c.demand_mshr_miss_rate        0.873818                       # mshr miss rate for demand accesses
-system.cpu7.l1c.overall_mshr_miss_rate       0.873818                       # mshr miss rate for overall accesses
-system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33638.262764                       # average ReadReq mshr miss latency
-system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 42512.349466                       # average WriteReq mshr miss latency
-system.cpu7.l1c.demand_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
-system.cpu7.l1c.overall_avg_mshr_miss_latency 37042.233808                       # average overall mshr miss latency
-system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency          inf                       # average ReadReq mshr uncacheable latency
-system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency          inf                       # average WriteReq mshr uncacheable latency
-system.cpu7.l1c.overall_avg_mshr_uncacheable_latency          inf                       # average overall mshr uncacheable latency
-system.cpu7.l1c.mshr_cap_events                     0                       # number of times MSHR cap was activated
-system.cpu7.l1c.soft_prefetch_mshr_full             0                       # number of mshr full events for SW prefetching instrutions
+system.cpu7.l1c.writebacks::writebacks          11797                       # number of writebacks
+system.cpu7.l1c.writebacks::total               11797                       # number of writebacks
+system.cpu7.l1c.ReadReq_mshr_misses::cpu7        37155                       # number of ReadReq MSHR misses
+system.cpu7.l1c.ReadReq_mshr_misses::total        37155                       # number of ReadReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::cpu7        23121                       # number of WriteReq MSHR misses
+system.cpu7.l1c.WriteReq_mshr_misses::total        23121                       # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7        60276                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total        60276                       # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7        60276                       # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total        60276                       # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7   1249829653                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total   1249829653                       # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7    982928032                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total    982928032                       # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7   2232757685                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total   2232757685                       # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7   2232757685                       # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total   2232757685                       # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7    901961636                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total    901961636                       # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7    558194703                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total    558194703                       # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7   1460156339                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total   1460156339                       # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7     0.830316                       # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7     0.954152                       # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7     0.873818                       # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7     0.873818                       # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 33638.262764                       # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 42512.349466                       # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 37042.233808                       # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7          inf                       # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7          inf                       # average overall mshr uncacheable latency
 system.cpu7.l1c.no_allocate_misses                  0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
index bb6d59ead436fd35b853f6d30a77aab7606431de..b16ace9ba9477599bda57f61e34123b310110b00 100644 (file)
@@ -282,6 +282,7 @@ type=RubyTester
 check_flush=false
 checks_to_complete=100
 deadlock_threshold=50000
+system=system
 wakeup_frequency=10
 cpuPort=system.l1_cntrl0.sequencer.port[0]
 
index df1c9f71b7cd0692f4cf6b07b8fc927a02067d3b..31ca832639286837cd521fab4236b80466a05ae7 100644 (file)
@@ -34,27 +34,26 @@ periodic_stats_period: 1000000
 ================ End RubySystem Configuration Print ================
 
 
-Real time: Feb/12/2012 12:56:15
+Real time: Feb/12/2012 15:33:22
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.46
-Virtual_time_in_minutes: 0.00766667
-Virtual_time_in_hours:   0.000127778
-Virtual_time_in_days:    5.32407e-06
+Virtual_time_in_seconds: 0.95
+Virtual_time_in_minutes: 0.0158333
+Virtual_time_in_hours:   0.000263889
+Virtual_time_in_days:    1.09954e-05
 
 Ruby_current_time: 366301
 Ruby_start_time: 0
 Ruby_cycles: 366301
 
-mbytes_resident: 39.4219
-mbytes_total: 241.242
-resident_ratio: 0.163461
+mbytes_resident: 0
+mbytes_total: 0
 
 ruby_cycles_executed: [ 366302 ]
 
@@ -119,11 +118,11 @@ Resource Usage
 page_size: 4096
 user_time: 0
 system_time: 0
-page_reclaims: 11076
-page_faults: 18
+page_reclaims: 11904
+page_faults: 0
 swaps: 0
-block_inputs: 0
-block_outputs: 0
+block_inputs: 4
+block_outputs: 5
 
 Network Stats
 -------------
index f8914feae0fe8351a8555cdb070239880fdad94e..865d6a91edaae474b9771f8e917a5a192ddfd795 100755 (executable)
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
-Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Feb 12 2012 12:56:01
-gem5 started Feb 12 2012 12:56:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Feb 12 2012 15:33:08
+gem5 started Feb 12 2012 15:33:21
+gem5 executing on Alis-MacBook-Pro.local
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
index 134ffa963906d850415f98b59e4d8a3780669c1a..3c5f9984ce308de7f825e4abf3dbce56bfe086aa 100644 (file)
@@ -4,9 +4,9 @@ sim_seconds                                  0.000366                       # Nu
 sim_ticks                                      366301                       # Number of ticks simulated
 final_tick                                     366301                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1737283                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 247036                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                                 728650                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 266424                       # Number of bytes of host memory used
+host_seconds                                     0.50                       # Real time elapsed on the host
 system.physmem.bytes_read                           0                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read                      0                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written                        0                       # Number of bytes written to this memory