gallium/radeon: get pipe_interleave_bytes AKA group_bytes from the winsys

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index 9a0a30e3a6f36dfb34dfa04d566e0a473cf4b181..61d32c06671fbdc23ae2f95ab77dc7227fe7c590 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -986,7 +986,7 @@ void evergreen_init_color_surface_rat(struct r600_context *rctx,
        unsigned block_size =
                align(util_format_get_blocksize(pipe_buffer->format), 4);
        unsigned pitch_alignment =
-               MAX2(64, rctx->screen->b.tiling_info.group_bytes / block_size);
+               MAX2(64, rctx->screen->b.info.pipe_interleave_bytes / block_size);
        unsigned pitch = align(pipe_buffer->width0, pitch_alignment);
 
        /* XXX: This is copied from evergreen_init_color_surface().  I don't

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index ec1d882f8c016e4188ea98590cb1b8bc1eb6504e..977c5d0d71d0ede78d07b0f4bd454d3d53c037de 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -800,59 +800,6 @@ static boolean r600_fence_finish(struct pipe_screen *screen,
        return rws->fence_wait(rws, rfence->gfx, timeout);
 }
 
-static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
-                                 uint32_t tiling_config)
-{
-       switch ((tiling_config & 0xc0) >> 6) {
-       case 0:
-               rscreen->tiling_info.group_bytes = 256;
-               break;
-       case 1:
-               rscreen->tiling_info.group_bytes = 512;
-               break;
-       default:
-               return false;
-       }
-       return true;
-}
-
-static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
-                                      uint32_t tiling_config)
-{
-       switch ((tiling_config & 0xf00) >> 8) {
-       case 0:
-               rscreen->tiling_info.group_bytes = 256;
-               break;
-       case 1:
-               rscreen->tiling_info.group_bytes = 512;
-               break;
-       default:
-               return false;
-       }
-       return true;
-}
-
-static bool r600_init_tiling(struct r600_common_screen *rscreen)
-{
-       uint32_t tiling_config = rscreen->info.r600_tiling_config;
-
-       /* set default group bytes, overridden by tiling info ioctl */
-       if (rscreen->chip_class <= R700) {
-               rscreen->tiling_info.group_bytes = 256;
-       } else {
-               rscreen->tiling_info.group_bytes = 512;
-       }
-
-       if (!tiling_config)
-               return true;
-
-       if (rscreen->chip_class <= R700) {
-               return r600_interpret_tiling(rscreen, tiling_config);
-       } else {
-               return evergreen_interpret_tiling(rscreen, tiling_config);
-       }
-}
-
 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
                                                  const struct pipe_resource *templ)
 {
@@ -909,9 +856,6 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
        rscreen->chip_class = rscreen->info.chip_class;
        rscreen->debug_flags = debug_get_flags_option("R600_DEBUG", common_debug_options, 0);
 
-       if (!r600_init_tiling(rscreen)) {
-               return false;
-       }
        util_format_s3tc_init();
        pipe_mutex_init(rscreen->aux_context_lock);
        pipe_mutex_init(rscreen->gpu_load_mutex);
@@ -959,6 +903,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
                printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
                printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
                printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
+               printf("pipe_interleave_bytes = %i\n", rscreen->info.pipe_interleave_bytes);
                printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);
                printf("cik_macrotile_mode_array_valid = %i\n", rscreen->info.cik_macrotile_mode_array_valid);
        }

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 52c517fb3e48e4097b5b5d5c3b81e6b062087d34..e92df876c228649f7220f873346015105e9801ea 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -281,17 +281,12 @@ struct r600_surface {
        unsigned pa_su_poly_offset_db_fmt_cntl;
 };
 
-struct r600_tiling_info {
-       unsigned group_bytes;
-};
-
 struct r600_common_screen {
        struct pipe_screen              b;
        struct radeon_winsys            *ws;
        enum radeon_family              family;
        enum chip_class                 chip_class;
        struct radeon_info              info;
-       struct r600_tiling_info         tiling_info;
        uint64_t                        debug_flags;
        bool                            has_cp_dma;
        bool                            has_streamout;

diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c
index 9d91e64ed30088bd13620a3418d6ac745c9ce3c6..27b385bd357ee534d0b765103ca9fa0ea9f9231d 100644 (file)
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -362,7 +362,7 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen,
        unsigned element_bits = 4;
        unsigned cmask_cache_bits = 1024;
        unsigned num_pipes = rscreen->info.num_tile_pipes;
-       unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+       unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
 
        unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes;
        unsigned pixels_per_macro_tile = elements_per_macro_tile * cmask_tile_elements;
@@ -394,7 +394,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen,
                                      struct r600_texture *rtex,
                                      struct r600_cmask_info *out)
 {
-       unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+       unsigned pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
        unsigned num_pipes = rscreen->info.num_tile_pipes;
        unsigned cl_width, cl_height;
 
@@ -569,7 +569,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen,
        slice_elements = (width * height) / (8 * 8);
        slice_bytes = slice_elements * 4;
 
-       pipe_interleave_bytes = rscreen->tiling_info.group_bytes;
+       pipe_interleave_bytes = rscreen->info.pipe_interleave_bytes;
        base_align = num_pipes * pipe_interleave_bytes;
 
        rtex->htile.pitch = width;

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index b4cca0efcec4a682fb5f9bf20335997bd7124aca..ec055180b96d17cb6c6be0fbfb600edca108e040 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -281,6 +281,7 @@ struct radeon_info {
     uint32_t                    r600_tiling_config;
     uint32_t                    num_render_backends;
     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */
+    uint32_t                    pipe_interleave_bytes;
     uint32_t                    enabled_rb_mask; /* GCN harvest config */
 
     /* Tile modes. */

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 2c4de75f8be7b0d222c244724d13c66cf515c262..c956cf489827b321589460543caaafabb79fb8cc 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -265,6 +265,7 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
    ws->info.clock_crystal_freq = ws->amdinfo.gpu_counter_freq;
    ws->info.r600_tiling_config = r600_get_gb_tiling_config(&ws->amdinfo);
    ws->info.num_tile_pipes = cik_get_num_tile_pipes(&ws->amdinfo);
+   ws->info.pipe_interleave_bytes = 256 << ((ws->amdinfo.gb_addr_cfg >> 4) & 0x7);
    ws->info.has_virtual_memory = TRUE;
    ws->info.has_sdma = dma.available_rings != 0;
 

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index f857a14e0338510ddd24dbf7bd93d0c15e709321..f7b8c690b14aea6e4df52917ab46c3405daee8e8 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -390,6 +390,15 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
                 4 << ((ws->info.r600_tiling_config & 0xf0) >> 4) :
                 4 << ((ws->info.r600_tiling_config & 0x30) >> 4);
 
+        ws->info.pipe_interleave_bytes =
+            ws->info.chip_class >= EVERGREEN ?
+                256 << ((ws->info.r600_tiling_config & 0xf00) >> 8) :
+                256 << ((ws->info.r600_tiling_config & 0xc0) >> 6);
+
+        if (!ws->info.pipe_interleave_bytes)
+            ws->info.pipe_interleave_bytes =
+                ws->info.chip_class >= EVERGREEN ? 512 : 256;
+
         if (ws->info.drm_minor >= 11) {
             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
                                  &ws->info.num_tile_pipes);