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diff --git a/openpower/sv/svp64.mdwn b/openpower/sv/svp64.mdwn
index d742556c61cf948c1c27fa9a66f183464f84bad3..b1f672599c597e2911934f0d02ca027a1ec99f3c 100644 (file)
--- a/openpower/sv/svp64.mdwn
+++ b/openpower/sv/svp64.mdwn
@@ -40,6 +40,8 @@ Table of contents
 # Introduction
 
 This document focuses on the encoding of [[SV|sv]], and assumes familiarity with the same. It does not cover how SV works (merely the instruction encoding), and is therefore best read in conjunction with the [[sv/overview]], as well as the [[sv/svp64_quirks]] section.
+It is also crucial to note that whilst this format augments instruction
+behaviour it works in conjunction with SVSTATE and other [[sv/sprs]].
 
 All bit numbers are in MSB0 form (the bits are numbered from 0 at the MSB
 and counting up as you move to the LSB end). All bit ranges are inclusive