verilog: allow spaces in macro arguments

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 752f7a7a8c0cbf373c415102e3e3d36f931b9e56..5a2804a4176628fe2a9ae3aa45de550df70ec54b 100644 (file)
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -392,7 +392,6 @@ static bool read_argument(std::string &dest)
 {
        std::vector<char> openers;
        for (;;) {
-               skip_spaces();
                std::string tok = next_token(true);
                if (tok == ")") {
                        if (openers.empty())

diff --git a/tests/simple/macro_arg_spaces.sv b/tests/simple/macro_arg_spaces.sv
new file mode 100644 (file)
index 0000000..75c4cd1
--- /dev/null
+++ b/tests/simple/macro_arg_spaces.sv
@@ -0,0 +1,28 @@
+module top(
+       input wire [31:0] i,
+       output wire [31:0] x, y, z
+);
+
+`define BAR(a) a
+`define FOO(a = function automatic [31:0] f) a
+
+`BAR(function automatic [31:0] a);
+       input [31:0] i;
+       a = i * 2;
+endfunction
+
+`FOO();
+       input [31:0] i;
+       f = i * 3;
+endfunction
+
+`FOO(function automatic [31:0] b);
+       input [31:0] i;
+       b = i * 5;
+endfunction
+
+assign x = a(i);
+assign y = f(i);
+assign z = b(i);
+
+endmodule