sim: riscv: add missing AC_MSG_RESULT call

Previous commit in here forgot to include this.

diff --git a/sim/configure b/sim/configure
index e25d60c0d901f3fa7009bbc0fb4d0506c42d04fd..1916e1d37f63087c6084778cdc1346477d7a30bd 100755 (executable)
--- a/sim/configure
+++ b/sim/configure
@@ -16279,6 +16279,8 @@ case $target in #(
   *) :
      ;;
 esac
+{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $SIM_RISCV_BITSIZE" >&5
+$as_echo "$SIM_RISCV_BITSIZE" >&6; }
 
 
 { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether sim rx should be cycle accurate" >&5

diff --git a/sim/riscv/acinclude.m4 b/sim/riscv/acinclude.m4
index 29dcaebc61d68cec60403c6b560c94de0d7150b7..0a421f4d4d53c672d86e5da37ffb010fdc58ca32 100644 (file)
--- a/sim/riscv/acinclude.m4
+++ b/sim/riscv/acinclude.m4
@@ -18,4 +18,5 @@ AC_MSG_CHECKING([riscv bitsize])
 SIM_RISCV_BITSIZE=64
 AS_CASE([$target],
        [riscv32*], [SIM_RISCV_BITSIZE=32])
+AC_MSG_RESULT([$SIM_RISCV_BITSIZE])
 AC_SUBST(SIM_RISCV_BITSIZE)