ARM: Decode the scalar saturating add/subtract instructions.
authorGabe Black <gblack@eecs.umich.edu>
Wed, 2 Jun 2010 17:58:05 +0000 (12:58 -0500)
committerGabe Black <gblack@eecs.umich.edu>
Wed, 2 Jun 2010 17:58:05 +0000 (12:58 -0500)
src/arch/arm/isa/decoder/arm.isa
src/arch/arm/isa/formats/data.isa

index bfb89b22a3504c5a729a7f71c632df72bbf77a37..050571240efed71f14fe28253747dd65bdfa1f6c 100644 (file)
@@ -116,12 +116,7 @@ format DataOp {
                     0x3: decode OPCODE {
                         0x9: ArmBlxReg::armBlxReg();
                     }
-                    0x5: decode OPCODE {
-                        0x8: WarnUnimpl::qadd();
-                        0x9: WarnUnimpl::qsub();
-                        0xa: WarnUnimpl::qdadd();
-                        0xb: WarnUnimpl::qdsub();
-                    }
+                    0x5: ArmSatAddSub::armSatAddSub();
                 }
                 0x1: ArmHalfWordMultAndMultAcc::armHalfWordMultAndMultAcc();
             }
index 355a41038f95e2b5485a0c6bc1575219d698c5d6..f6e093b80a19134fcad7de752c24b4b227d568b1 100644 (file)
@@ -341,6 +341,28 @@ def format ArmDataProcImm() {{
     '''
 }};
 
+def format ArmSatAddSub() {{
+    decode_block = '''
+    {
+        IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+        IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+        IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+        switch (OPCODE) {
+          case 0x8:
+            return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
+          case 0x9:
+            return new QsubRegCc(machInst, rd, rm, rn, 0, LSL);
+          case 0xa:
+            return new QdaddRegCc(machInst, rd, rm, rn, 0, LSL);
+          case 0xb:
+            return new QdsubRegCc(machInst, rd, rm, rn, 0, LSL);
+          default:
+            return new Unknown(machInst);
+        }
+    }
+    '''
+}};
+
 def format Thumb16ShiftAddSubMoveCmp() {{
     decode_block = '''
     {