clarify

diff --git a/openpower/sv/rfc/ls001.mdwn b/openpower/sv/rfc/ls001.mdwn
index be389e575826214739b022528267a301c41b5e35..d4cf3eb17de47f273bb94e6c67149159afff08de 100644 (file)
--- a/openpower/sv/rfc/ls001.mdwn
+++ b/openpower/sv/rfc/ls001.mdwn
@@ -247,9 +247,9 @@ count and reducing assembler complexity are:
   found in Vector ISAs (VEXTRACT, VINSERT etc) again with no need
   to actually provide explicit such instructions.
 * **Saturation**. **all** LD/ST and Arithmetic and Logical operations may
-  be saturated (without adding explicit scalar saturated opcodes)
+  be saturated (without adding explicit saturated opcodes)
 * **Reduction and Prefix-Sum** (Fibonnacci Series) Modes, including a
-  "Reverse Gear".
+  "Reverse Gear" (running loops in reverse order).
 * **vec2/3/4 "Packing" and "Unpacking"** (similar to VSX `vpack` and `vpkss`)
   accessible in a way that is easier than REMAP, added for the same reasons
   that drove `vpack` and `vpkss` etc. to be added: pixel, audio, and 3D