format table

diff --git a/HDL_workflow/ECP5_FPGA.mdwn b/HDL_workflow/ECP5_FPGA.mdwn
index 83d1c6ab17493041e871c7d508b893bc9e825d18..e4d7f823509a4e5393ad757d1e8c7d02b4f8a607 100644 (file)
--- a/HDL_workflow/ECP5_FPGA.mdwn
+++ b/HDL_workflow/ECP5_FPGA.mdwn
@@ -165,9 +165,9 @@ Additionally, does the note in the schematic about needing to swap EVEN and ODD
 
 # VERSA ECP5 Connections
 
-|-------------|-------------|----------------|-----------|
-|             |             |STLINKV2  JTAG  |           |
-|    pin #    | FPGA IO PAD | Pin #  (Signal)|Wire Colour|
+Table of connections:
+
+| X3  pin #   | FPGA IO PAD | STLinkv2       |Wire Colour|
 |-------------|-------------|----------------|-----------|
 |1 GND        | GND         | GND            |   Black   |
 |2 NC         |NOT CONNECTED| NOT CONNECTED  |    NC     |