arm: invalidate TLB miscreg cache on modification of HSCTLR

Change-Id: I5212c91c56435fe008950ed99feacc6921609226

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 0b753087e923944df783bacd0e78909d8e092646..c90de133769902eba20777919b340cc189d6626c 100644 (file)
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2015 ARM Limited
+ * Copyright (c) 2010-2016 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -1629,6 +1629,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
           case MISCREG_TCR_EL3:
           case MISCREG_SCTLR_EL2:
           case MISCREG_SCTLR_EL3:
+          case MISCREG_HSCTLR:
           case MISCREG_TTBR0_EL1:
           case MISCREG_TTBR1_EL1:
           case MISCREG_TTBR0_EL2: