opcodes/arm: adjust whitespace in cpsie instruction

While I was working on the disassembler styling for ARM I noticed that
the whitespace in the cpsie instruction was inconsistent with most of
the other ARM disassembly output, the disassembly for cpsie looks like
this:

  cpsie   if,#10

notice there's no space before the '#10' immediate, most other ARM
instructions have a space before each operand.

This commit updates the disassembler to add the missing space, and
updates the tests I found that tested this instruction.

diff --git a/gas/testsuite/gas/arm/archv6.d b/gas/testsuite/gas/arm/archv6.d
index bee9909f2aff2d56bf786b0de51b343d806af3fa..ec609b51237ef7db445e29ed04f45eeb02974d4d 100644 (file)
--- a/gas/testsuite/gas/arm/archv6.d
+++ b/gas/testsuite/gas/arm/archv6.d
@@ -219,7 +219,7 @@ Disassembly of section .text:
 0+34c <[^>]*> e6ef2475 ?       uxtb    r2, r5, ror #8
 0+350 <[^>]*> 16ef2075 ?       uxtbne  r2, r5
 0+354 <[^>]*> 16ef2475 ?       uxtbne  r2, r5, ror #8
-0+358 <[^>]*> f10a00ca ?       cpsie   if,#10
-0+35c <[^>]*> f10a00d5 ?       cpsie   if,#21
+0+358 <[^>]*> f10a00ca ?       cpsie   if, #10
+0+35c <[^>]*> f10a00d5 ?       cpsie   if, #21
 0+360 <[^>]*> f8cd0510 ?       srsia   sp, #16
 0+364 <[^>]*> f9ed0510 ?       srsib   sp!, #16

diff --git a/gas/testsuite/gas/arm/t16-bad.s b/gas/testsuite/gas/arm/t16-bad.s
index 9d2ced3ca3df1364c7045a0c4fc8421b9bfcc557..8b0865da693cb43e0f274bd275d1f297d1ff13c0 100644 (file)
--- a/gas/testsuite/gas/arm/t16-bad.s
+++ b/gas/testsuite/gas/arm/t16-bad.s
@@ -131,8 +131,8 @@ l:
 
        @ Miscellaneous
        bkpt    #257
-       cpsie   ai,#5
-       cpsid   ai,#5
+       cpsie   ai, #5
+       cpsid   ai, #5
 
        @ Conditional suffixes
        addeq   r0,r1,r2

diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c
index dffbad3e52589e9a6aaf8097cc749a12ddbf41fa..b71ab984e193ee895c767ec3354c859aa364c757 100644 (file)
--- a/opcodes/arm-dis.c
+++ b/opcodes/arm-dis.c
@@ -3828,11 +3828,11 @@ static const struct opcode32 arm_opcodes[] =
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     0xf1080000, 0xfffffe3f, "cpsie\t%{B:%8'a%7'i%6'f%}"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
-    0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
+    0xf10a0000, 0xfffffe20, "cpsie\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     0xf10C0000, 0xfffffe3f, "cpsid\t%{B:%8'a%7'i%6'f%}"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
-    0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%},%{I:#%0-4d%}"},
+    0xf10e0000, 0xfffffe20, "cpsid\t%{B:%8'a%7'i%6'f%}, %{I:#%0-4d%}"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),
     0xf1000000, 0xfff1fe20, "cps\t%{I:#%0-4d%}"},
   {ARM_FEATURE_CORE_LOW (ARM_EXT_V6),