Trivial.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
cmd_buffer->queue_family_index = pool->queue_family_index;
} else {
- /* Init the pool_link so we can safefly call list_del when we destroy
+ /* Init the pool_link so we can safely call list_del when we destroy
* the command buffer
*/
list_inithead(&cmd_buffer->pool_link);
}
/*
- *with DCC some colors don't require CMASK elimiation before being
+ * With DCC some colors don't require CMASK elimination before being
* used as a texture. This sets a predicate value to determine if the
* cmask eliminate is required.
*/
/*
* Pipeline layouts. These have nothing to do with the pipeline. They are
- * just muttiple descriptor set layouts pasted together
+ * just multiple descriptor set layouts pasted together.
*/
VkResult radv_CreatePipelineLayout(
(device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
(device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
- /* The gpu id is already embeded in the uuid so we just pass "radv"
+ /* The gpu id is already embedded in the uuid so we just pass "radv"
* when creating the cache.
*/
char buf[VK_UUID_SIZE * 2 + 1];
device->rad_info.family == CHIP_RAVEN;
}
- /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
+ /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
* on SI.
*/
device->has_clear_state = device->rad_info.chip_class >= CIK;
* evenly between CUs. The number is only a function of the number of CUs.
* We can decrease the constant to decrease the scratch buffer size.
*
- * sctx->scratch_waves must be >= the maximum posible size of
+ * sctx->scratch_waves must be >= the maximum possible size of
* 1 threadgroup, so that the hw doesn't hang from being unable
* to start any.
*
uint32_t num;
};
-/* We use a big string constant to avoid lots of reloctions from the entry
+/* We use a big string constant to avoid lots of relocations from the entry
* point table to lots of little strings. The entries in the entry point table
* store the index into this big string.
*/
else
return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
default:
- unreachable("illegale image type");
+ unreachable("illegal image type");
}
}
if (device->physical_device->rad_info.chip_class >= GFX9) {
unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
- /* Depth is the the last accessible layer on Gfx9.
+ /* Depth is the last accessible layer on Gfx9.
* The hw doesn't need to know the total number of layers.
*/
if (type == V_008F1C_SQ_RSRC_IMG_3D)
/* get current basic block */
current_block = LLVMGetInsertBlock(ctx->ac.builder);
- /* chqeck if there's another block after this one */
+ /* check if there's another block after this one */
next_block = LLVMGetNextBasicBlock(current_block);
if (next_block) {
/* insert the new block before the next block */
outer[i] = LLVMGetUndef(ctx->ac.i32);
}
- // LINES reverseal
+ // LINES reversal
if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,