genrtlil: add width detection for AST_PREFIX nodes

diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 90d5f1bba11ca21c50f07e8f971addf96ec15105..45aab9d8ebee32e7682a1ffb5a5e927890b561ac 100644 (file)
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -993,6 +993,14 @@ void AstNode::detectSignWidthWorker(int &width_hint, bool &sign_hint, bool *foun
                break;
        }
 
+       case AST_PREFIX:
+               // Prefix nodes always resolve to identifiers in generate loops, so we
+               // can simply perform the resolution to determine the sign and width.
+               simplify(true, false, false, 1, -1, false, false);
+               log_assert(type == AST_IDENTIFIER);
+               detectSignWidthWorker(width_hint, sign_hint, found_real);
+               break;
+
        case AST_FCALL:
                if (str == "\\$anyconst" || str == "\\$anyseq" || str == "\\$allconst" || str == "\\$allseq") {
                        if (GetSize(children) == 1) {

diff --git a/tests/simple/loop_prefix_case.v b/tests/simple/loop_prefix_case.v
new file mode 100644 (file)
index 0000000..7ee28ed
--- /dev/null
+++ b/tests/simple/loop_prefix_case.v
@@ -0,0 +1,18 @@
+module top(
+       input wire x,
+       output reg y
+);
+       localparam I = 1;
+       genvar i;
+       generate
+               for (i = 0; i < 1; i = i + 1) begin : blk
+                       wire [i:i] z = x;
+               end
+       endgenerate
+       always @* begin
+               case (blk[I - 1].z)
+                       1: y = 0;
+                       0: y = 1;
+               endcase
+       end
+endmodule