continue;
}
+ if (sq != SQ_ALU && outstanding_lds_oq)
+ continue;
+
if (!bu_ready_next[sq].empty())
bu_ready[sq].splice(bu_ready[sq].end(), bu_ready_next[sq]);
}
// simple heuristic to limit register pressure,
- if (sq == SQ_ALU && live_count > rp_threshold &&
+ if (sq == SQ_ALU && live_count > rp_threshold && !outstanding_lds_oq &&
(!bu_ready[SQ_TEX].empty() ||
!bu_ready[SQ_VTX].empty() ||
!bu_ready_next[SQ_TEX].empty() ||
check_alu_ready_count(24))
break;
+
+ if (sq == SQ_ALU && n->consumes_lds_oq() &&
+ (bu_ready[SQ_TEX].size() || bu_ready[SQ_VTX].size() || bu_ready[SQ_GDS].size())) {
+ GCM_DUMP( sblog << "switching scheduling due to lds op\n"; );
+ break;
+ }
bu_ready[sq].pop_front();
if (sq != SQ_CF) {
assert(op_map[n].bottom_bb == bu_bb);
+ if (n->produces_lds_oq())
+ outstanding_lds_oq--;
+ if (n->consumes_lds_oq())
+ outstanding_lds_oq++;
bu_release_defs(n->src, true);
bu_release_defs(n->dst, false);
sched_queue ready;
sched_queue ready_above;
+ unsigned outstanding_lds_oq;
container_node pending;
struct op_info {
gcm(shader &sh) : pass(sh),
bu_ready(), bu_ready_next(), bu_ready_early(),
- ready(), op_map(), uses(), nuc_stk(1), ucs_level(),
+ ready(), outstanding_lds_oq(),
+ op_map(), uses(), nuc_stk(1), ucs_level(),
bu_bb(), pending_defs(), pending_nodes(), cur_sq(),
live(), live_count(), pending_exec_mask_update() {}