Add "verilog_defines -list" and "verilog_defines -reset"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 0e2bead6f905a99dd1d2e146235038c18052d152..058d750c394522a2911edcb43be4f75cb8872e21 100644 (file)
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -553,6 +553,12 @@ struct VerilogDefines : public Pass {
                log("    -Uname[=definition]\n");
                log("        undefine the preprocessor symbol 'name'\n");
                log("\n");
+               log("    -reset\n");
+               log("        clear list of defined preprocessor symbols\n");
+               log("\n");
+               log("    -list\n");
+               log("        list currently defined preprocessor symbols\n");
+               log("\n");
        }
        void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
        {
@@ -588,6 +594,16 @@ struct VerilogDefines : public Pass {
                                design->verilog_defines.erase(name);
                                continue;
                        }
+                       if (arg == "-reset") {
+                               design->verilog_defines.clear();
+                               continue;
+                       }
+                       if (arg == "-list") {
+                               for (auto &it : design->verilog_defines) {
+                                       log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str());
+                               }
+                               continue;
+                       }
                        break;
                }