test/test_fifo, genlib/fifo: move test to unittest

diff --git a/migen/genlib/fifo.py b/migen/genlib/fifo.py
index b9769d8e24afc3dbab69f5857ccebdbc689a59fe..ad478ef0a580c5a345ac3225718dc8fa97aa13e4 100644 (file)
--- a/migen/genlib/fifo.py
+++ b/migen/genlib/fifo.py
@@ -178,28 +178,3 @@ class AsyncFIFO(Module, _FIFOInterface):
                        rdport.adr.eq(consume.q_next_binary[:-1]),
                        self.dout_bits.eq(rdport.dat_r)
                ]
-
-class _SyncFIFOTB(Module):
-       def __init__(self):
-               self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
-
-               self.sync += [
-                       If(self.dut.we & self.dut.writable, 
-                               self.dut.din.a.eq(self.dut.din.a + 1),
-                               self.dut.din.b.eq(self.dut.din.b + 2)
-                       )
-               ]
-               
-       def do_simulation(self, s):
-               s.wr(self.dut.we, s.cycle_counter % 4 == 0)
-               s.wr(self.dut.re, s.cycle_counter % 3 == 0)
-               print("readable: {0} re: {1} data: {2}/{3}".format(s.rd(self.dut.readable),
-                       s.rd(self.dut.re),
-                       s.rd(self.dut.dout.a), s.rd(self.dut.dout.b)))
-
-def _main():
-       from migen.sim.generic import Simulator
-       Simulator(_SyncFIFOTB()).run(20)
-
-if __name__ == "__main__":
-       _main()

diff --git a/migen/test/test_fifo.py b/migen/test/test_fifo.py
new file mode 100644 (file)
index 0000000..c7667f0
--- /dev/null
+++ b/migen/test/test_fifo.py
@@ -0,0 +1,35 @@
+import unittest
+
+from migen.fhdl.std import *
+from migen.genlib.fifo import SyncFIFO, AsyncFIFO
+
+from .support import SimCase, SimBench
+
+class SyncFIFOCase(SimCase):
+       class TestBench(SimBench):
+               def __init__(self):
+                       self.submodules.dut = SyncFIFO([("a", 32), ("b", 32)], 2)
+
+                       self.sync += [
+                               If(self.dut.we & self.dut.writable,
+                                       self.dut.din.a.eq(self.dut.din.a + 1),
+                                       self.dut.din.b.eq(self.dut.din.b + 2)
+                               )
+                       ]
+
+       def test_sizes(self):
+               self.assertEqual(flen(self.tb.dut.din_bits), 64)
+               self.assertEqual(flen(self.tb.dut.dout_bits), 64)
+
+       def test_run_sequence(self):
+               seq = list(range(20))
+               def cb(tb, s):
+                       # fire re and we at "random"
+                       s.wr(tb.dut.we, s.cycle_counter % 2 == 0)
+                       s.wr(tb.dut.re, s.cycle_counter % 3 == 0)
+                       # the output if valid must be correct
+                       if s.rd(tb.dut.readable) and s.rd(tb.dut.re):
+                               i = seq.pop(0)
+                               self.assertEqual(s.rd(tb.dut.dout.a), i)
+                               self.assertEqual(s.rd(tb.dut.dout.b), i*2)
+               self.run_with(cb, 20)