FP32 is called BFP32 by IBM (ls005), see ls002

diff --git a/openpower/sv/rfc/ls005.mdwn b/openpower/sv/rfc/ls005.mdwn
index 19b0ae35efe27431e5ec785b1074ff21a0a11107..a16fcf222bc7245dbb60ca4c7c7eec0badf0fa82 100644 (file)
--- a/openpower/sv/rfc/ls005.mdwn
+++ b/openpower/sv/rfc/ls005.mdwn
@@ -99,12 +99,12 @@ whether (and how many) sequentially-grouped registers are taken together to
 create 16-bit, 32-bit and 64-bit addresses (depending on application need).
 GPR is obvious, FPR is quirky.  SVP64 redefines FP ops (those not ending in "s")
 to be "full width" and all ops ending in "s" to be "half of
-the FP width".
+the full width".
 
 * XLEN=64 keeps FPR "full width" exactly as presently defined, and
   "half width" exactly as presently defined.
 * XLEN=32 overrides FPR "full width" operations to
-  full FP32, and "half width" to be "FP16 stored in an FP32"
+  full BFP32, and "half width" to be "BFP16 stored in an BFP32"
 * XLEN=16 redefines FPR "full width" operations to full [IEEE FP16](https://en.wikipedia.org/wiki/Half-precision_floating-point_format) and leaves
   "half width" UNDEFINED (there is no IEEE FP8).
 * XLEN=8 redefines FPR "full width" operations to [BF16 (bfloat16)](https://en.wikipedia.org/wiki/Bfloat16_floating-point_format) and leaves