fi
-libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
+libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv-elf/lib/libopcodes.a
as_ac_File=`$as_echo "ac_cv_file_$libopc" | $as_tr_sh`
{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $libopc" >&5
$as_echo_n "checking for $libopc... " >&6; }
run = true;
}
+extern "C" int print_insn_little_riscv(bfd_vma, disassemble_info*);
+
void processor_t::disasm(insn_t insn, reg_t pc)
{
printf("core %3d: 0x%016llx (0x%08x) ",id,(unsigned long long)pc,insn.bits);
disassemble_info info;
INIT_DISASSEMBLE_INFO(info, stdout, fprintf);
info.flavour = bfd_target_unknown_flavour;
- info.arch = bfd_arch_mips;
- info.mach = 101; // XXX bfd_mach_mips_riscv requires modified bfd.h
+ info.arch = bfd_architecture(25); // bfd_arch_riscv
+ info.mach = 164; // bfd_mach_riscv_rocket64
info.endian = BFD_ENDIAN_LITTLE;
info.buffer = (bfd_byte*)&insn;
info.buffer_length = sizeof(insn);
info.buffer_vma = pc;
- int ret = print_insn_little_mips(pc, &info);
+ int ret = print_insn_little_riscv(pc, &info);
assert(ret == insn_length(insn.bits));
#else
printf("unknown");
AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
])
-libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv/lib/libopcodes.a
+libopc=`dirname \`which riscv-gcc\``/../`$ac_config_guess`/riscv-elf/lib/libopcodes.a
AC_CHECK_FILES([$libopc],[have_libopcodes="yes"],[have_libopcodes="no"])
libbfd="/opt/local/lib/libbfd.dylib"