Remove unused Minerva CPU import from headless examples

The headless examples do not use an embedded CPU. Instead, the host
computer commands the Gram controller via a Wishbone-UART bridge.

diff --git a/examples/headless-ecpix5.py b/examples/headless-ecpix5.py
index 8e1bd2046a947cf3d0c45f501c8082ee3557c810..da7333b8de38a3691a4f4dd903606888fcd33ed7 100644 (file)
--- a/examples/headless-ecpix5.py
+++ b/examples/headless-ecpix5.py
@@ -4,7 +4,6 @@ from nmigen import *
 from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
 
-from lambdasoc.cpu.minerva import MinervaCPU
 from lambdasoc.periph.intc import GenericInterruptController
 from lambdasoc.periph.serial import AsyncSerialPeripheral
 from lambdasoc.periph.sram import SRAMPeripheral

diff --git a/examples/headless-versa-85.py b/examples/headless-versa-85.py
index 3050f8966ff90e57d6e0d049cc6e9d2642b43cce..371a8688f0f606e1dda90c9d3f440729197ef30e 100644 (file)
--- a/examples/headless-versa-85.py
+++ b/examples/headless-versa-85.py
@@ -5,7 +5,6 @@ from nmigen import *
 from nmigen.lib.cdc import ResetSynchronizer
 from nmigen_soc import wishbone, memory
 
-from lambdasoc.cpu.minerva import MinervaCPU
 from lambdasoc.periph.intc import GenericInterruptController
 from lambdasoc.periph.serial import AsyncSerialPeripheral
 from lambdasoc.periph.sram import SRAMPeripheral