me->flags &= ~PKE_FLAG_INT_NOLOOP;
/* mask interrupt bit from instruction word so re-decoded instructions don't stall */
BIT_MASK_SET(fw, PKE_OPCODE_I_B, PKE_OPCODE_I_E, 0);
+ intr = 0;
}
else /* new interrupt-flagged instruction */
{
if(PKE_REG_MASK_GET(me, STAT, PPS) == PKE_REG_STAT_PPS_IDLE)
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_DECODE);
+ /* handle [new - first time] interrupts */
+ if(intr)
+ {
+ PKE_REG_MASK_SET(me, STAT, PIS, 1);
+ PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
+ /* presume stall state follows; only PKEMARK may go ahead anyway */
+ }
+
/* decode & execute */
- if(IS_PKE_CMD(cmd, PKENOP))
+ if(IS_PKE_CMD(cmd, PKENOP) && !intr)
pke_code_nop(me, fw);
- else if(IS_PKE_CMD(cmd, STCYCL))
+ else if(IS_PKE_CMD(cmd, STCYCL) && !intr)
pke_code_stcycl(me, fw);
- else if(me->pke_number == 1 && IS_PKE_CMD(cmd, OFFSET))
+ else if(me->pke_number == 1 && IS_PKE_CMD(cmd, OFFSET) && !intr)
pke_code_offset(me, fw);
- else if(me->pke_number == 1 && IS_PKE_CMD(cmd, BASE))
+ else if(me->pke_number == 1 && IS_PKE_CMD(cmd, BASE) && !intr)
pke_code_base(me, fw);
- else if(IS_PKE_CMD(cmd, ITOP))
+ else if(IS_PKE_CMD(cmd, ITOP) && !intr)
pke_code_itop(me, fw);
- else if(IS_PKE_CMD(cmd, STMOD))
+ else if(IS_PKE_CMD(cmd, STMOD) && !intr)
pke_code_stmod(me, fw);
- else if(me->pke_number == 1 && IS_PKE_CMD(cmd, MSKPATH3))
+ else if(me->pke_number == 1 && IS_PKE_CMD(cmd, MSKPATH3) && !intr)
pke_code_mskpath3(me, fw);
else if(IS_PKE_CMD(cmd, PKEMARK))
pke_code_pkemark(me, fw);
- else if(IS_PKE_CMD(cmd, FLUSHE))
+ else if(IS_PKE_CMD(cmd, FLUSHE) && !intr)
pke_code_flushe(me, fw);
- else if(me->pke_number == 1 && IS_PKE_CMD(cmd, FLUSH))
+ else if(me->pke_number == 1 && IS_PKE_CMD(cmd, FLUSH) && !intr)
pke_code_flush(me, fw);
- else if(me->pke_number == 1 && IS_PKE_CMD(cmd, FLUSHA))
+ else if(me->pke_number == 1 && IS_PKE_CMD(cmd, FLUSHA) && !intr)
pke_code_flusha(me, fw);
- else if(IS_PKE_CMD(cmd, PKEMSCAL))
+ else if(IS_PKE_CMD(cmd, PKEMSCAL) && !intr)
pke_code_pkemscal(me, fw);
- else if(IS_PKE_CMD(cmd, PKEMSCNT))
+ else if(IS_PKE_CMD(cmd, PKEMSCNT) && !intr)
pke_code_pkemscnt(me, fw);
- else if(me->pke_number == 1 && IS_PKE_CMD(cmd, PKEMSCALF))
+ else if(me->pke_number == 1 && IS_PKE_CMD(cmd, PKEMSCALF) && !intr)
pke_code_pkemscalf(me, fw);
- else if(IS_PKE_CMD(cmd, STMASK))
+ else if(IS_PKE_CMD(cmd, STMASK) && !intr)
pke_code_stmask(me, fw);
- else if(IS_PKE_CMD(cmd, STROW))
+ else if(IS_PKE_CMD(cmd, STROW) && !intr)
pke_code_strow(me, fw);
- else if(IS_PKE_CMD(cmd, STCOL))
+ else if(IS_PKE_CMD(cmd, STCOL) && !intr)
pke_code_stcol(me, fw);
- else if(IS_PKE_CMD(cmd, MPG))
+ else if(IS_PKE_CMD(cmd, MPG) && !intr)
pke_code_mpg(me, fw);
- else if(IS_PKE_CMD(cmd, DIRECT))
+ else if(IS_PKE_CMD(cmd, DIRECT) && !intr)
pke_code_direct(me, fw);
- else if(IS_PKE_CMD(cmd, DIRECTHL))
+ else if(IS_PKE_CMD(cmd, DIRECTHL) && !intr)
pke_code_directhl(me, fw);
- else if(IS_PKE_CMD(cmd, UNPACK))
+ else if(IS_PKE_CMD(cmd, UNPACK) && !intr)
pke_code_unpack(me, fw);
/* ... no other commands ... */
else
void
pke_code_nop(struct pke_device* me, unsigned_4 pkecode)
{
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* done */
pke_pc_advance(me, 1);
PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_IDLE);
{
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* copy immediate value into CYCLE reg */
PKE_REG_MASK_SET(me, CYCLE, WL, BIT_MASK_GET(imm, 8, 15));
PKE_REG_MASK_SET(me, CYCLE, CL, BIT_MASK_GET(imm, 0, 7));
{
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* copy 10 bits to OFFSET field */
PKE_REG_MASK_SET(me, OFST, OFFSET, BIT_MASK_GET(imm, 0, 9));
/* clear DBF bit */
{
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* copy 10 bits to BASE field */
PKE_REG_MASK_SET(me, BASE, BASE, BIT_MASK_GET(imm, 0, 9));
/* done */
{
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* copy 10 bits to ITOPS field */
PKE_REG_MASK_SET(me, ITOPS, ITOPS, BIT_MASK_GET(imm, 0, 9));
/* done */
{
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* copy 2 bits to MODE register */
PKE_REG_MASK_SET(me, MODE, MDE, BIT_MASK_GET(imm, 0, 2));
/* done */
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
unsigned_4 gif_mode;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* set appropriate bit */
if(BIT_MASK_GET(imm, PKE_REG_MSKPATH3_B, PKE_REG_MSKPATH3_E) != 0)
gif_mode = GIF_REG_MODE_M3R_MASK;
void
pke_code_pkemark(struct pke_device* me, unsigned_4 pkecode)
{
- /* ignore possible interrupt stall */
-
int imm = BIT_MASK_GET(pkecode, PKE_OPCODE_IMM_B, PKE_OPCODE_IMM_E);
/* copy 16 bits to MARK register */
PKE_REG_MASK_SET(me, MARK, MARK, BIT_MASK_GET(imm, 0, 15));
void
pke_code_flushe(struct pke_device* me, unsigned_4 pkecode)
{
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute next PEW bit */
if(pke_check_stall(me, chk_vu))
{
{
int something_busy = 0;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute next PEW, PGW bits */
if(pke_check_stall(me, chk_vu))
{
{
int something_busy = 0;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute next PEW, PGW bits */
if(pke_check_stall(me, chk_vu))
{
void
pke_code_pkemscal(struct pke_device* me, unsigned_4 pkecode)
{
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute next PEW bit */
if(pke_check_stall(me, chk_vu))
{
void
pke_code_pkemscnt(struct pke_device* me, unsigned_4 pkecode)
{
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute next PEW bit */
if(pke_check_stall(me, chk_vu))
{
{
int something_busy = 0;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute next PEW, PGW bits */
if(pke_check_stall(me, chk_vu))
{
{
unsigned_4* mask;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* check that FIFO has one more word for STMASK operand */
mask = pke_pc_operand(me, 1);
if(mask != NULL)
/* check that FIFO has four more words for STROW operand */
unsigned_4* last_op;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
last_op = pke_pc_operand(me, 4);
if(last_op != NULL)
{
/* check that FIFO has four more words for STCOL operand */
unsigned_4* last_op;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
last_op = pke_pc_operand(me, 4);
if(last_op != NULL)
{
if(me->qw_pc != 3 && me->qw_pc != 1)
return pke_code_error(me, pkecode);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* map zero to max+1 */
if(num==0) num=0x100;
if(me->qw_pc != 3)
return pke_code_error(me, pkecode);
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* map zero to max+1 */
if(imm==0) imm=0x10000;
int n, num_operands;
unsigned_4* last_operand_word = NULL;
- /* handle interrupts */
- if(BIT_MASK_GET(pkecode, PKE_OPCODE_I_B, PKE_OPCODE_I_E))
- {
- PKE_REG_MASK_SET(me, STAT, PIS, 1);
- PKE_REG_MASK_SET(me, STAT, PPS, PKE_REG_STAT_PPS_STALL);
- return;
- }
-
/* compute PKEcode length, as given in CPU2 spec, v2.1 pg. 11 */
if(wl <= cl)
n = num;