(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64/discussion.mdwn b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
index 6b8afe2bf2d89238bb5f88cd32f5a6f5fb333515..401fc3498ae3a4d63aec03f6de7ad639a5cfe07a 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64/discussion.mdwn
+++ b/openpower/sv/svp_rewrite/svp64/discussion.mdwn
@@ -39,7 +39,7 @@ mode:
 
 * zmode: 2 bit src pred zero mode, dest pred zero mode
 * ffirst: 3 bit.  EN (and CR index bit 0-3, applicable when Rc=1).
-   operations that do not have Rc may take bit 1 to mean "invert test"
+   operations that do not have Rc or when Rc=0 may take bit 1 to mean " zero ir nonzero".
 
 ## twin predication, CR based.