radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 7d4ce6108478b751f3cf4463bd4cf2e3f22594e5..d37df6b986af61deff8dedfdce7d6621dd04bc72 100644 (file)
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -139,8 +139,6 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                   Op.getOperand(2));
     case AMDGPUIntrinsic::AMDIL_round_nearest:
       return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
-    case AMDGPUIntrinsic::AMDIL_round_posinf:
-      return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
   }
 }
 

diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td b/src/gallium/drivers/radeon/AMDILIntrinsics.td
index 213c8bbfbb7f510ccb5fdceb49feb528434548e3..3f9e20f0c8545d3263dfdd3846a1f8b4d8f71578 100644 (file)
--- a/src/gallium/drivers/radeon/AMDILIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td
@@ -146,8 +146,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
           UnaryIntFloat;
   def int_AMDIL_round_neginf : GCCBuiltin<"__amdil_round_neginf">,
           UnaryIntFloat;
-  def int_AMDIL_round_posinf : GCCBuiltin<"__amdil_round_posinf">,
-          UnaryIntFloat;
   def int_AMDIL_round_zero : GCCBuiltin<"__amdil_round_zero">,
           UnaryIntFloat;
   def int_AMDIL_acos : GCCBuiltin<"__amdil_acos">,

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 3b251938774dce59af92cd472ee36302556ebfb7..57ec372d097e1095e4d6355287852b1f41d31a39 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1117,8 +1117,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context * ctx)
        bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
        bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
        bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
-       bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_nomem;
-       bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "llvm.AMDIL.round.posinf.";
+       bld_base->op_actions[TGSI_OPCODE_CEIL].emit = build_tgsi_intrinsic_readonly;
+       bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";