Two fixes to try and get TLB miss cost more in line with real platform:

1) Add fault_handler_delay param to FullCPU to wait N cycles after
committing faulting instruction before fetching fault handler.
2) Make hw_rei a serializing instruction (flushes pipe, basically).

arch/alpha/isa_desc:
    Make hw_rei a serializing instruction (guarantees previous insts
    complete before hw_rei will issue).

--HG--
extra : convert_revision : 704cef65b3869be9eee724055cedb22114a78359

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index 6a6bca4fe2b65a144218b0d1656b295c1be46131..0e07400d37154733578dda3d24b45a45300af063 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2566,7 +2566,7 @@ decode OPCODE default Unknown::unknown() {
     }
 
     format BasicOperate {
-       0x1e: hw_rei({{ xc->hwrei(); }});
+       0x1e: hw_rei({{ xc->hwrei(); }}, IsSerializing);
 
        // M5 special opcodes use the reserved 0x01 opcode space
        0x01: decode M5FUNC {