RTLIL::SigSpec sig_co = cell->getPort("\\CO");
bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def());
- sig_a.extend(SIZE(sig_y), signed_a);
- sig_b.extend(SIZE(sig_y), signed_b);
+ sig_a.extend_u0(SIZE(sig_y), signed_a);
+ sig_b.extend_u0(SIZE(sig_y), signed_b);
bool carry = sig_ci[0] == RTLIL::S1;
bool b_inv = sig_bi[0] == RTLIL::S1;
std::vector<int> undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep);
std::vector<int> undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep);
- extendSignalWidth(undef_a, undef_b, undef_y, cell, true);
- extendSignalWidth(undef_a, undef_b, undef_x, cell, true);
- extendSignalWidth(undef_a, undef_b, undef_co, cell, true);
+ extendSignalWidth(undef_a, undef_b, undef_y, cell);
+ extendSignalWidth(undef_a, undef_b, undef_x, cell);
+ extendSignalWidth(undef_a, undef_b, undef_co, cell);
std::vector<int> all_inputs_undef;
all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end());
undefGating(x, def_x, undef_x);
undefGating(co, def_co, undef_co);
}
- log_ping();
return true;
}