Fix VerificImporter asymmetric memories error message

Signed-off-by: Clifford Wolf <clifford@clifford.at>

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 61d9d593cf17a82f3796ee07ae4f52d6ee294c18..5280a2b9c12c81582b1baaf4a04d876a776bd725 100644 (file)
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1201,7 +1201,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
                {
                        RTLIL::Memory *memory = module->memories.at(RTLIL::escape_id(inst->GetOutput()->Name()));
                        if (memory->width != int(inst->Input2Size()))
-                               log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetInput()->Name());
+                               log_error("Import of asymmetric memories of this type is not supported yet: %s %s\n", inst->Name(), inst->GetOutput()->Name());
 
                        RTLIL::SigSpec addr = operatorInput1(inst);
                        RTLIL::SigSpec data = operatorInput2(inst);