realign some of the i830 code from the i915

diff --git a/src/mesa/drivers/dri/i915tex/i830_state.c b/src/mesa/drivers/dri/i915tex/i830_state.c
index c0673363f32a23527ba6b6a7f125ddf6f9b2f4a2..812daa65246c5e93811331280d3697fec051d48b 100644 (file)
--- a/src/mesa/drivers/dri/i915tex/i830_state.c
+++ b/src/mesa/drivers/dri/i915tex/i830_state.c
@@ -1042,6 +1042,7 @@ i830_init_packets(struct i830_context *i830)
 
    i830->state.Buffer[I830_DESTREG_DV0] = _3DSTATE_DST_BUF_VARS_CMD;
 
+#if 0
    switch (screen->fbFormat) {
    case DV_PF_565:
       i830->state.Buffer[I830_DESTREG_DV1] = (DSTORG_HORT_BIAS(0x8) |   /* .5 */
@@ -1058,7 +1059,7 @@ i830_init_packets(struct i830_context *i830)
                                               DEPTH_FRMT_24_FIXED_8_OTHER);
       break;
    }
-
+#endif
    i830->state.Buffer[I830_DESTREG_SENABLE] = (_3DSTATE_SCISSOR_ENABLE_CMD |
                                                DISABLE_SCISSOR_RECT);
    i830->state.Buffer[I830_DESTREG_SR0] = _3DSTATE_SCISSOR_RECT_0_CMD;

diff --git a/src/mesa/drivers/dri/i915tex/i830_texstate.c b/src/mesa/drivers/dri/i915tex/i830_texstate.c
index ba79cf94599fc8c712e0c6ac7a5e98bdd2db84e0..e3f34e3944a11374d771aff3f944fd3911a522f9 100644 (file)
--- a/src/mesa/drivers/dri/i915tex/i830_texstate.c
+++ b/src/mesa/drivers/dri/i915tex/i830_texstate.c
@@ -25,21 +25,13 @@
  * 
  **************************************************************************/
 
-#include "glheader.h"
-#include "macros.h"
 #include "mtypes.h"
-#include "simple_list.h"
 #include "enums.h"
 #include "texformat.h"
-#include "texstore.h"
+#include "dri_bufmgr.h"
 
-#include "mm.h"
-
-#include "intel_screen.h"
-#include "intel_ioctl.h"
-#include "intel_tex.h"
 #include "intel_mipmap_tree.h"
-#include "intel_regions.h"
+#include "intel_tex.h"
 
 #include "i830_context.h"
 #include "i830_reg.h"
@@ -129,6 +121,13 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
 
    memset(state, 0, sizeof(state));
 
+   /*We need to refcount these. */
+
+   if (i830->state.tex_buffer[unit] != NULL) {
+       driBOUnReference(i830->state.tex_buffer[unit]);
+       i830->state.tex_buffer[unit] = NULL;
+   }
+
    if (!intel_finalize_mipmap_tree(intel, unit))
       return GL_FALSE;
 
@@ -137,7 +136,7 @@ i830_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3)
     */
    firstImage = tObj->Image[0][intelObj->firstLevel];
 
-   i830->state.tex_buffer[unit] = intelObj->mt->region->buffer;
+   i830->state.tex_buffer[unit] = driBOReference(intelObj->mt->region->buffer);
    i830->state.tex_offset[unit] = intel_miptree_image_offset(intelObj->mt, 0,
                                                              intelObj->
                                                              firstLevel);
@@ -298,10 +297,17 @@ i830UpdateTextureState(struct intel_context *intel)
       case TEXTURE_RECT_BIT:
          ok = i830_update_tex_unit(intel, i, TEXCOORDS_ARE_IN_TEXELUNITS);
          break;
-      case 0:
-         if (i830->state.active & I830_UPLOAD_TEX(i))
+      case 0:{
+        struct i830_context *i830 = i830_context(&intel->ctx);
+         if (i830->state.active & I830_UPLOAD_TEX(i)) 
             I830_ACTIVESTATE(i830, I830_UPLOAD_TEX(i), GL_FALSE);
+
+        if (i830->state.tex_buffer[i] != NULL) {
+           driBOUnReference(i830->state.tex_buffer[i]);
+           i830->state.tex_buffer[i] = NULL;
+        }
          break;
+      }
       case TEXTURE_3D_BIT:
       default:
          ok = GL_FALSE;

diff --git a/src/mesa/drivers/dri/i915tex/i830_vtbl.c b/src/mesa/drivers/dri/i915tex/i830_vtbl.c
index 18fc6d4b91f0c77f0f6cdd1dc54275f763ec6768..dd0670dec37275e8d04fddc40d17ad4ae8c0e1e1 100644 (file)
--- a/src/mesa/drivers/dri/i915tex/i830_vtbl.c
+++ b/src/mesa/drivers/dri/i915tex/i830_vtbl.c
@@ -451,14 +451,16 @@ i830_emit_state(struct intel_context *intel)
       OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]);
       OUT_RELOC(state->draw_region->buffer,
                 DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
-                DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0);
+                DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
+                state->draw_region->draw_offset);
 
       if (state->depth_region) {
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]);
          OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]);
          OUT_RELOC(state->depth_region->buffer,
                    DRM_BO_FLAG_MEM_TT | DRM_BO_FLAG_WRITE,
-                   DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE, 0);
+                   DRM_BO_MASK_MEM | DRM_BO_FLAG_WRITE,
+                   state->depth_region->draw_offset);
       }
 
       OUT_BATCH(state->Buffer[I830_DESTREG_DV0]);
@@ -469,7 +471,7 @@ i830_emit_state(struct intel_context *intel)
       OUT_BATCH(state->Buffer[I830_DESTREG_SR2]);
       ADVANCE_BATCH();
    }
-
+   
    if (dirty & I830_UPLOAD_STIPPLE) {
       DBG("I830_UPLOAD_STIPPLE:\n");
       emit(i830, state->Stipple, sizeof(state->Stipple));