fhdl.ast: fix Switch with constant test.

diff --git a/nmigen/fhdl/ast.py b/nmigen/fhdl/ast.py
index 3455b38835d09d35f3ca16763c0451649ea3e221..77a7ff29794eae3215b1ff69654b8f88b117da29 100644 (file)
--- a/nmigen/fhdl/ast.py
+++ b/nmigen/fhdl/ast.py
@@ -678,9 +678,9 @@ class Switch(Statement):
         self.cases = OrderedDict()
         for key, stmts in cases.items():
             if isinstance(key, (bool, int)):
-                key = "{:0{}b}".format(key, len(test))
+                key = "{:0{}b}".format(key, len(self.test))
             elif isinstance(key, str):
-                assert len(key) == len(test)
+                assert len(key) == len(self.test)
             else:
                 raise TypeError
             if not isinstance(stmts, Iterable):

diff --git a/nmigen/test/test_fhdl_dsl.py b/nmigen/test/test_fhdl_dsl.py
index e28ced6fecd0bc07402bd58a13cfa8a5a5e1284f..f8b109e2665aa3d1086218e76a30c455a977a1d1 100644 (file)
--- a/nmigen/test/test_fhdl_dsl.py
+++ b/nmigen/test/test_fhdl_dsl.py
@@ -263,6 +263,20 @@ class DSLTestCase(FHDLTestCase):
         )
         """)
 
+    def test_Switch_const_test(self):
+        m = Module()
+        with m.Switch(1):
+            with m.Case(1):
+                m.d.comb += self.c1.eq(1)
+        m._flush()
+        self.assertRepr(m._statements, """
+        (
+            (switch (const 1'd1)
+                (case 1 (eq (sig c1) (const 1'd1)))
+            )
+        )
+        """)
+
     def test_Case_width_wrong(self):
         m = Module()
         with m.Switch(self.w1):