//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
-
+
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
+
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
endgenerate
/* End implementation */
assign X = AA ^ BB;
-
-endmodule
+
+endmodule
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
- output Y;
+ output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
- twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
+ twentynm_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
_TECHMAP_REPLACE_ (.combout(Y), .dataa(A[0]), .datab(A[1]), .datac(1'b1),.datad(1'b1), .datae(1'b1), .dataf(1'b1), .datag(1'b1));
end /*else
if(WIDTH == 3) begin
/* Altera Arria 10 GX LUT Primitive */
module twentynm_lcell_comb (output combout, cout, sumout,
- input dataa, datab, datac, datad,
+ input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
/* No clearbox model */
`ifdef NO_CLEARBOX
(* blackbox *)
-module altpll
+module altpll
( inclk,
fbin,
pllena,
c2,
c3,
c4);
-
+
parameter intended_device_family = "MAX 10";
parameter operation_mode = "NORMAL";
parameter pll_type = "AUTO";
input phasestep;
input configupdate;
inout fbmimicbidir;
-
+
output [width_clock-1:0] clk;
output [3:0] extclk;
output fref;
output icdrclk;
output c0, c1, c2, c3, c4;
-
+
endmodule // altpll
`endif
parameter CFG_ABITS = 8;
parameter CFG_DBITS = 36;
- parameter ABITS = "1";
- parameter DBITS = "1";
+ parameter ABITS = "1";
+ parameter DBITS = "1";
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
-
+
input CLK2;
input CLK3;
//Read data
input B1EN;
wire [CFG_DBITS-1:0] B1DATA_t;
-
+
localparam MODE = CFG_DBITS == 1 ? 1:
CFG_DBITS == 2 ? 2:
CFG_DBITS == 4 ? 3:
CFG_DBITS == 32 ? 8:
CFG_DBITS == 36 ? 9:
'bx;
-
+
localparam NUMWORDS = CFG_DBITS == 1 ? 8192:
CFG_DBITS == 2 ? 4096:
CFG_DBITS == 4 ? 2048:
CFG_DBITS == 32 ? 256:
CFG_DBITS == 36 ? 256:
'bx;
-
- altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
- .clock_enable_input_a ("ALTERNATE" ),
- .clock_enable_output_b ("NORMAL" ),
- .clock_enable_output_a ("NORMAL" ),
- .wrcontrol_aclr_a ("NONE" ),
- .indata_aclr_a ("NONE" ),
- .address_aclr_a ("NONE" ),
- .outdata_aclr_a ("NONE" ),
- .outdata_reg_a ("UNREGISTERED"),
- .operation_mode ("SINGLE_PORT" ),
- .intended_device_family ("CYCLONE IVE" ),
- .outdata_reg_a ("UNREGISTERED"),
- .lpm_type ("altsyncram" ),
- .init_type ("unused" ),
+
+ altsyncram #(.clock_enable_input_b ("ALTERNATE" ),
+ .clock_enable_input_a ("ALTERNATE" ),
+ .clock_enable_output_b ("NORMAL" ),
+ .clock_enable_output_a ("NORMAL" ),
+ .wrcontrol_aclr_a ("NONE" ),
+ .indata_aclr_a ("NONE" ),
+ .address_aclr_a ("NONE" ),
+ .outdata_aclr_a ("NONE" ),
+ .outdata_reg_a ("UNREGISTERED"),
+ .operation_mode ("SINGLE_PORT" ),
+ .intended_device_family ("CYCLONE IVE" ),
+ .outdata_reg_a ("UNREGISTERED"),
+ .lpm_type ("altsyncram" ),
+ .init_type ("unused" ),
.ram_block_type ("AUTO" ),
.lpm_hint ("ENABLE_RUNTIME_MOD=NO"), // Forced value
.power_up_uninitialized ("FALSE"),
.read_during_write_mode_port_a ("NEW_DATA_NO_NBE_READ"), // Forced value
.width_byteena_a (1), // Forced value
- .numwords_b ( NUMWORDS ),
- .numwords_a ( NUMWORDS ),
- .widthad_b ( CFG_ABITS ),
- .width_b ( CFG_DBITS ),
- .widthad_a ( CFG_ABITS ),
- .width_a ( CFG_DBITS )
+ .numwords_b ( NUMWORDS ),
+ .numwords_a ( NUMWORDS ),
+ .widthad_b ( CFG_ABITS ),
+ .width_b ( CFG_DBITS ),
+ .widthad_a ( CFG_ABITS ),
+ .width_a ( CFG_DBITS )
) _TECHMAP_REPLACE_ (
.data_a(B1DATA),
.address_a(B1ADDR),
.wren_b(1'b0),
.rden_b(1'b0),
.q_b(1'b0),
- .clock0(CLK2),
+ .clock0(CLK2),
.clock1(1'b1), // Unused in single port mode
.clocken0(1'b1),
.clocken1(1'b1),
.clocken2(1'b1),
.clocken3(1'b1),
- .aclr0(1'b0),
+ .aclr0(1'b0),
.aclr1(1'b0),
.addressstall_a(1'b0),
.addressstall_b(1'b0));
-
+
endmodule
*
*/
(* blackbox *)
-module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
- q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
+module altsyncram(data_a, address_a, wren_a, rden_a, q_a, data_b, address_b, wren_b, rden_b,
+ q_b, clock0, clock1, clocken0, clocken1, clocken2, clocken3, aclr0, aclr1,
addressstall_a, addressstall_b);
-
+
parameter clock_enable_input_b = "ALTERNATE";
parameter clock_enable_input_a = "ALTERNATE";
parameter clock_enable_output_b = "NORMAL";
parameter operation_mode = "SINGLE_PORT";
parameter intended_device_family = "MAX 10 FPGA";
parameter outdata_reg_a = "UNREGISTERED";
- parameter lpm_type = "altsyncram";
+ parameter lpm_type = "altsyncram";
parameter init_type = "unused";
parameter ram_block_type = "AUTO";
parameter lpm_hint = "ENABLE_RUNTIME_MOD=NO";
parameter width_b = 1;
parameter widthad_a = 1;
parameter width_a = 1;
-
+
// Port A declarations
output [35:0] q_a;
input [35:0] data_a;
input addressstall_a;
input addressstall_b;
// TODO: Implement the correct simulation model
-
+
endmodule // altsyncram
// NOTE: This is still WIP.
(* techmap_celltype = "$alu" *)
-/* Uncomment this for LCU????
+/* Uncomment this for LCU????
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
-
+
/* Start implementation */
//cycloneiv_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
/*
endgenerate
/* End implementation */
/*assign X = AA ^ BB;
-
+
endmodule*/
module _80_cycloneiv_alu (A, B, CI, BI, X, Y, CO);
parameter A_SIGNED = 0;
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
-
+
cycloneiv_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
- output Y;
+ output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
endmodule // GND
/* Altera Cyclone IV (GX) devices Input Buffer Primitive */
-module cycloneiv_io_ibuf
+module cycloneiv_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (GX) 4-input non-fracturable LUT Primitive */
-module cycloneiv_lcell_comb
+module cycloneiv_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
endmodule // cycloneiv_lcell_comb
/* Altera D Flip-Flop Primitive */
-module dffeas
+module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
reg q_tmp;
wire reset;
reg [7:0] debug_net;
-
+
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
else q_tmp <= d;
end
assign q = q_tmp;
-
+
endmodule // dffeas
/* Cyclone IV GX altpll clearbox model */
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
- parameter lock_high = 0;
- parameter lock_low = 0;
- parameter lock_window_ui = "0.05";
+ parameter lock_high = 0;
+ parameter lock_low = 0;
+ parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
- parameter vco_post_scale = 1;
+ parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
- parameter loop_filter_r = "1.0";
- parameter loop_filter_c = 0;
+ parameter loop_filter_r = "1.0";
+ parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneiv_pll";
parameter phase_counter_select_width = 3;
-
+
input [1:0] inclk;
input fbin;
input clkswitch;
input scanclkena;
input scandata;
input configupdate;
-
+
output [4:0] clk;
output [1:0] clkbad;
output activeclock;
output vcounderrange;
output fref;
output icdrclk;
-
+
endmodule // cycloneive_pll
wire [Y_WIDTH-1:0] AA = A_buf;
wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf;
wire [Y_WIDTH:0] C = {CO, CI};
-
+
cycloneive_lcell_comb #(.lut_mask(16'b0110_0110_1000_1000), .sum_lutc_input("cin")) carry_start (.cout(CO[0]), .dataa(BB[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
genvar i;
generate for (i = 1; i < Y_WIDTH; i = i + 1) begin:slice
end endgenerate
assign X = AA ^ BB;
-
+
endmodule
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
- output Y;
+ output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
end else
if (WIDTH == 2) begin
- cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
- .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ cycloneive_lcell_comb #(.lut_mask({4{LUT}}),
+ .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(1'b1),
.datad(1'b1));
end else
if(WIDTH == 3) begin
- cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
- .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ cycloneive_lcell_comb #(.lut_mask({2{LUT}}),
+ .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
.datad(1'b1));
end else
if(WIDTH == 4) begin
- cycloneive_lcell_comb #(.lut_mask(LUT),
- .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ cycloneive_lcell_comb #(.lut_mask(LUT),
+ .sum_lutc_input("datac")) _TECHMAP_REPLACE_ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
.datad(A[3]));
end else
wire _TECHMAP_FAIL_ = 1;
endgenerate
-
-endmodule
+
+endmodule
endmodule // GND
/* Altera Cyclone IV (E) devices Input Buffer Primitive */
-module cycloneive_io_ibuf
+module cycloneive_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera Cyclone IV (E) devices Output Buffer Primitive */
-module cycloneive_io_obuf
+module cycloneive_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera Cyclone IV (E) 4-input non-fracturable LUT Primitive */
-module cycloneive_lcell_comb
+module cycloneive_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
endmodule // cycloneive_lcell_comb
/* Altera D Flip-Flop Primitive */
-module dffeas
+module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
reg q_tmp;
wire reset;
reg [7:0] debug_net;
-
+
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
else q_tmp <= d;
end
assign q = q_tmp;
-
+
endmodule // dffeas
/* Cyclone IV E altpll clearbox model */
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
- parameter lock_high = 0;
- parameter lock_low = 0;
- parameter lock_window_ui = "0.05";
+ parameter lock_high = 0;
+ parameter lock_low = 0;
+ parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
- parameter vco_post_scale = 1;
+ parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
- parameter loop_filter_r = "1.0";
- parameter loop_filter_c = 0;
+ parameter loop_filter_r = "1.0";
+ parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "cycloneive_pll";
parameter phase_counter_select_width = 3;
-
+
input [1:0] inclk;
input fbin;
input clkswitch;
output phasedone;
output vcooverrange;
output vcounderrange;
-
+
endmodule // cycloneive_pll
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
-
+
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
+
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
endgenerate
/* End implementation */
assign X = AA ^ BB;
-
-endmodule
+
+endmodule
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
- output Y;
+ output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
- end
+ end
else
if (WIDTH == 2) begin
- cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ cyclonev_lcell_comb #(.lut_mask({16{LUT}}), .shared_arith("off"), .extended_lut("off"))
+ _TECHMAP_REPLACE_
+ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(1'b1),
- .datad(1'b1),
- .datae(1'b1),
- .dataf(1'b1),
+ .datad(1'b1),
+ .datae(1'b1),
+ .dataf(1'b1),
.datag(1'b1));
- end
+ end
else
if(WIDTH == 3) begin
- cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ cyclonev_lcell_comb #(.lut_mask({8{LUT}}), .shared_arith("off"), .extended_lut("off"))
+ _TECHMAP_REPLACE_
+ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
- .datad(1'b1),
- .datae(1'b1),
- .dataf(1'b1),
+ .datad(1'b1),
+ .datae(1'b1),
+ .dataf(1'b1),
.datag(1'b1));
- end
+ end
else
if(WIDTH == 4) begin
- cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ cyclonev_lcell_comb #(.lut_mask({4{LUT}}), .shared_arith("off"), .extended_lut("off"))
+ _TECHMAP_REPLACE_
+ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
- .datad(A[3]),
- .datae(1'b1),
- .dataf(1'b1),
+ .datad(A[3]),
+ .datae(1'b1),
+ .dataf(1'b1),
.datag(1'b1));
- end
+ end
else
- if(WIDTH == 5) begin
+ if(WIDTH == 5) begin
cyclonev_lcell_comb #(.lut_mask({2{LUT}}), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ _TECHMAP_REPLACE_
+ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
- .datad(A[3]),
- .datae(A[4]),
- .dataf(1'b1),
+ .datad(A[3]),
+ .datae(A[4]),
+ .dataf(1'b1),
.datag(1'b1));
- end
+ end
else
if(WIDTH == 6) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ _TECHMAP_REPLACE_
+ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
- .datad(A[3]),
- .datae(A[4]),
- .dataf(A[5]),
+ .datad(A[3]),
+ .datae(A[4]),
+ .dataf(A[5]),
.datag(1'b1));
- end
+ end
else
if(WIDTH == 7) begin
cyclonev_lcell_comb #(.lut_mask(LUT), .shared_arith("off"), .extended_lut("off"))
- _TECHMAP_REPLACE_
- (.combout(Y),
- .dataa(A[0]),
- .datab(A[1]),
+ _TECHMAP_REPLACE_
+ (.combout(Y),
+ .dataa(A[0]),
+ .datab(A[1]),
.datac(A[2]),
- .datad(A[3]),
- .datae(A[4]),
- .dataf(A[5]),
+ .datad(A[3]),
+ .datae(A[4]),
+ .dataf(A[5]),
.datag(A[6]));
- end
+ end
else
wire _TECHMAP_FAIL_ = 1;
endgenerate
endmodule // GND
/* Altera Cyclone V devices Input Buffer Primitive */
-module cyclonev_io_ibuf
+module cyclonev_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // cyclonev_io_ibuf
/* Altera Cyclone V devices Output Buffer Primitive */
-module cyclonev_io_obuf
+module cyclonev_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // cyclonev_io_obuf
/* Altera Cyclone V LUT Primitive */
-module cyclonev_lcell_comb
+module cyclonev_lcell_comb
(output combout, cout, sumout, shareout,
- input dataa, datab, datac, datad,
+ input dataa, datab, datac, datad,
input datae, dataf, datag, cin,
input sharein);
// Extended mode uses mux to define the output
wire mux_0, mux_1;
// Input for hold the shared LUT mode value
- wire shared_lut_alm;
-
+ wire shared_lut_alm;
+
// Simulation model of 4-input LUT
function lut4;
input [15:0] mask;
lut4 = dataa ? s1[1] : s1[0];
end
endfunction // lut4
-
+
// Simulation model of 5-input LUT
function lut5;
input [31:0] mask; // wp-01003.pdf, page 3: "a 5-LUT can be built with two 4-LUTs and a multiplexer.
/* Altera D Flip-Flop Primitive */
-module dffeas
+module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
reg q_tmp;
wire reset;
reg [7:0] debug_net;
-
+
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
else q_tmp <= d;
end
assign q = q_tmp;
-
+
endmodule // dffeas
//wire [Y_WIDTH:0] C = {CO, CI};
wire [Y_WIDTH+1:0] COx;
wire [Y_WIDTH+1:0] C = {COx, CI};
-
+
/* Start implementation */
(* keep *) fiftyfivenm_lcell_comb #(.lut_mask(16'b0000_0000_1010_1010), .sum_lutc_input("cin")) carry_start (.cout(COx[0]), .dataa(C[0]), .datab(1'b1), .datac(1'b1), .datad(1'b1));
-
+
genvar i;
generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice
if(i==Y_WIDTH-1) begin
endgenerate
/* End implementation */
assign X = AA ^ BB;
-
-endmodule
+
+endmodule
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R_i), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(1'b0), .sload(1'b0));
endmodule
-module \$__DFFE_PP0 (input D, C, E, R, output Q);
+module \$__DFFE_PP0 (input D, C, E, R, output Q);
parameter WYSIWYG="TRUE";
wire E_i = ~ E;
dffeas #(.is_wysiwyg(WYSIWYG)) _TECHMAP_REPLACE_ (.d(D), .q(Q), .clk(C), .clrn(R), .prn(1'b1), .ena(1'b1), .asdata(1'b0), .aload(1'b0), .sclr(E_i), .sload(1'b0));
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
- output Y;
+ output Y;
generate
if (WIDTH == 1) begin
assign Y = ~A[0]; // Not need to spend 1 logic cell for such an easy function
endmodule // GND
/* Altera MAX10 devices Input Buffer Primitive */
-module fiftyfivenm_io_ibuf
+module fiftyfivenm_io_ibuf
(output o, input i, input ibar);
assign ibar = ibar;
assign o = i;
endmodule // fiftyfivenm_io_ibuf
/* Altera MAX10 devices Output Buffer Primitive */
-module fiftyfivenm_io_obuf
+module fiftyfivenm_io_obuf
(output o, input i, input oe);
assign o = i;
assign oe = oe;
endmodule // fiftyfivenm_io_obuf
/* Altera MAX10 4-input non-fracturable LUT Primitive */
-module fiftyfivenm_lcell_comb
+module fiftyfivenm_lcell_comb
(output combout, cout,
input dataa, datab, datac, datad, cin);
endmodule // fiftyfivenm_lcell_comb
/* Altera D Flip-Flop Primitive */
-module dffeas
+module dffeas
(output q,
input d, clk, clrn, prn, ena,
input asdata, aload, sclr, sload);
reg q_tmp;
wire reset;
reg [7:0] debug_net;
-
+
assign reset = (prn && sclr && ~clrn && ena);
assign q = q_tmp & 1'b1;
else q_tmp <= d;
end
assign q = q_tmp;
-
+
endmodule // dffeas
/* MAX10 altpll clearbox model */
parameter bandwidth = 0;
parameter bandwidth_type = "auto";
parameter use_dc_coupling = "false";
- parameter lock_high = 0;
- parameter lock_low = 0;
- parameter lock_window_ui = "0.05";
+ parameter lock_high = 0;
+ parameter lock_low = 0;
+ parameter lock_window_ui = "0.05";
parameter test_bypass_lock_detect = "off";
parameter clk0_output_frequency = 0;
parameter clk0_multiply_by = 0;
parameter c4_test_source = -1;
parameter vco_multiply_by = 0;
parameter vco_divide_by = 0;
- parameter vco_post_scale = 1;
+ parameter vco_post_scale = 1;
parameter vco_frequency_control = "auto";
parameter vco_phase_shift_step = 0;
parameter charge_pump_current = 10;
- parameter loop_filter_r = "1.0";
- parameter loop_filter_c = 0;
+ parameter loop_filter_r = "1.0";
+ parameter loop_filter_c = 0;
parameter pll_compensation_delay = 0;
parameter lpm_type = "fiftyfivenm_pll";
parameter phase_counter_select_width = 3;
-
+
input [1:0] inclk;
input fbin;
input clkswitch;
output phasedone;
output vcooverrange;
output vcounderrange;
-
+
endmodule // cycloneive_pll
{
run("synth -run coarse");
}
-
+
if (!nobram && check_label("bram", "(skip if -nobram)"))
{
run("memory_bram -rules +/intel/common/brams.txt");
if (check_label("fine"))
{
- run("opt -fast -mux_undef -undriven -fine -full");
+ run("opt -fast -mux_undef -undriven -fine -full");
run("memory_map");
run("opt -undriven -fine");
run("dffsr2dff");
run("techmap -map +/intel/max10/cells_map.v");
else if(family_opt=="a10gx")
run("techmap -map +/intel/a10gx/cells_map.v");
- else if(family_opt=="cyclonev")
+ else if(family_opt=="cyclonev")
run("techmap -map +/intel/cyclonev/cells_map.v");
else if(family_opt=="cycloneiv")
run("techmap -map +/intel/cycloneiv/cells_map.v");
projects / yosys.git / commitdiff