Make the cached virtPort have a thread context so it can do everything that a newly...

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c75a08213cbc4f65572f9ec84cdb0fa964c0885b..fac214174e6e53a64bff8b0355eb9f144436ff94 100644 (file)
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -788,7 +788,7 @@ FullO3CPU<Impl>::updateMemPorts()
     // Update all ThreadContext's memory ports (Functional/Virtual
     // Ports)
     for (int i = 0; i < thread.size(); ++i)
-        thread[i]->connectMemPorts();
+        thread[i]->connectMemPorts(thread[i]->getTC());
 }
 #endif
 

diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index e7bdc6de58ddb55454ed7b3d44533d533e89b0a9..44e26729cb1e9735d466aecb3f1da94baae0f030 100755 (executable)
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -98,7 +98,7 @@ class O3ThreadContext : public ThreadContext
 
     void delVirtPort(VirtualPort *vp);
 
-    virtual void connectMemPorts() { thread->connectMemPorts(); }
+    virtual void connectMemPorts(ThreadContext *tc) { thread->connectMemPorts(tc); }
 #else
     virtual TranslatingPort *getMemPort() { return thread->getMemPort(); }
 

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index 6b07502efd1b72369d431eafb7cc12edaeb2e68c..0e04a36b25dc6974c3e32c648c49d46c24944b42 100644 (file)
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -148,7 +148,7 @@ AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 #if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
-    cpu->tcBase()->connectMemPorts();
+    cpu->tcBase()->connectMemPorts(cpu->tcBase());
 #endif
 }
 

diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc
index 2cf7d584d0edc7d1db8ec619000fad11705381ef..b86d4b2d7548c6dbd10e5e5ee8642507da4226c7 100644 (file)
--- a/src/cpu/simple/timing.cc
+++ b/src/cpu/simple/timing.cc
@@ -766,7 +766,7 @@ TimingSimpleCPU::DcachePort::setPeer(Port *port)
 #if FULL_SYSTEM
     // Update the ThreadContext's memory ports (Functional/Virtual
     // Ports)
-    cpu->tcBase()->connectMemPorts();
+    cpu->tcBase()->connectMemPorts(cpu->tcBase());
 #endif
 }
 

diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index cf51c1637d9f3dbf2929e7e67a29abae1c6583cb..b25a67d59e35ef15c70213b4de7be03008076b50 100644 (file)
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -134,7 +134,7 @@ class ThreadContext
 
     virtual void delVirtPort(VirtualPort *vp) = 0;
 
-    virtual void connectMemPorts() = 0;
+    virtual void connectMemPorts(ThreadContext *tc) = 0;
 #else
     virtual TranslatingPort *getMemPort() = 0;
 
@@ -325,7 +325,7 @@ class ProxyThreadContext : public ThreadContext
 
     void delVirtPort(VirtualPort *vp) { return actualTC->delVirtPort(vp); }
 
-    void connectMemPorts() { actualTC->connectMemPorts(); }
+    void connectMemPorts(ThreadContext *tc) { actualTC->connectMemPorts(tc); }
 #else
     TranslatingPort *getMemPort() { return actualTC->getMemPort(); }
 

diff --git a/src/cpu/thread_state.cc b/src/cpu/thread_state.cc
index bcfc9c924f077437668a605400ff0d7925422a57..18845baf7b1397bb9aeccd6dd3bac245c40d470c 100644 (file)
--- a/src/cpu/thread_state.cc
+++ b/src/cpu/thread_state.cc
@@ -113,10 +113,10 @@ ThreadState::unserialize(Checkpoint *cp, const std::string &section)
 
 #if FULL_SYSTEM
 void
-ThreadState::connectMemPorts()
+ThreadState::connectMemPorts(ThreadContext *tc)
 {
     connectPhysPort();
-    connectVirtPort();
+    connectVirtPort(tc);
 }
 
 void
@@ -134,7 +134,7 @@ ThreadState::connectPhysPort()
 }
 
 void
-ThreadState::connectVirtPort()
+ThreadState::connectVirtPort(ThreadContext *tc)
 {
     // @todo: For now this disregards any older port that may have
     // already existed.  Fix this memory leak once the bus port IDs
@@ -143,7 +143,7 @@ ThreadState::connectVirtPort()
         virtPort->removeConn();
     else
         virtPort = new VirtualPort(csprintf("%s-%d-vport",
-                                        baseCpu->name(), tid));
+                                        baseCpu->name(), tid), tc);
     connectToMemFunc(virtPort);
 }
 

diff --git a/src/cpu/thread_state.hh b/src/cpu/thread_state.hh
index 4f878db1f207ad5d14ac98fad278f583503342e3..b6a62eebc8122f9c53a36e246ec09ffed54aca25 100644 (file)
--- a/src/cpu/thread_state.hh
+++ b/src/cpu/thread_state.hh
@@ -91,11 +91,11 @@ struct ThreadState {
     Tick readLastSuspend() { return lastSuspend; }
 
 #if FULL_SYSTEM
-    void connectMemPorts();
+    void connectMemPorts(ThreadContext *tc);
 
     void connectPhysPort();
 
-    void connectVirtPort();
+    void connectVirtPort(ThreadContext *tc);
 
     void dumpFuncProfile();
 
@@ -201,7 +201,7 @@ struct ThreadState {
     FunctionalPort *physPort;
 
     /** A functional port, outgoing only, for functional accesse to virtual
-     * addresses. That doen't require execution context information */
+     * addresses. */
     VirtualPort *virtPort;
 #else
     TranslatingPort *port;